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----------------------------------------------------------------------------------
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-- Company: University of Southern Denmark
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-- Company: University of Southern Denmark
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-- Engineer: Simon Falsig
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-- Engineer: Simon Falsig
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--
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--
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-- Create Date: 19/3/2010
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-- Create Date: 19/3/2010
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-- Design Name: uTosNet
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-- Design Name: uTosNet
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-- Module Name: uTosNet_spi - Behavioral
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-- Module Name: uTosNet_spi - Behavioral
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-- File Name: utosnet_spi.vhd
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-- Project Name: uTosNet
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-- Project Name: uTosNet
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-- Target Devices: SDU XC3S50AN Board
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-- Target Devices: SDU XC3S50AN Board
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-- Tool versions: Xilinx ISE 11.4
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-- Tool versions: Xilinx ISE 11.4
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-- Description: PseudoTosNet is designed to provide an interface similar to
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-- Description: PseudoTosNet is designed to provide an interface similar to
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-- the full-blown TosNet core, but usable on the SDU XC3S50AN
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-- the full-blown TosNet core, but usable on the SDU XC3S50AN
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-- Board. It features a SPI module which is made for use in
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-- Board. It features a SPI module which is made for use in
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-- conjunction with a Digi Connect ME 9210 with the Generic
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-- conjunction with a Digi Connect ME 9210 with the Generic
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-- TosNet Masternode application. By using this combination, it
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-- TosNet Masternode application. By using this combination, it
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-- is possible to access the blockram from any Ethernet-enabled
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-- is possible to access the blockram from any Ethernet-enabled
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-- device.
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-- device.
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.10 - Initial release
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-- Revision 0.10 - Initial release
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--
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--
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-- Copyright 2010
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--
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-- This module is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This module is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this module. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity uTosNet_spi is
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entity uTosNet_spi is
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Port ( clk_50M : in STD_LOGIC;
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Port ( clk_50M : in STD_LOGIC;
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spi_miso : out STD_LOGIC;
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spi_miso : out STD_LOGIC;
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spi_mosi : in STD_LOGIC;
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spi_mosi : in STD_LOGIC;
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spi_clk : in STD_LOGIC;
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spi_clk : in STD_LOGIC;
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spi_en : in STD_LOGIC;
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spi_en : in STD_LOGIC;
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dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0);
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dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0);
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dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0);
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dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0);
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dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0);
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dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0);
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dataReg_clk : in STD_LOGIC;
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dataReg_clk : in STD_LOGIC;
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dataReg_writeEnable : in STD_LOGIC);
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dataReg_writeEnable : in STD_LOGIC);
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end uTosNet_spi;
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end uTosNet_spi;
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architecture Behavioral of uTosNet_spi is
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architecture Behavioral of uTosNet_spi is
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component dataRegister
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component dataRegister
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Port ( clka : in STD_LOGIC;
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Port ( clka : in STD_LOGIC;
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wea : in STD_LOGIC_VECTOR(0 downto 0);
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wea : in STD_LOGIC_VECTOR(0 downto 0);
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addra : in STD_LOGIC_VECTOR(5 downto 0);
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addra : in STD_LOGIC_VECTOR(5 downto 0);
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dina : in STD_LOGIC_VECTOR(31 downto 0);
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dina : in STD_LOGIC_VECTOR(31 downto 0);
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douta : out STD_LOGIC_VECTOR(31 downto 0);
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douta : out STD_LOGIC_VECTOR(31 downto 0);
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clkb : in STD_LOGIC;
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clkb : in STD_LOGIC;
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web : in STD_LOGIC_VECTOR(0 downto 0);
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web : in STD_LOGIC_VECTOR(0 downto 0);
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addrb : in STD_LOGIC_VECTOR(5 downto 0);
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addrb : in STD_LOGIC_VECTOR(5 downto 0);
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dinb : in STD_LOGIC_VECTOR(31 downto 0);
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dinb : in STD_LOGIC_VECTOR(31 downto 0);
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doutb : out STD_LOGIC_VECTOR(31 downto 0));
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doutb : out STD_LOGIC_VECTOR(31 downto 0));
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end component;
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end component;
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signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0);
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signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0);
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signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0);
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signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0);
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signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0);
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signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0);
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signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0);
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signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0);
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signal int_dataReg_clk : STD_LOGIC;
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signal int_dataReg_clk : STD_LOGIC;
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signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0);
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signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0);
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signal readData : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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signal readData : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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signal writeAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
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signal writeAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
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signal readAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
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signal readAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
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signal doWrite : STD_LOGIC := '0';
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signal doWrite : STD_LOGIC := '0';
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signal doRead : STD_LOGIC := '0';
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signal doRead : STD_LOGIC := '0';
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signal int_spi_mosi : STD_LOGIC;
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signal int_spi_mosi : STD_LOGIC;
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signal int_spi_clk : STD_LOGIC;
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signal int_spi_clk : STD_LOGIC;
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signal int_spi_en : STD_LOGIC;
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signal int_spi_en : STD_LOGIC;
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signal last_spi_clk : STD_LOGIC;
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signal last_spi_clk : STD_LOGIC;
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signal dataInBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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signal dataInBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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signal dataOutBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
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signal dataOutBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
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signal bitCounter : STD_LOGIC_VECTOR(6 downto 0) := (others => '0');
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signal bitCounter : STD_LOGIC_VECTOR(6 downto 0) := (others => '0');
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begin
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begin
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dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:)
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dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:)
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dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister
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dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister
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Port map ( clka => dataReg_clk, --PortA is used for the user application
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Port map ( clka => dataReg_clk, --PortA is used for the user application
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wea => dataReg_writeEnable_V, --
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wea => dataReg_writeEnable_V, --
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addra => dataReg_addr, --
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addra => dataReg_addr, --
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dina => dataReg_dataIn, --
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dina => dataReg_dataIn, --
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douta => dataReg_dataOut, --
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douta => dataReg_dataOut, --
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clkb => int_dataReg_clk, --PortB is used for the SPI interface
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clkb => int_dataReg_clk, --PortB is used for the SPI interface
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web => int_dataReg_we, --
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web => int_dataReg_we, --
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addrb => int_dataReg_addr, --
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addrb => int_dataReg_addr, --
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dinb => int_dataReg_dataIn, --
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dinb => int_dataReg_dataIn, --
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doutb => int_dataReg_dataOut); --
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doutb => int_dataReg_dataOut); --
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--Synchronize inputs
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--Synchronize inputs
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process(clk_50M)
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process(clk_50M)
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begin
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begin
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if(clk_50M = '0' and clk_50M'event) then
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if(clk_50M = '0' and clk_50M'event) then
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int_spi_mosi <= spi_mosi;
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int_spi_mosi <= spi_mosi;
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int_spi_clk <= spi_clk;
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int_spi_clk <= spi_clk;
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int_spi_en <= spi_en;
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int_spi_en <= spi_en;
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end if;
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end if;
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end process;
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end process;
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--SPI Process
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--SPI Process
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process(clk_50M)
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process(clk_50M)
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begin
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begin
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if(clk_50M = '1' and clk_50M'event) then
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if(clk_50M = '1' and clk_50M'event) then
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last_spi_clk <= int_spi_clk; --Save current value to use for manual edge triggering
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last_spi_clk <= int_spi_clk; --Save current value to use for manual edge triggering
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if(int_spi_en = '1') then --SPI is not enabled (spi_en is active low)
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if(int_spi_en = '1') then --SPI is not enabled (spi_en is active low)
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bitCounter <= (others => '0'); --Reset the bitcounter
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bitCounter <= (others => '0'); --Reset the bitcounter
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if((doWrite = '1') and (int_dataReg_we = "0")) then --If a write was requested in the previously received command,
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if((doWrite = '1') and (int_dataReg_we = "0")) then --If a write was requested in the previously received command,
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int_dataReg_addr <= writeAddress; -- then prepare it,
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int_dataReg_addr <= writeAddress; -- then prepare it,
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int_dataReg_dataIn <= dataInBuffer; -- the data to write are those left in the input buffer,
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int_dataReg_dataIn <= dataInBuffer; -- the data to write are those left in the input buffer,
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int_dataReg_we <= "1"; --
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int_dataReg_we <= "1"; --
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int_dataReg_clk <= '0'; --
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int_dataReg_clk <= '0'; --
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elsif((doWrite = '1') and (int_dataReg_clk = '0')) then --
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elsif((doWrite = '1') and (int_dataReg_clk = '0')) then --
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int_dataReg_clk <= '1'; -- and perform it by pulling the dataReg clock high
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int_dataReg_clk <= '1'; -- and perform it by pulling the dataReg clock high
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doWrite <= '0'; --Write is done
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doWrite <= '0'; --Write is done
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else --If there aren't any writes to perform,
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else --If there aren't any writes to perform,
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int_dataReg_clk <= '0'; -- just clear the various signals
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int_dataReg_clk <= '0'; -- just clear the various signals
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int_dataReg_we <= "0"; --
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int_dataReg_we <= "0"; --
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doRead <= '0'; --
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doRead <= '0'; --
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doWrite <= '0'; --
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doWrite <= '0'; --
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end if;
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end if;
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else --SPI is enabled
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else --SPI is enabled
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if(int_spi_clk = '0' and last_spi_clk = '1') then --Falling edge on spi_clk
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if(int_spi_clk = '0' and last_spi_clk = '1') then --Falling edge on spi_clk
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dataInBuffer <= dataInBuffer(30 downto 0) & int_spi_mosi; --Read next received bit into the input buffer,
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dataInBuffer <= dataInBuffer(30 downto 0) & int_spi_mosi; --Read next received bit into the input buffer,
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bitCounter <= bitCounter + 1; -- and increment the bitcounter
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bitCounter <= bitCounter + 1; -- and increment the bitcounter
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elsif(int_spi_clk = '1' and last_spi_clk = '0') then --Rising edge on spi_clk
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elsif(int_spi_clk = '1' and last_spi_clk = '0') then --Rising edge on spi_clk
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spi_miso <= dataOutBuffer(31); --Write out the next bit from the output buffer,
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spi_miso <= dataOutBuffer(31); --Write out the next bit from the output buffer,
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dataOutBuffer <= dataOutBuffer(30 downto 0) & '0'; -- and left-shift the buffer
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dataOutBuffer <= dataOutBuffer(30 downto 0) & '0'; -- and left-shift the buffer
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end if;
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end if;
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case bitCounter is --Parse the command
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case bitCounter is --Parse the command
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when "0000101" => --Bit 27 (the 5th read bit),
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when "0000101" => --Bit 27 (the 5th read bit),
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doRead <= dataInBuffer(0); -- contains the 'doRead' flag
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doRead <= dataInBuffer(0); -- contains the 'doRead' flag
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when "0010000" => --Bits 16-25 (available when 16 bits have been read),
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when "0010000" => --Bits 16-25 (available when 16 bits have been read),
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readAddress <= dataInBuffer(5 downto 0); -- contain the address to read from
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readAddress <= dataInBuffer(5 downto 0); -- contain the address to read from
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when "0010001" => --Bit 15 (the 17th read bit),
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when "0010001" => --Bit 15 (the 17th read bit),
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int_dataReg_addr <= readAddress; -- doesn't contain anything useful, but we can easily use the timeslot for reading from the dataregister
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int_dataReg_addr <= readAddress; -- doesn't contain anything useful, but we can easily use the timeslot for reading from the dataregister
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int_dataReg_we <= "0"; --
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int_dataReg_we <= "0"; --
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int_dataReg_clk <= '0'; --
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int_dataReg_clk <= '0'; --
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when "0010010" => --Bit 14 (the 18th read bit),
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when "0010010" => --Bit 14 (the 18th read bit),
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int_dataReg_clk <= '1'; -- still nothing, now performing the read by pulling the dataregister clock high
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int_dataReg_clk <= '1'; -- still nothing, now performing the read by pulling the dataregister clock high
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when "0010011" => --Bit 13 (the 19th read bit),
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when "0010011" => --Bit 13 (the 19th read bit),
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int_dataReg_clk <= '0'; -- the read is finished,
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int_dataReg_clk <= '0'; -- the read is finished,
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readData <= int_dataReg_dataOut; -- and the read value is stored
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readData <= int_dataReg_dataOut; -- and the read value is stored
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when "0010101" => --Bit 11 (the 21st read bit),
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when "0010101" => --Bit 11 (the 21st read bit),
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doWrite <= dataInBuffer(0); -- contains the 'doWrite' flag
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doWrite <= dataInBuffer(0); -- contains the 'doWrite' flag
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when "0011111" => --Bit 1 (the 31st read bit),
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when "0011111" => --Bit 1 (the 31st read bit),
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if(doRead = '1') then -- we're not using this bit for anything right now, but we need to put the previously read data value into the output buffer now
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if(doRead = '1') then -- we're not using this bit for anything right now, but we need to put the previously read data value into the output buffer now
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dataOutBuffer <= readData; --
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dataOutBuffer <= readData; --
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else --If a read was not requested,
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else --If a read was not requested,
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dataOutBuffer <= (others => '0'); -- the output buffer is just filled with zeros instead
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dataOutBuffer <= (others => '0'); -- the output buffer is just filled with zeros instead
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end if;
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end if;
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when "0100000" => --Bits 9-0 (available when 32 bits have been read),
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when "0100000" => --Bits 9-0 (available when 32 bits have been read),
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writeAddress <= dataInBuffer(5 downto 0); -- contain the address to write to
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writeAddress <= dataInBuffer(5 downto 0); -- contain the address to write to
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when others => --Other bit positions are ignored
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when others => --Other bit positions are ignored
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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