library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 8 bit processor status register P
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-- 8 bit processor status register P
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-- NV1BDIZC
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-- NV1BDIZC
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-- 76543210
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-- 76543210
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-- ||||||||
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-- ||||||||
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-- ||||||||--- C = carry/borrow flag
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-- ||||||||--- C = carry/borrow flag
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-- |||||||---- Z = zero flag
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-- |||||||---- Z = zero flag
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-- ||||||----- I = interrupt mask
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-- ||||||----- I = interrupt mask
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-- |||||------ D = decimal/binary alu mode
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-- |||||------ D = decimal/binary alu mode
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-- ||||------- B = break opcode flag
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-- ||||------- B = break opcode flag
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-- |||-------- 1 = always "1'
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-- |||-------- 1 = always "1'
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-- ||--------- V = overflow flag
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-- ||--------- V = overflow flag
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-- |---------- N = negative flag
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-- |---------- N = negative flag
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entity pr is
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entity pr is
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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clr: in STD_LOGIC; -- clear
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clr: in STD_LOGIC; -- clear
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fwait: in STD_LOGIC;
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fwait: in STD_LOGIC;
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n: in STD_LOGIC; -- N input
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n: in STD_LOGIC; -- N input
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v: in STD_LOGIC; -- V input
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v: in STD_LOGIC; -- V input
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z: in STD_LOGIC; -- Z input
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z: in STD_LOGIC; -- Z input
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c: in STD_LOGIC; -- C input
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c: in STD_LOGIC; -- C input
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b: in STD_LOGIC; -- B input
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b: in STD_LOGIC; -- B input
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sv: in STD_LOGIC; -- set overflow (by external pin SO)
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sv: in STD_LOGIC; -- set overflow (by external pin SO)
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acr_in: in STD_LOGIC; -- auxiliary carry in
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acr_in: in STD_LOGIC; -- auxiliary carry in
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fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
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fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
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dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
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acr_out: out STD_LOGIC -- auxiliary carry out
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acr_out: out STD_LOGIC -- auxiliary carry out
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);
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);
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end pr;
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end pr;
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architecture rtl of pr is
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architecture rtl of pr is
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constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
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constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
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constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
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constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
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constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NVZC load
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constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NZ load
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constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 => C
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constant FLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- NZC load
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constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- 0 => C
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constant FLV_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- NVZC load
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constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => I
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constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => C
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constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => I
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constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => C
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constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => D
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constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => I
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constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => D
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constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => I
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constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => V
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constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- 1 => D
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constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- auc => ACR
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constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => D
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constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- hold ACR
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constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- 0 => V
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constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- 1 => I/D
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constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- auc => ACR
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constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Z load
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constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- hold ACR
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constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- 1 => I/D
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constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- Z load
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signal reg: STD_LOGIC_VECTOR(7 downto 0);
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signal reg: STD_LOGIC_VECTOR(7 downto 0);
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signal acr: STD_LOGIC; -- carry/borrow used for effectve address calculation
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signal acr: STD_LOGIC; -- carry/borrow used for effectve address calculation
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signal i_so: STD_LOGIC;
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signal i_so: STD_LOGIC;
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begin
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begin
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i_so <= reg(6) when sv = '1' else '1'; -- logic for external pin SO
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i_so <= reg(6) when sv = '1' else '1'; -- logic for external pin SO
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process(clk)
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process(clk)
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begin
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begin
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if (clk'event and clk = '1') then
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if (clk'event and clk = '1') then
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if fwait = '1' then
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if fwait = '1' then
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reg <= reg;
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reg <= reg;
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else
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else
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if clr = '1' then
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if clr = '1' then
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reg <= "00100100";
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reg <= "00100100";
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acr <= '0';
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acr <= '0';
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else
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else
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case fc is
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case fc is
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when PLD_P => reg(7 downto 6) <= din(7 downto 6); -- load NV1BDIZC
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when PLD_P => reg(7 downto 6) <= din(7 downto 6); -- load NV1BDIZC
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reg(5) <= '1';
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reg(5) <= '1';
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reg(4 downto 0) <= din(4 downto 0);
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reg(4 downto 0) <= din(4 downto 0);
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acr <= '0';
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acr <= '0';
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when FLD_P => reg <= n & v & '1' & reg(4 downto 2) & z & c; -- load NVZC
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when FLD_P => reg <= n & reg(6) & '1' & reg(4 downto 2) & z & reg(0); -- load NZ
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acr <= '0';
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when FLC_P => reg <= n & reg(6) & '1' & reg(4 downto 2) & z & c; -- load NZC
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acr <= '0';
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when FLV_P => reg <= n & v & '1' & reg(4 downto 2) & z & c; -- load NZCV
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acr <= '0';
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acr <= '0';
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when SEC_P => reg <= reg or "00000001"; -- 1 => C
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when SEC_P => reg <= reg or "00000001"; -- 1 => C
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acr <= acr;
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acr <= acr;
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when CLC_P => reg <= reg and "11111110"; -- 0 => C
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when CLC_P => reg <= reg and "11111110"; -- 0 => C
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acr <= acr;
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acr <= acr;
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when CLI_P => reg <= reg and "11111011"; -- 0 => I
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when CLI_P => reg <= reg and "11111011"; -- 0 => I
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acr <= acr;
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acr <= acr;
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when SED_P => reg <= reg or "00001000"; -- 1 => D
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when SED_P => reg <= reg or "00001000"; -- 1 => D
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acr <= acr;
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acr <= acr;
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when CLD_P => reg <= reg and "11110111"; -- 0 => D
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when CLD_P => reg <= reg and "11110111"; -- 0 => D
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acr <= acr;
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acr <= acr;
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when LDZ_P => reg(1) <= z; -- z => Z
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when LDZ_P => reg(1) <= z; -- z => Z
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reg(7 downto 2) <= reg(7 downto 2);
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reg(7 downto 2) <= reg(7 downto 2);
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reg(0) <= reg(0);
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reg(0) <= reg(0);
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when SEI_P => reg(7 downto 5) <= reg(7 downto 5);
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when SEI_P => reg(7 downto 5) <= reg(7 downto 5);
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reg(4) <= reg(4);
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reg(4) <= reg(4);
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reg(3) <= reg(3);
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reg(3) <= reg(3);
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reg(2) <= '1'; -- 1 => I
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reg(2) <= '1'; -- 1 => I
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reg(1 downto 0) <= reg(1 downto 0);
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reg(1 downto 0) <= reg(1 downto 0);
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acr <= acr;
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acr <= acr;
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when SID_P => reg(7 downto 5) <= reg(7 downto 5); -- set I and clear D decimal flag (used by interrupt sequence)
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when SID_P => reg(7 downto 5) <= reg(7 downto 5); -- set I and clear D decimal flag (used by interrupt sequence)
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reg(4) <= b; -- 1 => B (if BRK)
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reg(4) <= b; -- 1 => B (if BRK)
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reg(3) <= '0'; -- 0 -> D
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reg(3) <= '0'; -- 0 -> D
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reg(2) <= '1'; -- 1 => I
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reg(2) <= '1'; -- 1 => I
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reg(1 downto 0) <= reg(1 downto 0);
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reg(1 downto 0) <= reg(1 downto 0);
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acr <= acr;
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acr <= acr;
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when CLV_P => reg <= reg and "10111111"; -- 0 => V
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when CLV_P => reg <= reg and "10111111"; -- 0 => V
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acr <= acr;
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acr <= acr;
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when AUC_P => acr <= acr_in; -- store auxiliary carry (ACR)
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when AUC_P => acr <= acr_in; -- store auxiliary carry (ACR)
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reg <= reg;
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reg <= reg;
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when HAC_P => acr <= acr; -- holds auxiliary carry (ACR)
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when HAC_P => acr <= acr; -- holds auxiliary carry (ACR)
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reg <= reg;
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reg <= reg;
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when others => reg(7) <= reg(7);
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when others => reg(7) <= reg(7);
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reg(6) <= i_so; -- set overflow by pin SO
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reg(6) <= i_so; -- set overflow by pin SO
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reg(5 downto 0) <= reg(5 downto 0);
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reg(5 downto 0) <= reg(5 downto 0);
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acr <= '0';
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acr <= '0';
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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dout <= reg;
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dout <= reg;
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acr_out <= acr;
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acr_out <= acr;
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end rtl;
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end rtl;
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