----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- 8 bit microprocessor (65C02) with some enhances VHDL project --
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-- 8 bit microprocessor (65C02) with some enhances VHDL project --
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-- Full RTL synchronous pipelined architecture --
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-- Full RTL synchronous pipelined architecture --
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-- Project by Valerio Venturi (Italy) --
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-- Project by Valerio Venturi (Italy) --
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-- Date: 14/04/2011 --
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-- Date: 14/04/2011 --
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-- Last revision: 05/05/2011 --
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-- Last revision: 19/04/2020 --
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- NOTE:
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-- in this version I made some changes on the pr.vhd and mcpla.vhd files because some instructions changed the V flag by mistake
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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use IEEE.STD_LOGIC_arith.all;
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-- global architecture
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-- global architecture
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entity v6502 is
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entity v6502 is
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port( clk0: in STD_LOGIC; -- PHASE0 clock input
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port( clk0: in STD_LOGIC; -- PHASE0 clock input
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res: in STD_LOGIC; -- reset input
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res: in STD_LOGIC; -- reset input
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irq: in STD_LOGIC; -- interrupt request input
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irq: in STD_LOGIC; -- interrupt request input
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nmi: in STD_LOGIC; -- not maskable interrupt input
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nmi: in STD_LOGIC; -- not maskable interrupt input
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rdy: in STD_LOGIC; -- wait state input (read/write)
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rdy: in STD_LOGIC; -- wait state input (read/write)
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so: in STD_LOGIC; -- set overflow V input
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so: in STD_LOGIC; -- set overflow V input
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rw: out STD_LOGIC; -- read/write out
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rw: out STD_LOGIC; -- read/write out
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sync: out STD_LOGIC; -- opcode fetch out
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sync: out STD_LOGIC; -- opcode fetch out
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vp: out STD_LOGIC; -- vector pull
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vp: out STD_LOGIC; -- vector pull
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ope: out STD_LOGIC; -- microcode end
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ope: out STD_LOGIC; -- microcode end
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addr: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit address bus out
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addr: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit address bus out
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data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus
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data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus
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data_out: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit output data bus
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data_out: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit output data bus
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);
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);
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end v6502;
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end v6502;
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architecture struct of v6502 is
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architecture struct of v6502 is
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signal i_res: STD_LOGIC; -- internal global reset RES
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signal i_res: STD_LOGIC; -- internal global reset RES
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signal i_irq: STD_LOGIC; -- internal interrupt request IRQ
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signal i_irq: STD_LOGIC; -- internal interrupt request IRQ
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signal i_nmi: STD_LOGIC; -- internal interrupt request NMI
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signal i_nmi: STD_LOGIC; -- internal interrupt request NMI
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signal i_rdy: STD_LOGIC; -- internal wait request RDY
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signal i_rdy: STD_LOGIC; -- internal wait request RDY
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signal i_so: STD_LOGIC; -- internal set overflow SO
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signal i_so: STD_LOGIC; -- internal set overflow SO
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signal i_vp: STD_LOGIC; -- internal VP (vector pull)
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signal i_vp: STD_LOGIC; -- internal VP (vector pull)
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signal int: STD_LOGIC; -- internal global interrupt (instruction boundary synchronized)
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signal int: STD_LOGIC; -- internal global interrupt (instruction boundary synchronized)
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signal we: STD_LOGIC; -- write enable (combinatorial from PLA)
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signal we: STD_LOGIC; -- write enable (combinatorial from PLA)
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signal we_r: STD_LOGIC; -- write enable (registered)
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signal we_r: STD_LOGIC; -- write enable (registered)
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signal ien: STD_LOGIC; -- interrupt IRQ enable
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signal ien: STD_LOGIC; -- interrupt IRQ enable
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-- microcode signals (register control)
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-- microcode signals (register control)
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signal regop: STD_LOGIC_VECTOR(3 downto 0); -- register operation microcode
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signal regop: STD_LOGIC_VECTOR(3 downto 0); -- register operation microcode
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signal rsel: STD_LOGIC_VECTOR(3 downto 0); -- register select microcode
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signal rsel: STD_LOGIC_VECTOR(3 downto 0); -- register select microcode
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signal a_l: STD_LOGIC; -- A load
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signal a_l: STD_LOGIC; -- A load
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signal x_l: STD_LOGIC; -- X load
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signal x_l: STD_LOGIC; -- X load
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signal y_l: STD_LOGIC; -- Y load
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signal y_l: STD_LOGIC; -- Y load
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signal z_l: STD_LOGIC; -- Y load
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signal z_l: STD_LOGIC; -- Y load
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signal p_l: STD_LOGIC; -- P load
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signal p_l: STD_LOGIC; -- P load
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signal o_l: STD_LOGIC; -- OPE load
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signal o_l: STD_LOGIC; -- OPE load
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signal sp_ll: STD_LOGIC; -- SP load lsb
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signal sp_ll: STD_LOGIC; -- SP load lsb
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signal sp_lh: STD_LOGIC; -- SP load msb
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signal sp_lh: STD_LOGIC; -- SP load msb
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signal sp_u: STD_LOGIC; -- SP increment
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signal sp_u: STD_LOGIC; -- SP increment
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signal sp_d: STD_LOGIC; -- SP decrement
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signal sp_d: STD_LOGIC; -- SP decrement
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signal dmux_sel: STD_LOGIC_VECTOR(1 downto 0); -- ALU operand #2 data multiplexer
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signal dmux_sel: STD_LOGIC_VECTOR(1 downto 0); -- ALU operand #2 data multiplexer
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-- microcode signals (ALU control)
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-- microcode signals (ALU control)
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signal aluop: STD_LOGIC_VECTOR(4 downto 0); -- ALU operation code
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signal aluop: STD_LOGIC_VECTOR(4 downto 0); -- ALU operation code
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-- microcode signals CPU control logic
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-- microcode signals CPU control logic
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signal opfetch: STD_LOGIC; -- opcode fetch
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signal opfetch: STD_LOGIC; -- opcode fetch
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signal i_sync: STD_LOGIC; -- internal SYNC not latched
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signal i_sync: STD_LOGIC; -- internal SYNC not latched
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signal m_sync: STD_LOGIC; -- internal SYNC latched
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signal m_sync: STD_LOGIC; -- internal SYNC latched
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signal opdec: STD_LOGIC; -- opcode decode
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signal opdec: STD_LOGIC; -- opcode decode
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signal pcmp: STD_LOGIC_VECTOR(1 downto 0); -- PC/MP out control effective
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signal pcmp: STD_LOGIC_VECTOR(1 downto 0); -- PC/MP out control effective
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signal pcmp_mc: STD_LOGIC_VECTOR(1 downto 0); -- PC/MP out control microcode
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signal pcmp_mc: STD_LOGIC_VECTOR(1 downto 0); -- PC/MP out control microcode
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signal pcinc: STD_LOGIC; -- PC increment
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signal pcinc: STD_LOGIC; -- PC increment
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signal e_eop: STD_LOGIC; -- early microcode sequence end (for some opcodes)
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signal e_eop: STD_LOGIC; -- early microcode sequence end (for some opcodes)
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signal mc_eop: STD_LOGIC; -- microcode sequence end (for some opcodes)
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signal mc_eop: STD_LOGIC; -- microcode sequence end (for some opcodes)
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signal eop: STD_LOGIC; -- microcode sequence end (effective)
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signal eop: STD_LOGIC; -- microcode sequence end (effective)
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signal we_mc: STD_LOGIC; -- microcode write enable
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signal we_mc: STD_LOGIC; -- microcode write enable
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signal we_mc_l: STD_LOGIC; -- microcode write enable to latch
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signal we_mc_l: STD_LOGIC; -- microcode write enable to latch
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signal fbrk: STD_LOGIC; -- force BRK opcode (used by hardware interrupts)
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signal fbrk: STD_LOGIC; -- force BRK opcode (used by hardware interrupts)
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signal opbrk: STD_LOGIC; -- BRK opcode (used for distinguish between hardware/software interrupts)
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signal opbrk: STD_LOGIC; -- BRK opcode (used for distinguish between hardware/software interrupts)
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signal bcf: STD_LOGIC; -- branch condition resolved
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signal bcf: STD_LOGIC; -- branch condition resolved
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signal pcc: STD_LOGIC; -- PC carry
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signal pcc: STD_LOGIC; -- PC carry
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signal clri: STD_LOGIC; -- clear interrupt request pending microcode
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signal clri: STD_LOGIC; -- clear interrupt request pending microcode
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signal vso: STD_LOGIC; -- SO input high to low edge flag
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signal vso: STD_LOGIC; -- SO input high to low edge flag
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signal mc_branch: STD_LOGIC; -- branch (relative) opcode
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signal mc_branch: STD_LOGIC; -- branch (relative) opcode
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signal adc_sbc_mc: STD_LOGIC; -- ADC/SBC opcode (used for decimal adjustment)
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signal adc_sbc_mc: STD_LOGIC; -- ADC/SBC opcode (used for decimal adjustment)
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signal ai_op: STD_LOGIC; -- opcode with absolute indexed addressing mode
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signal ai_op: STD_LOGIC; -- opcode with absolute indexed addressing mode
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signal daa_req: STD_LOGIC; -- DAA required
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signal daa_req: STD_LOGIC; -- DAA required
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signal mcad: STD_LOGIC_VECTOR(10 downto 0); -- microcode address
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signal mcad: STD_LOGIC_VECTOR(10 downto 0); -- microcode address
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signal mcscan: STD_LOGIC_VECTOR(2 downto 0); -- microcode pointer control
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signal mcscan: STD_LOGIC_VECTOR(2 downto 0); -- microcode pointer control
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signal p_op: STD_LOGIC_VECTOR(3 downto 0); -- microcode control bits register P
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signal p_op: STD_LOGIC_VECTOR(3 downto 0); -- microcode control bits register P
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signal pcr_fc: STD_LOGIC_VECTOR(2 downto 0); -- microcode control PC
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signal pcr_fc: STD_LOGIC_VECTOR(2 downto 0); -- microcode control PC
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signal mpr_fc: STD_LOGIC_VECTOR(3 downto 0); -- microcode control MP
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signal mpr_fc: STD_LOGIC_VECTOR(3 downto 0); -- microcode control MP
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signal mcbit: STD_LOGIC_VECTOR(34 downto 0); -- microcode control bits
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signal mcbit: STD_LOGIC_VECTOR(34 downto 0); -- microcode control bits
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signal regbit: STD_LOGIC_VECTOR(8 downto 0); -- microcode control bits
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signal regbit: STD_LOGIC_VECTOR(8 downto 0); -- microcode control bits
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signal ivoffs: STD_LOGIC_VECTOR(2 downto 0); -- microcode interrupt vector offset encoding
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signal ivoffs: STD_LOGIC_VECTOR(2 downto 0); -- microcode interrupt vector offset encoding
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signal mcn: STD_LOGIC; -- microcode does NOPs
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signal mcn: STD_LOGIC; -- microcode does NOPs
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signal add_sub_op: STD_LOGIC; -- ADC/SBC opcode
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signal add_sub_op: STD_LOGIC; -- ADC/SBC opcode
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-- ALU signals
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-- ALU signals
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signal bcd: STD_LOGIC; -- ALU binary/bcd mode
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signal bcd: STD_LOGIC; -- ALU binary/bcd mode
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signal c_flg: STD_LOGIC; -- ALU carry flag
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signal c_flg: STD_LOGIC; -- ALU carry flag
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signal z_flg: STD_LOGIC; -- ALU zero flag
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signal z_flg: STD_LOGIC; -- ALU zero flag
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signal v_flg: STD_LOGIC; -- ALU overflow flag
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signal v_flg: STD_LOGIC; -- ALU overflow flag
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signal n_flg: STD_LOGIC; -- ALU negative flag
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signal n_flg: STD_LOGIC; -- ALU negative flag
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signal pc_c_alu_flg: STD_LOGIC; -- ALU PC carry flag
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signal pc_c_alu_flg: STD_LOGIC; -- ALU PC carry flag
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signal acr_reg: STD_LOGIC; -- ALU auxiliary carry (registered)
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signal acr_reg: STD_LOGIC; -- ALU auxiliary carry (registered)
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signal bcd_lsb: STD_LOGIC; -- bcd lsb overflow flag
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signal bcd_lsb: STD_LOGIC; -- bcd lsb overflow flag
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signal bcd_msb: STD_LOGIC; -- bcd msb overflow flag
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signal bcd_msb: STD_LOGIC; -- bcd msb overflow flag
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signal branch_neg: STD_LOGIC; -- branch negative offset flag
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signal branch_neg: STD_LOGIC; -- branch negative offset flag
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-- bus
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-- bus
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signal dbin: STD_LOGIC_VECTOR(7 downto 0); -- input data bus D0..D7
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signal dbin: STD_LOGIC_VECTOR(7 downto 0); -- input data bus D0..D7
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signal dbout: STD_LOGIC_VECTOR(7 downto 0); -- output data bus D0..D7
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signal dbout: STD_LOGIC_VECTOR(7 downto 0); -- output data bus D0..D7
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signal a_bus: STD_LOGIC_VECTOR(7 downto 0); -- accumulator register A bus
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signal a_bus: STD_LOGIC_VECTOR(7 downto 0); -- accumulator register A bus
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signal x_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register X bus
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signal x_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register X bus
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signal y_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register Y bus
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signal y_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register Y bus
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signal z_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register Z bus
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signal z_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register Z bus
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signal sp_bus: STD_LOGIC_VECTOR(15 downto 0); -- stack pointer register S bus
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signal sp_bus: STD_LOGIC_VECTOR(15 downto 0); -- stack pointer register S bus
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signal p_bus: STD_LOGIC_VECTOR(7 downto 0); -- status register P bus
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signal p_bus: STD_LOGIC_VECTOR(7 downto 0); -- status register P bus
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signal op_bus: STD_LOGIC_VECTOR(7 downto 0); -- opcode register bus
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signal op_bus: STD_LOGIC_VECTOR(7 downto 0); -- opcode register bus
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signal o_bus: STD_LOGIC_VECTOR(7 downto 0); -- operand register bus
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signal o_bus: STD_LOGIC_VECTOR(7 downto 0); -- operand register bus
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signal bcd_bus: STD_LOGIC_VECTOR(7 downto 0); -- bcd constants bus (used for decimal adjustement)
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signal bcd_bus: STD_LOGIC_VECTOR(7 downto 0); -- bcd constants bus (used for decimal adjustement)
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signal oper_bus: STD_LOGIC_VECTOR(7 downto 0); -- operand bus (ALU operand #2 bus)
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signal oper_bus: STD_LOGIC_VECTOR(7 downto 0); -- operand bus (ALU operand #2 bus)
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signal r_bus: STD_LOGIC_VECTOR(7 downto 0); -- general register bus (ALU operand #2 bus)
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signal r_bus: STD_LOGIC_VECTOR(7 downto 0); -- general register bus (ALU operand #2 bus)
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signal alu_bus: STD_LOGIC_VECTOR(7 downto 0); -- ALU output bus
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signal alu_bus: STD_LOGIC_VECTOR(7 downto 0); -- ALU output bus
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signal pc_bus: STD_LOGIC_VECTOR(15 downto 0); -- program counter register PC bus
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signal pc_bus: STD_LOGIC_VECTOR(15 downto 0); -- program counter register PC bus
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signal mp_bus: STD_LOGIC_VECTOR(15 downto 0); -- memory pointer register PC bus
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signal mp_bus: STD_LOGIC_VECTOR(15 downto 0); -- memory pointer register PC bus
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signal ad_bus: STD_LOGIC_VECTOR(15 downto 0); -- address bus
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signal ad_bus: STD_LOGIC_VECTOR(15 downto 0); -- address bus
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-- 16 bit program counter register (PC)
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-- 16 bit program counter register (PC)
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component pcr
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component pcr
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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i: in STD_LOGIC; -- increment
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i: in STD_LOGIC; -- increment
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fwait: in STD_LOGIC; -- wait
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fwait: in STD_LOGIC; -- wait
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fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
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fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
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din1: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din1: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din2: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din2: in STD_LOGIC_VECTOR(7 downto 0); -- input
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dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
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);
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);
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end component;
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end component;
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-- 16 bit memory pointer register (MP)
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-- 16 bit memory pointer register (MP)
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component mpr
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component mpr
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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fwait: in STD_LOGIC; -- wait
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fwait: in STD_LOGIC; -- wait
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c: in STD_LOGIC; -- carry input
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c: in STD_LOGIC; -- carry input
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fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
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fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
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din_l: in STD_LOGIC_VECTOR(7 downto 0); -- input LSB
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din_l: in STD_LOGIC_VECTOR(7 downto 0); -- input LSB
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din_h: in STD_LOGIC_VECTOR(7 downto 0); -- input MSB
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din_h: in STD_LOGIC_VECTOR(7 downto 0); -- input MSB
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zp: in STD_LOGIC_VECTOR(7 downto 0); -- input zero bage register Z
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zp: in STD_LOGIC_VECTOR(7 downto 0); -- input zero bage register Z
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v: in STD_LOGIC_VECTOR(2 downto 0); -- vector offset input
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v: in STD_LOGIC_VECTOR(2 downto 0); -- vector offset input
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dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
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);
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);
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end component;
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end component;
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-- 8 bit opcode register opr (pipeline opcode prefetch register)
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-- 8 bit opcode register opr (pipeline opcode prefetch register)
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component opr
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component opr
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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clr: in STD_LOGIC; -- force BRK opcode
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clr: in STD_LOGIC; -- force BRK opcode
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fwait: in STD_LOGIC; -- wait
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fwait: in STD_LOGIC; -- wait
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ld: in STD_LOGIC; -- load
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ld: in STD_LOGIC; -- load
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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b: out STD_LOGIC; -- BRK opcode
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b: out STD_LOGIC; -- BRK opcode
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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);
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);
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end component;
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end component;
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-- 8 bit operand hold register oper
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-- 8 bit operand hold register oper
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component oper
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component oper
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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fwait: in STD_LOGIC; -- wait
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fwait: in STD_LOGIC; -- wait
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ld: in STD_LOGIC; -- load
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ld: in STD_LOGIC; -- load
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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);
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);
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end component;
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end component;
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-- 8 bit accumulator register A
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-- 8 bit accumulator register A
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component ar
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component ar
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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fwait: in STD_LOGIC;
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fwait: in STD_LOGIC;
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ld: in STD_LOGIC; -- load
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ld: in STD_LOGIC; -- load
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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);
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);
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end component;
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end component;
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-- 8 bit index register X
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-- 8 bit index register X
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component xr
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component xr
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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fwait: in STD_LOGIC;
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fwait: in STD_LOGIC;
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ld: in STD_LOGIC; -- load
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ld: in STD_LOGIC; -- load
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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);
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);
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end component;
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end component;
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-- 8 bit index register Y
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-- 8 bit index register Y
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component yr
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component yr
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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fwait: in STD_LOGIC;
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fwait: in STD_LOGIC;
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ld: in STD_LOGIC; -- load
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ld: in STD_LOGIC; -- load
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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);
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);
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end component;
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end component;
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-- 8 bit zero page register Z
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-- 8 bit zero page register Z
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-- cleared by any interrupts
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-- cleared by any interrupts
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component zr
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component zr
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port( clk: in STD_LOGIC; -- clock
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port( clk: in STD_LOGIC; -- clock
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clr: in STD_LOGIC; -- reset
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clr: in STD_LOGIC; -- reset
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fwait: in STD_LOGIC;
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fwait: in STD_LOGIC;
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ld: in STD_LOGIC; -- load
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ld: in STD_LOGIC; -- load
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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din: in STD_LOGIC_VECTOR(7 downto 0); -- input
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
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);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit stack pointer SP
|
-- 16 bit stack pointer SP
|
component spr
|
component spr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
clr: in STD_LOGIC; -- load init value
|
clr: in STD_LOGIC; -- load init value
|
ld_l: in STD_LOGIC; -- load lsb
|
ld_l: in STD_LOGIC; -- load lsb
|
ld_h: in STD_LOGIC; -- load msb
|
ld_h: in STD_LOGIC; -- load msb
|
u: in STD_LOGIC; -- increment
|
u: in STD_LOGIC; -- increment
|
d: in STD_LOGIC; -- decrement
|
d: in STD_LOGIC; -- decrement
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 8 bit processor status register P
|
-- 8 bit processor status register P
|
-- NV1BDIZC
|
-- NV1BDIZC
|
-- 76543210
|
-- 76543210
|
-- ||||||||
|
-- ||||||||
|
-- ||||||||--- C = carry/borrow flag
|
-- ||||||||--- C = carry/borrow flag
|
-- |||||||---- Z = zero flag
|
-- |||||||---- Z = zero flag
|
-- ||||||----- I = interrupt mask
|
-- ||||||----- I = interrupt mask
|
-- |||||------ D = decimal/binary alu mode
|
-- |||||------ D = decimal/binary alu mode
|
-- ||||------- B = break opcode flag
|
-- ||||------- B = break opcode flag
|
-- |||-------- 1 = always "1'
|
-- |||-------- 1 = always "1'
|
-- ||--------- V = overflow flag
|
-- ||--------- V = overflow flag
|
-- |---------- N = negative flag
|
-- |---------- N = negative flag
|
-- The P register also contains an additional carry/borrow flag (ACR) used for effective address calculation but
|
-- The P register also contains an additional carry/borrow flag (ACR) used for effective address calculation but
|
-- it is not visible at program level
|
-- it is not visible at program level
|
component pr
|
component pr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
clr: in STD_LOGIC; -- clear
|
clr: in STD_LOGIC; -- clear
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
n: in STD_LOGIC; -- N input
|
n: in STD_LOGIC; -- N input
|
v: in STD_LOGIC; -- V input
|
v: in STD_LOGIC; -- V input
|
z: in STD_LOGIC; -- Z input
|
z: in STD_LOGIC; -- Z input
|
c: in STD_LOGIC; -- C input
|
c: in STD_LOGIC; -- C input
|
b: in STD_LOGIC; -- B input
|
b: in STD_LOGIC; -- B input
|
sv: in STD_LOGIC; -- set overflow
|
sv: in STD_LOGIC; -- set overflow
|
acr_in: in STD_LOGIC; -- auxiliary carry in
|
acr_in: in STD_LOGIC; -- auxiliary carry in
|
fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
|
fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
|
dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
|
acr_out: out STD_LOGIC -- auxiliary carry out
|
acr_out: out STD_LOGIC -- auxiliary carry out
|
);
|
);
|
end component;
|
end component;
|
|
|
-- BCD register (used for decimal adjustement)
|
-- BCD register (used for decimal adjustement)
|
component bcd_reg is
|
component bcd_reg is
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
en: in STD_LOGIC;
|
en: in STD_LOGIC;
|
bcd_sl: in STD_LOGIC; -- loads "6" to lsb
|
bcd_sl: in STD_LOGIC; -- loads "6" to lsb
|
bcd_sh: in STD_LOGIC; -- loads "6" to msb
|
bcd_sh: in STD_LOGIC; -- loads "6" to msb
|
dout: out STD_LOGIC_VECTOR(7 downto 0)
|
dout: out STD_LOGIC_VECTOR(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 8 bit (binary/bcd) two-way through pass ALU
|
-- 8 bit (binary/bcd) two-way through pass ALU
|
-- operation:
|
-- operation:
|
-- aluop = "0000" => dout <= op1 (pass/test)
|
-- aluop = "0000" => dout <= op1 (pass/test)
|
-- aluop = "0001" => dout <= op1 + op2 + carry
|
-- aluop = "0001" => dout <= op1 + op2 + carry
|
-- aluop = "0010" => dout <= op1 - op2 - carry
|
-- aluop = "0010" => dout <= op1 - op2 - carry
|
-- aluop = "0011" => dout <= op1 and op2
|
-- aluop = "0011" => dout <= op1 and op2
|
-- aluop = "0100" => dout <= op1 or op2
|
-- aluop = "0100" => dout <= op1 or op2
|
-- aluop = "0101" => dout <= op1 xor op2
|
-- aluop = "0101" => dout <= op1 xor op2
|
-- aluop = "0110" => dout <= op1 + 1
|
-- aluop = "0110" => dout <= op1 + 1
|
-- aluop = "0111" => dout <= op1 - 1
|
-- aluop = "0111" => dout <= op1 - 1
|
-- aluop = "1000" => dout <= op1 << 1 (ASL)
|
-- aluop = "1000" => dout <= op1 << 1 (ASL)
|
-- aluop = "1001" => dout <= op1 >> 1 (LSR)
|
-- aluop = "1001" => dout <= op1 >> 1 (LSR)
|
-- aluop = "1010" => dout <= op1 << 1 (ROL)
|
-- aluop = "1010" => dout <= op1 << 1 (ROL)
|
-- aluop = "1011" => dout <= op1 >> 1 (ROR)
|
-- aluop = "1011" => dout <= op1 >> 1 (ROR)
|
component alu_bin
|
component alu_bin
|
port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation)
|
port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation)
|
cin: in STD_LOGIC; -- carry/borrow in
|
cin: in STD_LOGIC; -- carry/borrow in
|
vin: in STD_LOGIC; -- overflow in
|
vin: in STD_LOGIC; -- overflow in
|
op1: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #1
|
op1: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #1
|
op2: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #2
|
op2: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #2
|
fc: in STD_LOGIC_VECTOR(5 downto 0); -- function code
|
fc: in STD_LOGIC_VECTOR(5 downto 0); -- function code
|
cf: out STD_LOGIC; -- carry/borrow (byte) out
|
cf: out STD_LOGIC; -- carry/borrow (byte) out
|
zf: out STD_LOGIC; -- zero flag out
|
zf: out STD_LOGIC; -- zero flag out
|
nf: out STD_LOGIC; -- negative flag out
|
nf: out STD_LOGIC; -- negative flag out
|
vf: out STD_LOGIC; -- overflow flag out
|
vf: out STD_LOGIC; -- overflow flag out
|
pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation
|
pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation
|
bcd_ol: out STD_LOGIC; -- bcd lsb overflow
|
bcd_ol: out STD_LOGIC; -- bcd lsb overflow
|
bcd_oh: out STD_LOGIC; -- bcd msb overflow
|
bcd_oh: out STD_LOGIC; -- bcd msb overflow
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit result out
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit result out
|
);
|
);
|
end component;
|
end component;
|
|
|
-- PC/MP address multiplexer
|
-- PC/MP address multiplexer
|
component addrmux
|
component addrmux
|
port( sel: in STD_LOGIC_VECTOR(1 downto 0);
|
port( sel: in STD_LOGIC_VECTOR(1 downto 0);
|
a: in STD_LOGIC_VECTOR(15 downto 0);
|
a: in STD_LOGIC_VECTOR(15 downto 0);
|
b: in STD_LOGIC_VECTOR(15 downto 0);
|
b: in STD_LOGIC_VECTOR(15 downto 0);
|
s: in STD_LOGIC_VECTOR(15 downto 0);
|
s: in STD_LOGIC_VECTOR(15 downto 0);
|
y: out STD_LOGIC_VECTOR(15 downto 0)
|
y: out STD_LOGIC_VECTOR(15 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- register multiplexer
|
-- register multiplexer
|
component regmux
|
component regmux
|
port( sel: in STD_LOGIC_VECTOR(3 downto 0);
|
port( sel: in STD_LOGIC_VECTOR(3 downto 0);
|
a: in STD_LOGIC_VECTOR(7 downto 0);
|
a: in STD_LOGIC_VECTOR(7 downto 0);
|
b: in STD_LOGIC_VECTOR(7 downto 0);
|
b: in STD_LOGIC_VECTOR(7 downto 0);
|
c: in STD_LOGIC_VECTOR(7 downto 0);
|
c: in STD_LOGIC_VECTOR(7 downto 0);
|
d: in STD_LOGIC_VECTOR(7 downto 0);
|
d: in STD_LOGIC_VECTOR(7 downto 0);
|
e: in STD_LOGIC_VECTOR(7 downto 0);
|
e: in STD_LOGIC_VECTOR(7 downto 0);
|
f: in STD_LOGIC_VECTOR(7 downto 0);
|
f: in STD_LOGIC_VECTOR(7 downto 0);
|
g: in STD_LOGIC_VECTOR(7 downto 0);
|
g: in STD_LOGIC_VECTOR(7 downto 0);
|
h: in STD_LOGIC_VECTOR(7 downto 0);
|
h: in STD_LOGIC_VECTOR(7 downto 0);
|
i: in STD_LOGIC_VECTOR(7 downto 0);
|
i: in STD_LOGIC_VECTOR(7 downto 0);
|
j: in STD_LOGIC_VECTOR(7 downto 0);
|
j: in STD_LOGIC_VECTOR(7 downto 0);
|
k: in STD_LOGIC_VECTOR(7 downto 0);
|
k: in STD_LOGIC_VECTOR(7 downto 0);
|
y: out STD_LOGIC_VECTOR(7 downto 0)
|
y: out STD_LOGIC_VECTOR(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- data multiplexer (register "O" bypass)
|
-- data multiplexer (register "O" bypass)
|
component dmux is
|
component dmux is
|
port( sel: in STD_LOGIC_VECTOR(1 downto 0);
|
port( sel: in STD_LOGIC_VECTOR(1 downto 0);
|
a: in STD_LOGIC_VECTOR(7 downto 0);
|
a: in STD_LOGIC_VECTOR(7 downto 0);
|
b: in STD_LOGIC_VECTOR(7 downto 0);
|
b: in STD_LOGIC_VECTOR(7 downto 0);
|
c: in STD_LOGIC_VECTOR(7 downto 0);
|
c: in STD_LOGIC_VECTOR(7 downto 0);
|
y: out STD_LOGIC_VECTOR(7 downto 0)
|
y: out STD_LOGIC_VECTOR(7 downto 0)
|
);
|
);
|
end component dmux;
|
end component dmux;
|
|
|
-- microcode sequencer logic
|
-- microcode sequencer logic
|
component mcseq
|
component mcseq
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
mc_nop: in STD_LOGIC;
|
mc_nop: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
q: out STD_LOGIC_VECTOR(2 downto 0)
|
q: out STD_LOGIC_VECTOR(2 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- micropla logic
|
-- micropla logic
|
-- output fields format:
|
-- output fields format:
|
component mcpla
|
component mcpla
|
port( a: in STD_LOGIC_VECTOR(10 downto 0);
|
port( a: in STD_LOGIC_VECTOR(10 downto 0);
|
q: out STD_LOGIC_VECTOR(34 downto 0)
|
q: out STD_LOGIC_VECTOR(34 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- register operation decoding logic
|
-- register operation decoding logic
|
component decreg
|
component decreg
|
port( r: in STD_LOGIC_VECTOR(3 downto 0);
|
port( r: in STD_LOGIC_VECTOR(3 downto 0);
|
y: out STD_LOGIC_VECTOR(8 downto 0)
|
y: out STD_LOGIC_VECTOR(8 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- cpu main state machine
|
-- cpu main state machine
|
component cpufsm
|
component cpufsm
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
ireq: in STD_LOGIC;
|
ireq: in STD_LOGIC;
|
branch: in STD_LOGIC;
|
branch: in STD_LOGIC;
|
bflag: in STD_LOGIC;
|
bflag: in STD_LOGIC;
|
aim: in STD_LOGIC;
|
aim: in STD_LOGIC;
|
bcarry: in STD_LOGIC;
|
bcarry: in STD_LOGIC;
|
icarry: in STD_LOGIC;
|
icarry: in STD_LOGIC;
|
p1: in STD_LOGIC_VECTOR(1 downto 0);
|
p1: in STD_LOGIC_VECTOR(1 downto 0);
|
e_ei: in STD_LOGIC;
|
e_ei: in STD_LOGIC;
|
mc_ei: in STD_LOGIC;
|
mc_ei: in STD_LOGIC;
|
addsub: in STD_LOGIC;
|
addsub: in STD_LOGIC;
|
dec_mode: in STD_LOGIC;
|
dec_mode: in STD_LOGIC;
|
fetch: out STD_LOGIC;
|
fetch: out STD_LOGIC;
|
op_sync: out STD_LOGIC;
|
op_sync: out STD_LOGIC;
|
pci: out STD_LOGIC;
|
pci: out STD_LOGIC;
|
pq: out STD_LOGIC_VECTOR(1 downto 0);
|
pq: out STD_LOGIC_VECTOR(1 downto 0);
|
fb: out STD_LOGIC;
|
fb: out STD_LOGIC;
|
od: out STD_LOGIC;
|
od: out STD_LOGIC;
|
mc_nop: out STD_LOGIC
|
mc_nop: out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
-- interrupt logic
|
-- interrupt logic
|
component intlog
|
component intlog
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
iack: in STD_LOGIC; -- interrupt acknowledge by microcode
|
iack: in STD_LOGIC; -- interrupt acknowledge by microcode
|
r: in STD_LOGIC; -- RESET request
|
r: in STD_LOGIC; -- RESET request
|
n: in STD_LOGIC; -- NMI request
|
n: in STD_LOGIC; -- NMI request
|
i: in STD_LOGIC; -- IRQ request
|
i: in STD_LOGIC; -- IRQ request
|
b: in STD_LOGIC; -- BRK opcode
|
b: in STD_LOGIC; -- BRK opcode
|
s: in STD_LOGIC; -- SO
|
s: in STD_LOGIC; -- SO
|
imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ)
|
imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ)
|
ioffs: in STD_LOGIC_VECTOR(1 downto 0); -- interrupt servicing offset
|
ioffs: in STD_LOGIC_VECTOR(1 downto 0); -- interrupt servicing offset
|
ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI)
|
ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI)
|
vset: out STD_LOGIC; -- SO output
|
vset: out STD_LOGIC; -- SO output
|
voffs: out STD_LOGIC_VECTOR(2 downto 0) -- interrupt vector offset
|
voffs: out STD_LOGIC_VECTOR(2 downto 0) -- interrupt vector offset
|
);
|
);
|
end component;
|
end component;
|
|
|
-- branch logic
|
-- branch logic
|
component branch
|
component branch
|
port( op: in STD_LOGIC_VECTOR(3 downto 0);
|
port( op: in STD_LOGIC_VECTOR(3 downto 0);
|
n: in STD_LOGIC;
|
n: in STD_LOGIC;
|
v: in STD_LOGIC;
|
v: in STD_LOGIC;
|
z: in STD_LOGIC;
|
z: in STD_LOGIC;
|
c: in STD_LOGIC;
|
c: in STD_LOGIC;
|
bres: out STD_LOGIC
|
bres: out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
-- opcode decimal instructions and prefetch prediction logic
|
-- opcode decimal instructions and prefetch prediction logic
|
component pre_dec
|
component pre_dec
|
port( op: in STD_LOGIC_VECTOR(7 downto 0);
|
port( op: in STD_LOGIC_VECTOR(7 downto 0);
|
fetch: in STD_LOGIC;
|
fetch: in STD_LOGIC;
|
ei: out STD_LOGIC;
|
ei: out STD_LOGIC;
|
dec: out STD_LOGIC
|
dec: out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
u1:pcr port map(clk=>clk0,
|
u1:pcr port map(clk=>clk0,
|
i=>pcinc,
|
i=>pcinc,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
fc(3 downto 1)=>pcr_fc,
|
fc(3 downto 1)=>pcr_fc,
|
fc(0)=>o_bus(7),
|
fc(0)=>o_bus(7),
|
din1=>alu_bus,
|
din1=>alu_bus,
|
din2=>o_bus,
|
din2=>o_bus,
|
dout=>pc_bus
|
dout=>pc_bus
|
);
|
);
|
|
|
u2:mpr port map(clk=>clk0,
|
u2:mpr port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
c=>acr_reg,
|
c=>acr_reg,
|
fc=>mpr_fc,
|
fc=>mpr_fc,
|
din_l=>alu_bus,
|
din_l=>alu_bus,
|
din_h=>dbin,
|
din_h=>dbin,
|
zp=>z_bus,
|
zp=>z_bus,
|
v=>ivoffs,
|
v=>ivoffs,
|
dout=>mp_bus
|
dout=>mp_bus
|
);
|
);
|
|
|
u3:ar port map(clk=>clk0,
|
u3:ar port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>a_l,
|
ld=>a_l,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>a_bus
|
dout=>a_bus
|
);
|
);
|
|
|
u4:xr port map(clk=>clk0,
|
u4:xr port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>x_l,
|
ld=>x_l,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>x_bus
|
dout=>x_bus
|
);
|
);
|
|
|
u5:yr port map(clk=>clk0,
|
u5:yr port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>y_l,
|
ld=>y_l,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>y_bus
|
dout=>y_bus
|
);
|
);
|
|
|
u6:zr port map(clk=>clk0,
|
u6:zr port map(clk=>clk0,
|
clr=>clri,
|
clr=>clri,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>z_l,
|
ld=>z_l,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>z_bus
|
dout=>z_bus
|
);
|
);
|
|
|
u7:spr port map(clk=>clk0,
|
u7:spr port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld_l=>sp_ll,
|
ld_l=>sp_ll,
|
ld_h=>sp_lh,
|
ld_h=>sp_lh,
|
u=>sp_u,
|
u=>sp_u,
|
d=>sp_d,
|
d=>sp_d,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>sp_bus
|
dout=>sp_bus
|
);
|
);
|
|
|
u8:pr port map(clk=>clk0,
|
u8:pr port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
n=>n_flg,
|
n=>n_flg,
|
v=>v_flg,
|
v=>v_flg,
|
z=>z_flg,
|
z=>z_flg,
|
c=>c_flg,
|
c=>c_flg,
|
b=>opbrk,
|
b=>opbrk,
|
sv=>vso,
|
sv=>vso,
|
acr_in=>pc_c_alu_flg,
|
acr_in=>pc_c_alu_flg,
|
fc=>p_op,
|
fc=>p_op,
|
din=>dbin,
|
din=>dbin,
|
dout=>p_bus,
|
dout=>p_bus,
|
acr_out=>acr_reg
|
acr_out=>acr_reg
|
);
|
);
|
|
|
u9:opr port map(clk=>clk0,
|
u9:opr port map(clk=>clk0,
|
clr=>fbrk,
|
clr=>fbrk,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>opfetch,
|
ld=>opfetch,
|
din=>dbin,
|
din=>dbin,
|
b=>opbrk,
|
b=>opbrk,
|
dout=>op_bus
|
dout=>op_bus
|
);
|
);
|
|
|
u10:oper port map(clk=>clk0,
|
u10:oper port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>o_l,
|
ld=>o_l,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>o_bus
|
dout=>o_bus
|
);
|
);
|
|
|
u11:bcd_reg port map(clk=>clk0,
|
u11:bcd_reg port map(clk=>clk0,
|
clr=>opfetch,
|
clr=>opfetch,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
en=>bcd,
|
en=>bcd,
|
bcd_sl=>bcd_lsb,
|
bcd_sl=>bcd_lsb,
|
bcd_sh=>bcd_msb,
|
bcd_sh=>bcd_msb,
|
dout=>bcd_bus
|
dout=>bcd_bus
|
);
|
);
|
|
|
u12:alu_bin port map(alu_byp=>acr_reg,
|
u12:alu_bin port map(alu_byp=>acr_reg,
|
cin=>p_bus(0),
|
cin=>p_bus(0),
|
vin=>p_bus(6),
|
vin=>p_bus(6),
|
op1=>r_bus,
|
op1=>r_bus,
|
op2=>oper_bus,
|
op2=>oper_bus,
|
fc(5 downto 1)=>aluop,
|
fc(5 downto 1)=>aluop,
|
fc(0)=>branch_neg,
|
fc(0)=>branch_neg,
|
cf=>c_flg,
|
cf=>c_flg,
|
zf=>z_flg,
|
zf=>z_flg,
|
nf=>n_flg,
|
nf=>n_flg,
|
vf=>v_flg,
|
vf=>v_flg,
|
pc_cf=>pc_c_alu_flg,
|
pc_cf=>pc_c_alu_flg,
|
bcd_ol=>bcd_lsb,
|
bcd_ol=>bcd_lsb,
|
bcd_oh=>bcd_msb,
|
bcd_oh=>bcd_msb,
|
dout=>alu_bus
|
dout=>alu_bus
|
);
|
);
|
|
|
u13:addrmux port map(sel=>pcmp,
|
u13:addrmux port map(sel=>pcmp,
|
a=>pc_bus,
|
a=>pc_bus,
|
b=>mp_bus,
|
b=>mp_bus,
|
s=>sp_bus,
|
s=>sp_bus,
|
y=>addr
|
y=>addr
|
);
|
);
|
|
|
u14:regmux port map(sel=>rsel,
|
u14:regmux port map(sel=>rsel,
|
a=>dbin,
|
a=>dbin,
|
b=>a_bus,
|
b=>a_bus,
|
c=>x_bus,
|
c=>x_bus,
|
d=>y_bus,
|
d=>y_bus,
|
e=>sp_bus(7 downto 0),
|
e=>sp_bus(7 downto 0),
|
f=>sp_bus(15 downto 8),
|
f=>sp_bus(15 downto 8),
|
g=>p_bus,
|
g=>p_bus,
|
h=>pc_bus(7 downto 0),
|
h=>pc_bus(7 downto 0),
|
i=>pc_bus(15 downto 8),
|
i=>pc_bus(15 downto 8),
|
j=>o_bus,
|
j=>o_bus,
|
k=>z_bus,
|
k=>z_bus,
|
y=>r_bus
|
y=>r_bus
|
);
|
);
|
|
|
u15:dmux port map(sel=>dmux_sel,
|
u15:dmux port map(sel=>dmux_sel,
|
a=>o_bus,
|
a=>o_bus,
|
b=>dbin,
|
b=>dbin,
|
c=>bcd_bus,
|
c=>bcd_bus,
|
y=>oper_bus
|
y=>oper_bus
|
);
|
);
|
|
|
u16:mcseq port map(clk=>clk0,
|
u16:mcseq port map(clk=>clk0,
|
clr=>opdec,
|
clr=>opdec,
|
mc_nop=>mcn,
|
mc_nop=>mcn,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
q=>mcscan
|
q=>mcscan
|
);
|
);
|
|
|
u17:mcpla port map(a=>mcad,
|
u17:mcpla port map(a=>mcad,
|
q=>mcbit
|
q=>mcbit
|
);
|
);
|
|
|
u18:decreg port map(r=>regop,
|
u18:decreg port map(r=>regop,
|
y=>regbit
|
y=>regbit
|
);
|
);
|
|
|
u19:cpufsm port map(clk=>clk0,
|
u19:cpufsm port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ireq=>int,
|
ireq=>int,
|
branch=>mc_branch,
|
branch=>mc_branch,
|
bflag=>bcf,
|
bflag=>bcf,
|
aim=>ai_op,
|
aim=>ai_op,
|
bcarry=>pcc,
|
bcarry=>pcc,
|
icarry=>acr_reg,
|
icarry=>acr_reg,
|
p1=>pcmp_mc,
|
p1=>pcmp_mc,
|
e_ei=>e_eop,
|
e_ei=>e_eop,
|
mc_ei=>mc_eop,
|
mc_ei=>mc_eop,
|
addsub=>add_sub_op,
|
addsub=>add_sub_op,
|
dec_mode=>p_bus(3),
|
dec_mode=>p_bus(3),
|
fetch=>opfetch,
|
fetch=>opfetch,
|
op_sync=>i_sync,
|
op_sync=>i_sync,
|
pci=>pcinc,
|
pci=>pcinc,
|
pq=>pcmp,
|
pq=>pcmp,
|
fb=>fbrk,
|
fb=>fbrk,
|
od=>opdec,
|
od=>opdec,
|
mc_nop=>mcn
|
mc_nop=>mcn
|
);
|
);
|
|
|
u20:intlog port map(clk=>clk0,
|
u20:intlog port map(clk=>clk0,
|
iack=>clri,
|
iack=>clri,
|
r=>i_res,
|
r=>i_res,
|
n=>i_nmi,
|
n=>i_nmi,
|
i=>i_irq,
|
i=>i_irq,
|
b=>opbrk,
|
b=>opbrk,
|
s=>i_so,
|
s=>i_so,
|
imask=>ien,
|
imask=>ien,
|
ioffs=>mp_bus(2 downto 1),
|
ioffs=>mp_bus(2 downto 1),
|
ireq=>int,
|
ireq=>int,
|
vset=>vso,
|
vset=>vso,
|
voffs=>ivoffs
|
voffs=>ivoffs
|
);
|
);
|
|
|
u21:branch port map(op=>op_bus(7 downto 4),
|
u21:branch port map(op=>op_bus(7 downto 4),
|
n=>p_bus(7),
|
n=>p_bus(7),
|
v=>p_bus(6),
|
v=>p_bus(6),
|
z=>p_bus(1),
|
z=>p_bus(1),
|
c=>p_bus(0),
|
c=>p_bus(0),
|
bres=>bcf
|
bres=>bcf
|
);
|
);
|
|
|
u22:pre_dec port map(op=>dbin,
|
u22:pre_dec port map(op=>dbin,
|
fetch=>opfetch,
|
fetch=>opfetch,
|
ei=>e_eop,
|
ei=>e_eop,
|
dec=>add_sub_op
|
dec=>add_sub_op
|
);
|
);
|
|
|
-- asynchronous CPU link section
|
-- asynchronous CPU link section
|
ien <= p_bus(2); -- P(I) flag
|
ien <= p_bus(2); -- P(I) flag
|
bcd <= p_bus(3); -- P(D) flag
|
bcd <= p_bus(3); -- P(D) flag
|
i_res <= not res; -- internal reset
|
i_res <= not res; -- internal reset
|
i_nmi <= not nmi; -- internal NMI
|
i_nmi <= not nmi; -- internal NMI
|
i_irq <= not irq; -- internal IRQ
|
i_irq <= not irq; -- internal IRQ
|
i_rdy <= not rdy; -- internal RDY
|
i_rdy <= not rdy; -- internal RDY
|
i_so <= not so; -- internal SO
|
i_so <= not so; -- internal SO
|
mcad <= op_bus & mcscan; -- microcode address
|
mcad <= op_bus & mcscan; -- microcode address
|
rsel <= mcbit(3 downto 0); -- registers read microcode
|
rsel <= mcbit(3 downto 0); -- registers read microcode
|
regop <= mcbit(7 downto 4); -- registers operation microcode
|
regop <= mcbit(7 downto 4); -- registers operation microcode
|
aluop <= mcbit(12 downto 8); -- ALU microcode
|
aluop <= mcbit(12 downto 8); -- ALU microcode
|
p_op <= mcbit(16 downto 13); -- register P microcode
|
p_op <= mcbit(16 downto 13); -- register P microcode
|
mpr_fc <= mcbit(20 downto 17); -- MPR microcode
|
mpr_fc <= mcbit(20 downto 17); -- MPR microcode
|
pcr_fc <= mcbit(23 downto 21); -- PCR microcode
|
pcr_fc <= mcbit(23 downto 21); -- PCR microcode
|
pcmp_mc <= mcbit(25 downto 24); -- PCR/MPR multiplexer microcode
|
pcmp_mc <= mcbit(25 downto 24); -- PCR/MPR multiplexer microcode
|
clri <= mcbit(26); -- clear interrupt request (also serves as register Z clear)
|
clri <= mcbit(26); -- clear interrupt request (also serves as register Z clear)
|
we_mc <= mcbit(27); -- write enable (combinatorial) microcode
|
we_mc <= mcbit(27); -- write enable (combinatorial) microcode
|
we_mc_l <= mcbit(28); -- write enable (latched) microcode
|
we_mc_l <= mcbit(28); -- write enable (latched) microcode
|
mc_eop <= mcbit(29); -- end of instruction reached
|
mc_eop <= mcbit(29); -- end of instruction reached
|
mc_branch <= mcbit(30); -- branch opcode
|
mc_branch <= mcbit(30); -- branch opcode
|
i_vp <= mcbit(31); -- vector pull
|
i_vp <= mcbit(31); -- vector pull
|
ai_op <= mcbit(32); -- opcode with addressing indexed microcode
|
ai_op <= mcbit(32); -- opcode with addressing indexed microcode
|
dmux_sel <= mcbit(34 downto 33); -- data multiplexer microcode
|
dmux_sel <= mcbit(34 downto 33); -- data multiplexer microcode
|
ope <= eop;
|
ope <= eop;
|
eop <= '1' when mc_eop = '1' or e_eop = '1' else '0';
|
eop <= '1' when mc_eop = '1' or e_eop = '1' else '0';
|
branch_neg <= '0' when mc_branch = '0' else o_bus(7); -- flag for branch negative offset is valid only with branches opcode
|
branch_neg <= '0' when mc_branch = '0' else o_bus(7); -- flag for branch negative offset is valid only with branches opcode
|
vp <= not i_vp;
|
vp <= not i_vp;
|
|
|
-- register operations
|
-- register operations
|
a_l <= regbit(0); -- A load
|
a_l <= regbit(0); -- A load
|
x_l <= regbit(1); -- X load
|
x_l <= regbit(1); -- X load
|
y_l <= regbit(2); -- Y load
|
y_l <= regbit(2); -- Y load
|
z_l <= regbit(3); -- Z load
|
z_l <= regbit(3); -- Z load
|
o_l <= regbit(4); -- O load
|
o_l <= regbit(4); -- O load
|
sp_ll <= regbit(5); -- S load lsb
|
sp_ll <= regbit(5); -- S load lsb
|
sp_lh <= regbit(6); -- S load msb
|
sp_lh <= regbit(6); -- S load msb
|
sp_u <= regbit(7); -- S += 1
|
sp_u <= regbit(7); -- S += 1
|
sp_d <= regbit(8); -- S -= 1
|
sp_d <= regbit(8); -- S -= 1
|
we <= we_mc or opfetch; -- write enable
|
we <= we_mc or opfetch; -- write enable
|
sync <= m_sync;
|
sync <= m_sync;
|
|
|
-- SYNC latched
|
-- SYNC latched
|
process(clk0)
|
process(clk0)
|
begin
|
begin
|
if (clk0'event and clk0 = '1') then
|
if (clk0'event and clk0 = '1') then
|
if i_rdy = '0' then
|
if i_rdy = '0' then
|
m_sync <= i_sync;
|
m_sync <= i_sync;
|
else
|
else
|
m_sync <= m_sync;
|
m_sync <= m_sync;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- PC carry logic
|
-- PC carry logic
|
process(o_bus,pc_c_alu_flg)
|
process(o_bus,pc_c_alu_flg)
|
begin
|
begin
|
if o_bus(7) = '0' then -- check for positive/negative branch offset (bit 7)
|
if o_bus(7) = '0' then -- check for positive/negative branch offset (bit 7)
|
pcc <= pc_c_alu_flg;
|
pcc <= pc_c_alu_flg;
|
else
|
else
|
pcc <= not pc_c_alu_flg;
|
pcc <= not pc_c_alu_flg;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- write enable registered
|
-- write enable registered
|
process(clk0)
|
process(clk0)
|
begin
|
begin
|
if (clk0'event and clk0 = '1') then
|
if (clk0'event and clk0 = '1') then
|
if i_res = '1' then
|
if i_res = '1' then
|
we_r <= '1';
|
we_r <= '1';
|
else
|
else
|
if i_rdy = '0' then
|
if i_rdy = '0' then
|
we_r <= we_mc_l;
|
we_r <= we_mc_l;
|
else
|
else
|
we_r <= we_r;
|
we_r <= we_r;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
rw <= we and we_r;
|
rw <= we and we_r;
|
|
|
-- data bus tristate (buffer ring gated) control logic
|
-- data bus tristate (buffer ring gated) control logic
|
--process(clk0,we,we_r,alu_bus)
|
--process(clk0,we,we_r,alu_bus)
|
--begin
|
--begin
|
-- if clock = '0' and (we = '0' or we_r = '0') then
|
-- if clock = '0' and (we = '0' or we_r = '0') then
|
-- data <= alu_bus;
|
-- data <= alu_bus;
|
-- else
|
-- else
|
-- data <= "ZZZZZZZZ";
|
-- data <= "ZZZZZZZZ";
|
-- end if;
|
-- end if;
|
--end process;
|
--end process;
|
data_out <= alu_bus;
|
data_out <= alu_bus;
|
dbin <= data_in or "00000000";
|
dbin <= data_in or "00000000";
|
|
|
end struct;
|
end struct;
|
|
|
|
|
|
|
|
|