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-- 8/16 bit microprocessor (65C816) VHDL project --
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-- 8/16 bit microprocessor (65C816) VHDL project --
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-- Full RTL synchronous pipelined architecture --
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-- Full RTL synchronous pipelined architecture --
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-- Project by Valerio Venturi (Italy) --
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-- Project by Valerio Venturi (Italy) --
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-- Start date: 5/04/2020 --
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-- Start date: 5/04/2020 --
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-- Last revision: 5/04/2023 --
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-- Last revision: 5/04/2023 --
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You can use the codes given in this website for non-commercial purposes without my permission. But if you are using it for commercial purposes then contact me with the details of your project for my permission.
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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use IEEE.STD_LOGIC_arith.all;
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-- global architecture
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-- global architecture
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entity v65c816 is
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entity v65c816 is
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port( clk0: in STD_LOGIC; -- PHASE0 clock input
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port( clk0: in STD_LOGIC; -- PHASE0 clock input
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res: in STD_LOGIC; -- reset input
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res: in STD_LOGIC; -- reset input
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irq: in STD_LOGIC; -- interrupt request input
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irq: in STD_LOGIC; -- interrupt request input
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nmi: in STD_LOGIC; -- not maskable interrupt input
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nmi: in STD_LOGIC; -- not maskable interrupt input
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rdy: in STD_LOGIC; -- wait state request input (read/write)
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rdy: in STD_LOGIC; -- wait state request input (read/write)
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rdy_out: out STD_LOGIC; -- CPU in wait state (WAI instruction)
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rdy_out: out STD_LOGIC; -- CPU in wait state (WAI instruction)
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stp_out: out STD_LOGIC; -- CPU in stop state (STP instruction)
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stp_out: out STD_LOGIC; -- CPU in stop state (STP instruction)
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rw: out STD_LOGIC; -- read/write out
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rw: out STD_LOGIC; -- read/write out
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vpa: out STD_LOGIC; -- vpa
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vpa: out STD_LOGIC; -- vpa
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vda: out STD_LOGIC; -- vda
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vda: out STD_LOGIC; -- vda
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ml: out STD_LOGIC; -- ml
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ml: out STD_LOGIC; -- ml
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vp: out STD_LOGIC; -- vector pull
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vp: out STD_LOGIC; -- vector pull
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ope: out STD_LOGIC; -- microcode end
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ope: out STD_LOGIC; -- microcode end
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e: out STD_LOGIC; -- emulation (1)/native mode (0)
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e: out STD_LOGIC; -- emulation (1)/native mode (0)
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m: out STD_LOGIC; -- M status
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m: out STD_LOGIC; -- M status
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x: out STD_LOGIC; -- X status
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x: out STD_LOGIC; -- X status
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op_exp: out STD_LOGIC; -- two byte instruction running
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op_exp: out STD_LOGIC; -- two byte instruction running
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addr: out STD_LOGIC_VECTOR(23 downto 0); -- 16 bit address bus out
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addr: out STD_LOGIC_VECTOR(23 downto 0); -- 16 bit address bus out
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data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus
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data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus
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data_out: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit output data bus
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data_out: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit output data bus
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-- DEBUG
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-- DEBUG
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-- a_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit A register
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-- a_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit A register
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-- x_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit X register
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-- x_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit X register
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-- y_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Y register
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-- y_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Y register
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-- s_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit S register
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-- s_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit S register
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-- op_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Operand register
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-- op_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Operand register
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-- p_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit P register
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-- p_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit P register
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-- k_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit K register
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-- k_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit K register
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-- b_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit B register
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-- b_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit B register
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-- o_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit Opcode register
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-- o_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit Opcode register
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-- mcode: out STD_LOGIC_VECTOR(3 downto 0) -- 4 bit microcode sequence register
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-- mcode: out STD_LOGIC_VECTOR(3 downto 0) -- 4 bit microcode sequence register
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);
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);
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end v65c816;
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end v65c816;
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architecture struct of v65c816 is
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architecture struct of v65c816 is
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signal i_res: STD_LOGIC; -- internal global reset RES
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signal i_res: STD_LOGIC; -- internal global reset RES
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signal i_irq: STD_LOGIC; -- internal interrupt request IRQ
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signal i_irq: STD_LOGIC; -- internal interrupt request IRQ
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signal i_nmi: STD_LOGIC; -- internal interrupt request NMI
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signal i_nmi: STD_LOGIC; -- internal interrupt request NMI
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signal i_rdy: STD_LOGIC; -- internal wait request RDY
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signal i_rdy: STD_LOGIC; -- internal wait request RDY
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signal e_rdy: STD_LOGIC; -- external invertedf RDY
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signal e_rdy: STD_LOGIC; -- external invertedf RDY
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signal i_vp: STD_LOGIC; -- internal VP (vector pull)
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signal i_vp: STD_LOGIC; -- internal VP (vector pull)
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signal int: STD_LOGIC; -- internal global interrupt (instruction boundary synchronized)
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signal int: STD_LOGIC; -- internal global interrupt (instruction boundary synchronized)
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signal we: STD_LOGIC; -- write enable (combinatorial from PLA)
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signal we: STD_LOGIC; -- write enable (combinatorial from PLA)
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signal we_r: STD_LOGIC; -- write enable (registered)
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signal we_r: STD_LOGIC; -- write enable (registered)
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signal ien: STD_LOGIC; -- interrupt IRQ enable
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signal ien: STD_LOGIC; -- interrupt IRQ enable
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signal emu: STD_LOGIC; -- emulation mode
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signal emu: STD_LOGIC; -- emulation mode
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signal two_byte_op: STD_LOGIC; -- two byte instruction
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signal two_byte_op: STD_LOGIC; -- two byte instruction
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-- microcode signals (register control)
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-- microcode signals (register control)
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signal regop: STD_LOGIC_VECTOR(5 downto 0); -- register operation microcode
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signal regop: STD_LOGIC_VECTOR(5 downto 0); -- register operation microcode
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signal rsel: STD_LOGIC_VECTOR(4 downto 0); -- register select microcode
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signal rsel: STD_LOGIC_VECTOR(4 downto 0); -- register select microcode
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signal a_l_lsb: STD_LOGIC; -- A load lsb
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signal a_l_lsb: STD_LOGIC; -- A load lsb
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signal a_l_msb: STD_LOGIC; -- A load msb
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signal a_l_msb: STD_LOGIC; -- A load msb
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signal a_dec: STD_LOGIC; -- A decrement (MVN/MVP)
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signal a_dec: STD_LOGIC; -- A decrement (MVN/MVP)
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signal x_l_lsb: STD_LOGIC; -- X load lsb
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signal x_l_lsb: STD_LOGIC; -- X load lsb
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signal x_l_msb: STD_LOGIC; -- X load msb
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signal x_l_msb: STD_LOGIC; -- X load msb
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signal x_d: STD_LOGIC; -- X decrement
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signal x_d: STD_LOGIC; -- X decrement
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signal x_u: STD_LOGIC; -- X increment
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signal x_u: STD_LOGIC; -- X increment
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signal y_d: STD_LOGIC; -- Y decrement
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signal y_d: STD_LOGIC; -- Y decrement
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signal y_u: STD_LOGIC; -- Y increment
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signal y_u: STD_LOGIC; -- Y increment
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signal y_l_lsb: STD_LOGIC; -- Y load lsb
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signal y_l_lsb: STD_LOGIC; -- Y load lsb
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signal y_l_msb: STD_LOGIC; -- Y load msb
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signal y_l_msb: STD_LOGIC; -- Y load msb
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signal d_l_lsb: STD_LOGIC; -- D load lsb
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signal d_l_lsb: STD_LOGIC; -- D load lsb
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signal d_l_msb: STD_LOGIC; -- D load msb
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signal d_l_msb: STD_LOGIC; -- D load msb
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signal p_l: STD_LOGIC; -- P load
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signal p_l: STD_LOGIC; -- P load
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signal k_l: STD_LOGIC; -- program bank register PBR K load
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signal k_l: STD_LOGIC; -- program bank register PBR K load
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signal b_l: STD_LOGIC; -- data bank register DBR B load
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signal b_l: STD_LOGIC; -- data bank register DBR B load
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signal k_cl: STD_LOGIC; -- program bank register PBR K clear
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signal k_cl: STD_LOGIC; -- program bank register PBR K clear
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signal b_cl: STD_LOGIC; -- data bank register DBR B clear
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signal b_cl: STD_LOGIC; -- data bank register DBR B clear
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signal o_l: STD_LOGIC; -- OPE load msb & lsb
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signal o_l: STD_LOGIC; -- OPE load msb & lsb
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signal o_l_lsb: STD_LOGIC; -- OPE load lsb
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signal o_l_lsb: STD_LOGIC; -- OPE load lsb
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signal o_l_msb: STD_LOGIC; -- OPE load msb
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signal o_l_msb: STD_LOGIC; -- OPE load msb
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signal sp_ll: STD_LOGIC; -- SP load lsb
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signal sp_ll: STD_LOGIC; -- SP load lsb
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signal sp_lh: STD_LOGIC; -- SP load msb
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signal sp_lh: STD_LOGIC; -- SP load msb
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signal sp_u: STD_LOGIC; -- SP increment
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signal sp_u: STD_LOGIC; -- SP increment
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signal sp_d: STD_LOGIC; -- SP decrement
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signal sp_d: STD_LOGIC; -- SP decrement
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signal dmux_sel: STD_LOGIC_VECTOR(2 downto 0); -- ALU operand #2 data multiplexer
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signal dmux_sel: STD_LOGIC_VECTOR(2 downto 0); -- ALU operand #2 data multiplexer
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signal kr_clear: STD_LOGIC; -- K clear
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signal kr_clear: STD_LOGIC; -- K clear
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signal br_clear: STD_LOGIC; -- B clear
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signal br_clear: STD_LOGIC; -- B clear
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signal sp_emu: STD_LOGIC; -- '1' when S must be set in emulation mode
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signal sp_emu: STD_LOGIC; -- '1' when S must be set in emulation mode
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-- microcode signals (ALU control)
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-- microcode signals (ALU control)
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signal aluop: STD_LOGIC_VECTOR(4 downto 0); -- ALU operation code
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signal aluop: STD_LOGIC_VECTOR(4 downto 0); -- ALU operation code
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-- microcode signals CPU control logic
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-- microcode signals CPU control logic
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signal mc_addr: STD_LOGIC_VECTOR(12 downto 0); -- microcode PLA address
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signal mc_addr: STD_LOGIC_VECTOR(12 downto 0); -- microcode PLA address
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signal opfetch: STD_LOGIC; -- opcode fetch
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signal opfetch: STD_LOGIC; -- opcode fetch
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signal i_sync: STD_LOGIC; -- internal SYNC not latched
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signal i_sync: STD_LOGIC; -- internal SYNC not latched
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signal m_sync: STD_LOGIC; -- internal SYNC latched
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signal m_sync: STD_LOGIC; -- internal SYNC latched
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signal opdec: STD_LOGIC; -- opcode decode
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signal opdec: STD_LOGIC; -- opcode decode
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signal pcmp: STD_LOGIC_VECTOR(2 downto 0); -- PC/MP out control effective
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signal pcmp: STD_LOGIC_VECTOR(2 downto 0); -- PC/MP out control effective
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signal pcmp_mc: STD_LOGIC_VECTOR(2 downto 0); -- PC/MP out control microcode
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signal pcmp_mc: STD_LOGIC_VECTOR(2 downto 0); -- PC/MP out control microcode
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signal pcinc: STD_LOGIC; -- PC increment
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signal pcinc: STD_LOGIC; -- PC increment
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signal e_eop: STD_LOGIC; -- early microcode sequence end (for some opcodes)
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signal e_eop: STD_LOGIC; -- early microcode sequence end (for some opcodes)
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signal mc_eop: STD_LOGIC; -- microcode sequence end
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signal mc_eop: STD_LOGIC; -- microcode sequence end
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signal eop: STD_LOGIC; -- microcode sequence end (effective)
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signal eop: STD_LOGIC; -- microcode sequence end (effective)
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signal we_mc: STD_LOGIC; -- microcode write enable
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signal we_mc: STD_LOGIC; -- microcode write enable
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signal we_mc_l: STD_LOGIC; -- microcode write enable to latch
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signal we_mc_l: STD_LOGIC; -- microcode write enable to latch
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signal fbrk: STD_LOGIC; -- force BRK opcode (used by hardware interrupts)
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signal fbrk: STD_LOGIC; -- force BRK opcode (used by hardware interrupts)
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signal opbrk: STD_LOGIC; -- BRK opcode (used for distinguish between hardware/software interrupts)
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signal opbrk: STD_LOGIC; -- BRK opcode (used for distinguish between hardware/software interrupts)
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signal opcop: STD_LOGIC; -- COP opcode
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signal opcop: STD_LOGIC; -- COP opcode
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signal sw_int: STD_LOGIC; -- software interrupt request
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signal sw_int: STD_LOGIC; -- software interrupt request
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signal branch_taken: STD_LOGIC; -- branch condition resolved
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signal branch_taken: STD_LOGIC; -- branch condition resolved
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signal pcc: STD_LOGIC; -- PC carry
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signal pcc: STD_LOGIC; -- PC carry
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signal clri: STD_LOGIC; -- clear interrupt request pending microcode
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signal clri: STD_LOGIC; -- clear interrupt request pending microcode
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signal mc_vda: STD_LOGIC; -- microcode VDA
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signal mc_vda: STD_LOGIC; -- microcode VDA
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signal mc_vpa: STD_LOGIC; -- microcode VPA
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signal mc_vpa: STD_LOGIC; -- microcode VPA
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signal mc_ml: STD_LOGIC; -- microcode ML
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signal mc_ml: STD_LOGIC; -- microcode ML
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signal adc_sbc_mc: STD_LOGIC; -- ADC/SBC opcode (used for decimal adjustment)
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signal adc_sbc_mc: STD_LOGIC; -- ADC/SBC opcode (used for decimal adjustment)
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signal ai_op: STD_LOGIC; -- opcode with absolute indexed addressing mode
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signal ai_op: STD_LOGIC; -- opcode with absolute indexed addressing mode
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signal daa_req: STD_LOGIC; -- DAA required
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signal daa_req: STD_LOGIC; -- DAA required
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signal mcad: STD_LOGIC_VECTOR(11 downto 0); -- microcode address
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signal mcad: STD_LOGIC_VECTOR(11 downto 0); -- microcode address
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signal mcscan: STD_LOGIC_VECTOR(3 downto 0); -- microcode pointer control
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signal mcscan: STD_LOGIC_VECTOR(3 downto 0); -- microcode pointer control
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signal p_op: STD_LOGIC_VECTOR(4 downto 0); -- microcode control bits register P
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signal p_op: STD_LOGIC_VECTOR(4 downto 0); -- microcode control bits register P
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signal pcr_fc: STD_LOGIC_VECTOR(3 downto 0); -- microcode control PC
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signal pcr_fc: STD_LOGIC_VECTOR(3 downto 0); -- microcode control PC
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signal mpr_fc: STD_LOGIC_VECTOR(4 downto 0); -- microcode control MP
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signal mpr_fc: STD_LOGIC_VECTOR(4 downto 0); -- microcode control MP
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signal mcbit: STD_LOGIC_VECTOR(44 downto 0); -- microcode control bits
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signal mcbit: STD_LOGIC_VECTOR(44 downto 0); -- microcode control bits
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signal regbit: STD_LOGIC_VECTOR(29 downto 0); -- microcode control bits on registers
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signal regbit: STD_LOGIC_VECTOR(29 downto 0); -- microcode control bits on registers
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signal ivoffs: STD_LOGIC_VECTOR(7 downto 0); -- interrupt vector offset encoding
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signal ivoffs: STD_LOGIC_VECTOR(7 downto 0); -- interrupt vector offset encoding
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signal mcn: STD_LOGIC; -- microcode does NOPs
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signal mcn: STD_LOGIC; -- microcode does NOPs
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signal add_sub_op: STD_LOGIC; -- ADC/SBC opcode
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signal add_sub_op: STD_LOGIC; -- ADC/SBC opcode
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signal m_bit: STD_LOGIC; -- M bit of status register
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signal m_bit: STD_LOGIC; -- M bit of status register
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signal x_bit: STD_LOGIC; -- X bit of status register
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signal x_bit: STD_LOGIC; -- X bit of status register
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signal index_size: STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit
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signal index_size: STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit
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signal m_size8: STD_LOGIC; -- memory operation size: 1 = 8 bit
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signal m_size8: STD_LOGIC; -- memory operation size: 1 = 8 bit
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signal m_size16: STD_LOGIC; -- memory operation size: 1 = 16 bit
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signal m_size16: STD_LOGIC; -- memory operation size: 1 = 16 bit
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signal s_size16: STD_LOGIC; -- memory operation size: 1 = 16 bit for special cases
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signal s_size16: STD_LOGIC; -- memory operation size: 1 = 16 bit for special cases
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signal m_size: STD_LOGIC; -- memory operation size: 1 = 8 bit, 0 = 16 bit
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signal m_size: STD_LOGIC; -- memory operation size: 1 = 8 bit, 0 = 16 bit
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signal acc_size: STD_LOGIC; -- accumulator C size: 1 = 8 bit, 0 = 16 bit
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signal acc_size: STD_LOGIC; -- accumulator C size: 1 = 8 bit, 0 = 16 bit
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signal mov_end: STD_LOGIC; -- MVN/MVP end transfer
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signal mov_end: STD_LOGIC; -- MVN/MVP end transfer
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signal ld_acc: STD_LOGIC; -- load accumulator C register (16 bit)
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signal ld_acc: STD_LOGIC; -- load accumulator C register (16 bit)
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signal ld_xy: STD_LOGIC; -- load X/Y registers (16 bit)
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signal ld_xy: STD_LOGIC; -- load X/Y registers (16 bit)
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-- ALU signals
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-- ALU signals
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signal c_flg: STD_LOGIC; -- ALU carry flag
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signal c_flg: STD_LOGIC; -- ALU carry flag
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signal z_flg: STD_LOGIC; -- ALU zero flag
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signal z_flg: STD_LOGIC; -- ALU zero flag
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signal v_flg: STD_LOGIC; -- ALU overflow flag
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signal v_flg: STD_LOGIC; -- ALU overflow flag
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signal n_flg: STD_LOGIC; -- ALU negative flag
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signal n_flg: STD_LOGIC; -- ALU negative flag
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signal pc_c_alu_flg: STD_LOGIC; -- ALU PC carry flag
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signal pc_c_alu_flg: STD_LOGIC; -- ALU PC carry flag
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signal acr_reg: STD_LOGIC; -- ALU auxiliary carry (registered)
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signal acr_reg: STD_LOGIC; -- ALU auxiliary carry (registered)
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-- multiplier signals
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-- multiplier signals
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signal mul_init: STD_LOGIC; -- multiplier initialize
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signal mul_init: STD_LOGIC; -- multiplier initialize
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signal mul_start_u: STD_LOGIC; -- multiplier unsigned start
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signal mul_start_u: STD_LOGIC; -- multiplier unsigned start
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signal mul_start_s: STD_LOGIC; -- multiplier signed start
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signal mul_start_s: STD_LOGIC; -- multiplier signed start
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signal mul_busy: STD_LOGIC; -- multiplier busy
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signal mul_busy: STD_LOGIC; -- multiplier busy
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signal mul_r_lsb: STD_LOGIC_VECTOR(15 downto 0); -- multiplier lsb result
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signal mul_r_lsb: STD_LOGIC_VECTOR(15 downto 0); -- multiplier lsb result
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signal mul_r_msb: STD_LOGIC_VECTOR(15 downto 0); -- multiplier msb result
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signal mul_r_msb: STD_LOGIC_VECTOR(15 downto 0); -- multiplier msb result
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signal mul_l_res: STD_LOGIC; -- load multiplier lsb result on register A/B and multiplier msb result on register X
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signal mul_l_res: STD_LOGIC; -- load multiplier lsb result on register A/B and multiplier msb result on register X
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signal mul_z_flg: STD_LOGIC; -- multiplier Z flag
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signal mul_z_flg: STD_LOGIC; -- multiplier Z flag
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signal mul_n_flg: STD_LOGIC; -- multiplier N flag
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signal mul_n_flg: STD_LOGIC; -- multiplier N flag
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-- WAI/STP signals
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-- WAI/STP signals
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signal wai_ff: STD_LOGIC; -- WAI instruction flipflop
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signal wai_ff: STD_LOGIC; -- WAI instruction flipflop
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signal stp_ff: STD_LOGIC; -- STP instruction flipflop
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signal stp_ff: STD_LOGIC; -- STP instruction flipflop
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signal wai_set: STD_LOGIC; -- WAI flipflop set
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signal wai_set: STD_LOGIC; -- WAI flipflop set
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signal stp_set: STD_LOGIC; -- STP flipflop set
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signal stp_set: STD_LOGIC; -- STP flipflop set
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-- bus
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-- bus
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signal dbin: STD_LOGIC_VECTOR(7 downto 0); -- input data bus D0..D7
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signal dbin: STD_LOGIC_VECTOR(7 downto 0); -- input data bus D0..D7
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signal dbout: STD_LOGIC_VECTOR(7 downto 0); -- output data bus D0..D7
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signal dbout: STD_LOGIC_VECTOR(7 downto 0); -- output data bus D0..D7
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signal a_bus: STD_LOGIC_VECTOR(15 downto 0); -- accumulator register A/B/C bus
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signal a_bus: STD_LOGIC_VECTOR(15 downto 0); -- accumulator register A/B/C bus
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signal x_bus: STD_LOGIC_VECTOR(15 downto 0); -- index register X bus
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signal x_bus: STD_LOGIC_VECTOR(15 downto 0); -- index register X bus
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signal y_bus: STD_LOGIC_VECTOR(15 downto 0); -- index register Y bus
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signal y_bus: STD_LOGIC_VECTOR(15 downto 0); -- index register Y bus
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signal k_bus: STD_LOGIC_VECTOR(7 downto 0); -- program bank PBR K bus
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signal k_bus: STD_LOGIC_VECTOR(7 downto 0); -- program bank PBR K bus
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signal b_bus: STD_LOGIC_VECTOR(7 downto 0); -- program data DBR B bus
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signal b_bus: STD_LOGIC_VECTOR(7 downto 0); -- program data DBR B bus
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signal d_bus: STD_LOGIC_VECTOR(15 downto 0); -- zero page/direct register D bus
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signal d_bus: STD_LOGIC_VECTOR(15 downto 0); -- zero page/direct register D bus
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signal sp_bus: STD_LOGIC_VECTOR(15 downto 0); -- stack pointer register S bus
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signal sp_bus: STD_LOGIC_VECTOR(15 downto 0); -- stack pointer register S bus
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signal p_bus: STD_LOGIC_VECTOR(7 downto 0); -- status register P bus
|
signal p_bus: STD_LOGIC_VECTOR(7 downto 0); -- status register P bus
|
signal op_bus: STD_LOGIC_VECTOR(7 downto 0); -- opcode register bus
|
signal op_bus: STD_LOGIC_VECTOR(7 downto 0); -- opcode register bus
|
signal o_bus: STD_LOGIC_VECTOR(15 downto 0); -- operand register bus
|
signal o_bus: STD_LOGIC_VECTOR(15 downto 0); -- operand register bus
|
signal oper_bus: STD_LOGIC_VECTOR(15 downto 0); -- operand bus (ALU operand #2 bus)
|
signal oper_bus: STD_LOGIC_VECTOR(15 downto 0); -- operand bus (ALU operand #2 bus)
|
signal r_bus: STD_LOGIC_VECTOR(15 downto 0); -- general register bus (ALU operand #2 bus)
|
signal r_bus: STD_LOGIC_VECTOR(15 downto 0); -- general register bus (ALU operand #2 bus)
|
signal alu_bus: STD_LOGIC_VECTOR(15 downto 0); -- ALU output bus
|
signal alu_bus: STD_LOGIC_VECTOR(15 downto 0); -- ALU output bus
|
signal pc_bus: STD_LOGIC_VECTOR(15 downto 0); -- program counter register PC bus
|
signal pc_bus: STD_LOGIC_VECTOR(15 downto 0); -- program counter register PC bus
|
signal mp_bus: STD_LOGIC_VECTOR(23 downto 0); -- memory data pointer register bus
|
signal mp_bus: STD_LOGIC_VECTOR(23 downto 0); -- memory data pointer register bus
|
signal ad_bus: STD_LOGIC_VECTOR(15 downto 0); -- address bus
|
signal ad_bus: STD_LOGIC_VECTOR(15 downto 0); -- address bus
|
signal i_addr_bus: STD_LOGIC_VECTOR(23 downto 0); -- internal 24 bit address bus
|
signal i_addr_bus: STD_LOGIC_VECTOR(23 downto 0); -- internal 24 bit address bus
|
|
|
-- 16 bit program counter register (PC)
|
-- 16 bit program counter register (PC)
|
component pcr
|
component pcr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
i: in STD_LOGIC; -- increment
|
i: in STD_LOGIC; -- increment
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
brk_op: in STD_LOGIC; -- forced BRK (by interrupt request)
|
brk_op: in STD_LOGIC; -- forced BRK (by interrupt request)
|
branch_flg: in STD_LOGIC; -- branch flag
|
branch_flg: in STD_LOGIC; -- branch flag
|
mov_f: in STD_LOGIC; -- MVN/MVP end transfer
|
mov_f: in STD_LOGIC; -- MVN/MVP end transfer
|
fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
|
fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
|
din1: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din1: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din2: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
din2: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 8 bit PBR program bank register K
|
-- 8 bit PBR program bank register K
|
component kr
|
component kr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
clr: in STD_LOGIC; -- reset
|
clr: in STD_LOGIC; -- reset
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
ld: in STD_LOGIC; -- load
|
ld: in STD_LOGIC; -- load
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 8 bit DBR program bank register B
|
-- 8 bit DBR program bank register B
|
component br
|
component br
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
clr: in STD_LOGIC; -- reset
|
clr: in STD_LOGIC; -- reset
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
ld: in STD_LOGIC; -- load
|
ld: in STD_LOGIC; -- load
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit memory pointer register (MP)
|
-- 16 bit memory pointer register (MP)
|
component mpr
|
component mpr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
dbr_ld: in STD_LOGIC; -- load DBR
|
dbr_ld: in STD_LOGIC; -- load DBR
|
c: in STD_LOGIC; -- carry
|
c: in STD_LOGIC; -- carry
|
fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code
|
fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code
|
din_l: in STD_LOGIC_VECTOR(7 downto 0); -- input LSB
|
din_l: in STD_LOGIC_VECTOR(7 downto 0); -- input LSB
|
din_h: in STD_LOGIC_VECTOR(7 downto 0); -- input MSB
|
din_h: in STD_LOGIC_VECTOR(7 downto 0); -- input MSB
|
dbr: in STD_LOGIC_VECTOR(7 downto 0);
|
dbr: in STD_LOGIC_VECTOR(7 downto 0);
|
dr: in STD_LOGIC_VECTOR(15 downto 0);
|
dr: in STD_LOGIC_VECTOR(15 downto 0);
|
op: in STD_LOGIC_VECTOR(15 downto 0);
|
op: in STD_LOGIC_VECTOR(15 downto 0);
|
xr: in STD_LOGIC_VECTOR(15 downto 0);
|
xr: in STD_LOGIC_VECTOR(15 downto 0);
|
yr: in STD_LOGIC_VECTOR(15 downto 0);
|
yr: in STD_LOGIC_VECTOR(15 downto 0);
|
sr: in STD_LOGIC_VECTOR(15 downto 0);
|
sr: in STD_LOGIC_VECTOR(15 downto 0);
|
v: in STD_LOGIC_VECTOR(7 downto 0); -- vector offset input
|
v: in STD_LOGIC_VECTOR(7 downto 0); -- vector offset input
|
dout: out STD_LOGIC_VECTOR(23 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(23 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 8 bit opcode register opr (pipeline opcode prefetch register)
|
-- 8 bit opcode register opr (pipeline opcode prefetch register)
|
component opr
|
component opr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
clr: in STD_LOGIC; -- force BRK opcode
|
clr: in STD_LOGIC; -- force BRK opcode
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
ld: in STD_LOGIC; -- load
|
ld: in STD_LOGIC; -- load
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
brk_f: out STD_LOGIC; -- BRK opcode
|
brk_f: out STD_LOGIC; -- BRK opcode
|
cop_f: out STD_LOGIC; -- COP opcode
|
cop_f: out STD_LOGIC; -- COP opcode
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit operand hold register oper
|
-- 16 bit operand hold register oper
|
component oper
|
component oper
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
clr: in STD_LOGIC; -- clear
|
clr: in STD_LOGIC; -- clear
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
ld: in STD_LOGIC;
|
ld: in STD_LOGIC;
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_msb: in STD_LOGIC; -- load msb
|
ld_msb: in STD_LOGIC; -- load msb
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit accumulator register A
|
-- 16 bit accumulator register A
|
component ar
|
component ar
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
size: in STD_LOGIC; -- accumulator register size: 1 = 8 bit, 0 = 16 bit
|
size: in STD_LOGIC; -- accumulator register size: 1 = 8 bit, 0 = 16 bit
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_msb: in STD_LOGIC; -- load msb
|
ld_msb: in STD_LOGIC; -- load msb
|
ld_mul_lsb: in STD_LOGIC; -- load multiplication lsb result
|
ld_mul_lsb: in STD_LOGIC; -- load multiplication lsb result
|
d: in STD_LOGIC; -- decrement
|
d: in STD_LOGIC; -- decrement
|
end_count: out STD_LOGIC; -- '1' when a is 0xFF or 0xFFFF
|
end_count: out STD_LOGIC; -- '1' when a is 0xFF or 0xFFFF
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
mul_lsb: in STD_LOGIC_VECTOR(15 downto 0); -- input multiplication lsb result
|
mul_lsb: in STD_LOGIC_VECTOR(15 downto 0); -- input multiplication lsb result
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit index register X
|
-- 16 bit index register X
|
component xr
|
component xr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
size: in STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit
|
size: in STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_msb: in STD_LOGIC; -- load msb
|
ld_msb: in STD_LOGIC; -- load msb
|
ld_mul_msb: in STD_LOGIC;
|
ld_mul_msb: in STD_LOGIC;
|
u: in STD_LOGIC; -- increment
|
u: in STD_LOGIC; -- increment
|
d: in STD_LOGIC; -- decrement
|
d: in STD_LOGIC; -- decrement
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
mul_msb: in STD_LOGIC_VECTOR(15 downto 0); -- input multiplication msb result
|
mul_msb: in STD_LOGIC_VECTOR(15 downto 0); -- input multiplication msb result
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit index register Y
|
-- 16 bit index register Y
|
component yr
|
component yr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
size: in STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit
|
size: in STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_msb: in STD_LOGIC; -- load msb
|
ld_msb: in STD_LOGIC; -- load msb
|
u: in STD_LOGIC; -- increment
|
u: in STD_LOGIC; -- increment
|
d: in STD_LOGIC; -- decrement
|
d: in STD_LOGIC; -- decrement
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit zero page/direct register D
|
-- 16 bit zero page/direct register D
|
component dr
|
component dr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
clr: in STD_LOGIC; -- reset
|
clr: in STD_LOGIC; -- reset
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_lsb: in STD_LOGIC; -- load lsb
|
ld_msb: in STD_LOGIC; -- load msb
|
ld_msb: in STD_LOGIC; -- load msb
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit stack pointer SP
|
-- 16 bit stack pointer SP
|
component spr
|
component spr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
em: in STD_LOGIC; -- emulation mode (1)/native mode (0)
|
em: in STD_LOGIC; -- emulation mode (1)/native mode (0)
|
clr: in STD_LOGIC; -- load init value
|
clr: in STD_LOGIC; -- load init value
|
ld_l: in STD_LOGIC; -- load lsb
|
ld_l: in STD_LOGIC; -- load lsb
|
ld_h: in STD_LOGIC; -- load msb
|
ld_h: in STD_LOGIC; -- load msb
|
u: in STD_LOGIC; -- increment
|
u: in STD_LOGIC; -- increment
|
d: in STD_LOGIC; -- decrement
|
d: in STD_LOGIC; -- decrement
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(15 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 8 bit processor status register P
|
-- 8 bit processor status register P
|
-- NV1BDIZC
|
-- NV1BDIZC
|
-- 76543210
|
-- 76543210
|
-- ||||||||
|
-- ||||||||
|
-- ||||||||--- C/E = carry/borrow flag (emulation bit: 1 = emulation mode, 0 = native mode)
|
-- ||||||||--- C/E = carry/borrow flag (emulation bit: 1 = emulation mode, 0 = native mode)
|
-- |||||||---- Z = zero flag
|
-- |||||||---- Z = zero flag
|
-- ||||||----- I = interrupt mask
|
-- ||||||----- I = interrupt mask
|
-- |||||------ D = decimal/binary alu mode
|
-- |||||------ D = decimal/binary alu mode
|
-- ||||------- B/X = index reg. select (1 = 8 bit, 0 = 16 bit) (B Break: 0 on stack after interrupt if E emulation mode = 1)
|
-- ||||------- B/X = index reg. select (1 = 8 bit, 0 = 16 bit) (B Break: 0 on stack after interrupt if E emulation mode = 1)
|
-- |||-------- M = memory/acc. select (1 = 8 bit, 0 = 16 bit) (always 1 if E = 1)
|
-- |||-------- M = memory/acc. select (1 = 8 bit, 0 = 16 bit) (always 1 if E = 1)
|
-- ||--------- V = overflow flag
|
-- ||--------- V = overflow flag
|
-- |---------- N = negative flag
|
-- |---------- N = negative flag
|
-- The P register also contains an additional carry/borrow flag (ACR) used for effective address calculation but
|
-- The P register also contains an additional carry/borrow flag (ACR) used for effective address calculation but
|
-- it is not visible at program level
|
-- it is not visible at program level
|
component pr
|
component pr
|
port( clk: in STD_LOGIC; -- clock
|
port( clk: in STD_LOGIC; -- clock
|
clr: in STD_LOGIC; -- clear
|
clr: in STD_LOGIC; -- clear
|
fwait: in STD_LOGIC; -- wait
|
fwait: in STD_LOGIC; -- wait
|
n: in STD_LOGIC; -- N input
|
n: in STD_LOGIC; -- N input
|
v: in STD_LOGIC; -- V input
|
v: in STD_LOGIC; -- V input
|
z: in STD_LOGIC; -- Z input
|
z: in STD_LOGIC; -- Z input
|
c: in STD_LOGIC; -- C input
|
c: in STD_LOGIC; -- C input
|
mpy_z: in STD_LOGIC; -- Z input from multiplier
|
mpy_z: in STD_LOGIC; -- Z input from multiplier
|
mpy_n: in STD_LOGIC; -- N input from multiplier
|
mpy_n: in STD_LOGIC; -- N input from multiplier
|
swi: in STD_LOGIC; -- software interrupt (BRK/COP opcode)
|
swi: in STD_LOGIC; -- software interrupt (BRK/COP opcode)
|
acr_in: in STD_LOGIC; -- auxiliary carry in
|
acr_in: in STD_LOGIC; -- auxiliary carry in
|
fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code
|
fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
din: in STD_LOGIC_VECTOR(7 downto 0); -- input
|
dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
|
dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
|
acr_out: out STD_LOGIC; -- auxiliary carry out
|
acr_out: out STD_LOGIC; -- auxiliary carry out
|
em: out STD_LOGIC; -- emulation (1)/native mode (0)
|
em: out STD_LOGIC; -- emulation (1)/native mode (0)
|
two_op: out STD_LOGIC -- two byte instruction
|
two_op: out STD_LOGIC -- two byte instruction
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16 bit (binary/bcd) two-way through pass ALU
|
-- 16 bit (binary/bcd) two-way through pass ALU
|
component alu_bin
|
component alu_bin
|
port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation)
|
port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation)
|
bcd: in STD_LOGIC; -- BCD mode
|
bcd: in STD_LOGIC; -- BCD mode
|
size: in STD_LOGIC; -- ALU size operation: 1 = 8 bit, 0 = 16 bit
|
size: in STD_LOGIC; -- ALU size operation: 1 = 8 bit, 0 = 16 bit
|
cin: in STD_LOGIC; -- carry/borrow in
|
cin: in STD_LOGIC; -- carry/borrow in
|
vin: in STD_LOGIC; -- overflow in
|
vin: in STD_LOGIC; -- overflow in
|
op1: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #1
|
op1: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #1
|
op2: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #2
|
op2: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #2
|
fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code
|
fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code
|
cf: out STD_LOGIC; -- carry/borrow (byte) out
|
cf: out STD_LOGIC; -- carry/borrow (byte) out
|
zf: out STD_LOGIC; -- zero flag out
|
zf: out STD_LOGIC; -- zero flag out
|
nf: out STD_LOGIC; -- negative flag out
|
nf: out STD_LOGIC; -- negative flag out
|
vf: out STD_LOGIC; -- overflow flag out
|
vf: out STD_LOGIC; -- overflow flag out
|
pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation
|
pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- 16 bit result out
|
dout: out STD_LOGIC_VECTOR(15 downto 0) -- 16 bit result out
|
);
|
);
|
end component;
|
end component;
|
|
|
-- PC/MP address multiplexer
|
-- PC/MP address multiplexer
|
component addrmux
|
component addrmux
|
port( sel: in STD_LOGIC_VECTOR(2 downto 0);
|
port( sel: in STD_LOGIC_VECTOR(2 downto 0);
|
a: in STD_LOGIC_VECTOR(23 downto 0);
|
a: in STD_LOGIC_VECTOR(23 downto 0);
|
b: in STD_LOGIC_VECTOR(23 downto 0);
|
b: in STD_LOGIC_VECTOR(23 downto 0);
|
dbr: in STD_LOGIC_VECTOR(7 downto 0);
|
dbr: in STD_LOGIC_VECTOR(7 downto 0);
|
s: in STD_LOGIC_VECTOR(15 downto 0);
|
s: in STD_LOGIC_VECTOR(15 downto 0);
|
xr: in STD_LOGIC_VECTOR(15 downto 0);
|
xr: in STD_LOGIC_VECTOR(15 downto 0);
|
yr: in STD_LOGIC_VECTOR(15 downto 0);
|
yr: in STD_LOGIC_VECTOR(15 downto 0);
|
y: out STD_LOGIC_VECTOR(23 downto 0)
|
y: out STD_LOGIC_VECTOR(23 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- register multiplexer
|
-- register multiplexer
|
component regmux
|
component regmux
|
port( sel: in STD_LOGIC_VECTOR(4 downto 0);
|
port( sel: in STD_LOGIC_VECTOR(4 downto 0);
|
a: in STD_LOGIC_VECTOR(7 downto 0);
|
a: in STD_LOGIC_VECTOR(7 downto 0);
|
b: in STD_LOGIC_VECTOR(15 downto 0);
|
b: in STD_LOGIC_VECTOR(15 downto 0);
|
c: in STD_LOGIC_VECTOR(15 downto 0);
|
c: in STD_LOGIC_VECTOR(15 downto 0);
|
d: in STD_LOGIC_VECTOR(15 downto 0);
|
d: in STD_LOGIC_VECTOR(15 downto 0);
|
e: in STD_LOGIC_VECTOR(15 downto 0);
|
e: in STD_LOGIC_VECTOR(15 downto 0);
|
g: in STD_LOGIC_VECTOR(7 downto 0);
|
g: in STD_LOGIC_VECTOR(7 downto 0);
|
h: in STD_LOGIC_VECTOR(7 downto 0);
|
h: in STD_LOGIC_VECTOR(7 downto 0);
|
i: in STD_LOGIC_VECTOR(7 downto 0);
|
i: in STD_LOGIC_VECTOR(7 downto 0);
|
j: in STD_LOGIC_VECTOR(15 downto 0);
|
j: in STD_LOGIC_VECTOR(15 downto 0);
|
k: in STD_LOGIC_VECTOR(15 downto 0);
|
k: in STD_LOGIC_VECTOR(15 downto 0);
|
l: in STD_LOGIC_VECTOR(7 downto 0);
|
l: in STD_LOGIC_VECTOR(7 downto 0);
|
m: in STD_LOGIC_VECTOR(7 downto 0);
|
m: in STD_LOGIC_VECTOR(7 downto 0);
|
y: out STD_LOGIC_VECTOR(15 downto 0)
|
y: out STD_LOGIC_VECTOR(15 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- data multiplexer (register "O" bypass)
|
-- data multiplexer (register "O" bypass)
|
component dmux is
|
component dmux is
|
port( sel: in STD_LOGIC_VECTOR(2 downto 0);
|
port( sel: in STD_LOGIC_VECTOR(2 downto 0);
|
a: in STD_LOGIC_VECTOR(15 downto 0);
|
a: in STD_LOGIC_VECTOR(15 downto 0);
|
b: in STD_LOGIC_VECTOR(7 downto 0);
|
b: in STD_LOGIC_VECTOR(7 downto 0);
|
y: out STD_LOGIC_VECTOR(15 downto 0)
|
y: out STD_LOGIC_VECTOR(15 downto 0)
|
);
|
);
|
end component dmux;
|
end component dmux;
|
|
|
-- microcode sequencer logic
|
-- microcode sequencer logic
|
component mcseq
|
component mcseq
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
mc_nop: in STD_LOGIC;
|
mc_nop: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
q: out STD_LOGIC_VECTOR(3 downto 0)
|
q: out STD_LOGIC_VECTOR(3 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- micropla logic
|
-- micropla logic
|
-- output fields format:
|
-- output fields format:
|
-- a[12] is two byte instruction bit
|
-- a[12] is two byte instruction bit
|
-- a[11..4] is 8 bit opcode
|
-- a[11..4] is 8 bit opcode
|
-- a[3..0] is 4 bit microinstruction counter
|
-- a[3..0] is 4 bit microinstruction counter
|
component mcpla
|
component mcpla
|
port( em: in STD_LOGIC; -- emulation mode (1)/native mode (0)
|
port( em: in STD_LOGIC; -- emulation mode (1)/native mode (0)
|
m: in STD_LOGIC; -- M memory/acc. 8 bit (1), M memory/acc. 16 bit (0)
|
m: in STD_LOGIC; -- M memory/acc. 8 bit (1), M memory/acc. 16 bit (0)
|
x: in STD_LOGIC; -- X index reg. 8 bit (1), X index reg. 16 bit (0)
|
x: in STD_LOGIC; -- X index reg. 8 bit (1), X index reg. 16 bit (0)
|
a: in STD_LOGIC_VECTOR(12 downto 0); -- two byte bit & 8 bit opcode & 4 bit microinstruction counter
|
a: in STD_LOGIC_VECTOR(12 downto 0); -- two byte bit & 8 bit opcode & 4 bit microinstruction counter
|
q: out STD_LOGIC_VECTOR(44 downto 0) -- microcode output
|
q: out STD_LOGIC_VECTOR(44 downto 0) -- microcode output
|
);
|
);
|
end component;
|
end component;
|
|
|
-- register operation decoding logic
|
-- register operation decoding logic
|
component decreg
|
component decreg
|
port( r: in STD_LOGIC_VECTOR(5 downto 0);
|
port( r: in STD_LOGIC_VECTOR(5 downto 0);
|
y: out STD_LOGIC_VECTOR(29 downto 0)
|
y: out STD_LOGIC_VECTOR(29 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- cpu main state machine
|
-- cpu main state machine
|
component cpufsm
|
component cpufsm
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
fwait: in STD_LOGIC;
|
ireq: in STD_LOGIC;
|
ireq: in STD_LOGIC;
|
aim: in STD_LOGIC;
|
aim: in STD_LOGIC;
|
bcarry: in STD_LOGIC;
|
bcarry: in STD_LOGIC;
|
icarry: in STD_LOGIC;
|
icarry: in STD_LOGIC;
|
p1: in STD_LOGIC_VECTOR(2 downto 0);
|
p1: in STD_LOGIC_VECTOR(2 downto 0);
|
e_ei: in STD_LOGIC;
|
e_ei: in STD_LOGIC;
|
mc_ei: in STD_LOGIC;
|
mc_ei: in STD_LOGIC;
|
addsub: in STD_LOGIC;
|
addsub: in STD_LOGIC;
|
dec_mode: in STD_LOGIC;
|
dec_mode: in STD_LOGIC;
|
fetch: out STD_LOGIC;
|
fetch: out STD_LOGIC;
|
op_sync: out STD_LOGIC;
|
op_sync: out STD_LOGIC;
|
pci: out STD_LOGIC;
|
pci: out STD_LOGIC;
|
pq: out STD_LOGIC_VECTOR(2 downto 0);
|
pq: out STD_LOGIC_VECTOR(2 downto 0);
|
fb: out STD_LOGIC;
|
fb: out STD_LOGIC;
|
od: out STD_LOGIC;
|
od: out STD_LOGIC;
|
mc_nop: out STD_LOGIC
|
mc_nop: out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
-- interrupt logic
|
-- interrupt logic
|
component intlog
|
component intlog
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
iack: in STD_LOGIC; -- interrupt acknowledge by microcode
|
iack: in STD_LOGIC; -- interrupt acknowledge by microcode
|
r: in STD_LOGIC; -- RESET request
|
r: in STD_LOGIC; -- RESET request
|
n: in STD_LOGIC; -- NMI request
|
n: in STD_LOGIC; -- NMI request
|
i: in STD_LOGIC; -- IRQ request
|
i: in STD_LOGIC; -- IRQ request
|
brk: in STD_LOGIC; -- BRK opcode
|
brk: in STD_LOGIC; -- BRK opcode
|
cop: in STD_LOGIC; -- COP opcode
|
cop: in STD_LOGIC; -- COP opcode
|
e: in STD_LOGIC; -- native\emulation mode
|
e: in STD_LOGIC; -- native\emulation mode
|
gmask: in STD_LOGIC; -- interrupt mask valid for IRQ and NMI (used by two byte instruction)
|
gmask: in STD_LOGIC; -- interrupt mask valid for IRQ and NMI (used by two byte instruction)
|
imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ)
|
imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ)
|
ioffs: in STD_LOGIC_VECTOR(7 downto 0); -- interrupt servicing offset
|
ioffs: in STD_LOGIC_VECTOR(7 downto 0); -- interrupt servicing offset
|
ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI)
|
ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI)
|
voffs: out STD_LOGIC_VECTOR(7 downto 0) -- interrupt vector offset
|
voffs: out STD_LOGIC_VECTOR(7 downto 0) -- interrupt vector offset
|
);
|
);
|
end component;
|
end component;
|
|
|
-- branch logic
|
-- branch logic
|
component branch
|
component branch
|
port( op: in STD_LOGIC_VECTOR(3 downto 0);
|
port( op: in STD_LOGIC_VECTOR(3 downto 0);
|
n: in STD_LOGIC;
|
n: in STD_LOGIC;
|
v: in STD_LOGIC;
|
v: in STD_LOGIC;
|
z: in STD_LOGIC;
|
z: in STD_LOGIC;
|
c: in STD_LOGIC;
|
c: in STD_LOGIC;
|
bres: out STD_LOGIC
|
bres: out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
-- opcode decimal instructions and prefetch prediction logic
|
-- opcode decimal instructions and prefetch prediction logic
|
component pre_dec
|
component pre_dec
|
port( op: in STD_LOGIC_VECTOR(7 downto 0);
|
port( op: in STD_LOGIC_VECTOR(7 downto 0);
|
fetch: in STD_LOGIC;
|
fetch: in STD_LOGIC;
|
ei: out STD_LOGIC;
|
ei: out STD_LOGIC;
|
dec: out STD_LOGIC
|
dec: out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
-- 16X16->32 bit multiplier signed/unsigned
|
-- 16X16->32 bit multiplier signed/unsigned
|
component multiplier
|
component multiplier
|
port( clk: in STD_LOGIC;
|
port( clk: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
clr: in STD_LOGIC;
|
init: in STD_LOGIC;
|
init: in STD_LOGIC;
|
start_u: in STD_LOGIC;
|
start_u: in STD_LOGIC;
|
start_s: in STD_LOGIC;
|
start_s: in STD_LOGIC;
|
mpcand: in STD_LOGIC_VECTOR(15 downto 0);
|
mpcand: in STD_LOGIC_VECTOR(15 downto 0);
|
mplier: in STD_LOGIC_VECTOR(15 downto 0);
|
mplier: in STD_LOGIC_VECTOR(15 downto 0);
|
busy: out STD_LOGIC;
|
busy: out STD_LOGIC;
|
res_lsb: out STD_LOGIC_VECTOR(15 downto 0);
|
res_lsb: out STD_LOGIC_VECTOR(15 downto 0);
|
res_msb: out STD_LOGIC_VECTOR(15 downto 0);
|
res_msb: out STD_LOGIC_VECTOR(15 downto 0);
|
z_flg: out STD_LOGIC;
|
z_flg: out STD_LOGIC;
|
n_flg: out STD_LOGIC
|
n_flg: out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
u1:pcr port map(clk=>clk0,
|
u1:pcr port map(clk=>clk0,
|
i=>pcinc,
|
i=>pcinc,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
brk_op=>opbrk,
|
brk_op=>opbrk,
|
branch_flg=>branch_taken,
|
branch_flg=>branch_taken,
|
mov_f=>mov_end,
|
mov_f=>mov_end,
|
fc=>pcr_fc,
|
fc=>pcr_fc,
|
din1=>alu_bus(7 downto 0),
|
din1=>alu_bus(7 downto 0),
|
din2=>o_bus,
|
din2=>o_bus,
|
dout=>pc_bus
|
dout=>pc_bus
|
);
|
);
|
|
|
u2:kr port map(clk=>clk0,
|
u2:kr port map(clk=>clk0,
|
clr=>kr_clear,
|
clr=>kr_clear,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>k_l,
|
ld=>k_l,
|
din=>alu_bus(7 downto 0),
|
din=>alu_bus(7 downto 0),
|
dout=>k_bus
|
dout=>k_bus
|
);
|
);
|
|
|
u3:br port map(clk=>clk0,
|
u3:br port map(clk=>clk0,
|
clr=>br_clear,
|
clr=>br_clear,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>b_l,
|
ld=>b_l,
|
din=>alu_bus(7 downto 0),
|
din=>alu_bus(7 downto 0),
|
dout=>b_bus
|
dout=>b_bus
|
);
|
);
|
|
|
u4:mpr port map(clk=>clk0,
|
u4:mpr port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
dbr_ld=>opfetch,
|
dbr_ld=>opfetch,
|
c=>acr_reg,
|
c=>acr_reg,
|
fc=>mpr_fc,
|
fc=>mpr_fc,
|
din_l=>alu_bus(7 downto 0),
|
din_l=>alu_bus(7 downto 0),
|
din_h=>dbin,
|
din_h=>dbin,
|
dbr=>b_bus,
|
dbr=>b_bus,
|
dr=>d_bus,
|
dr=>d_bus,
|
op=>o_bus,
|
op=>o_bus,
|
xr=>x_bus,
|
xr=>x_bus,
|
yr=>y_bus,
|
yr=>y_bus,
|
sr=>sp_bus,
|
sr=>sp_bus,
|
v=>ivoffs,
|
v=>ivoffs,
|
dout=>mp_bus
|
dout=>mp_bus
|
);
|
);
|
|
|
u5:ar port map(clk=>clk0,
|
u5:ar port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
size=>acc_size,
|
size=>acc_size,
|
ld_lsb=>a_l_lsb,
|
ld_lsb=>a_l_lsb,
|
ld_msb=>a_l_msb,
|
ld_msb=>a_l_msb,
|
ld_mul_lsb=>mul_l_res,
|
ld_mul_lsb=>mul_l_res,
|
d=>a_dec,
|
d=>a_dec,
|
end_count=>mov_end,
|
end_count=>mov_end,
|
din=>alu_bus,
|
din=>alu_bus,
|
mul_lsb=>mul_r_lsb,
|
mul_lsb=>mul_r_lsb,
|
dout=>a_bus
|
dout=>a_bus
|
);
|
);
|
|
|
u6:xr port map(clk=>clk0,
|
u6:xr port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
size=>index_size,
|
size=>index_size,
|
ld_lsb=>x_l_lsb,
|
ld_lsb=>x_l_lsb,
|
ld_msb=>x_l_msb,
|
ld_msb=>x_l_msb,
|
ld_mul_msb=>mul_l_res,
|
ld_mul_msb=>mul_l_res,
|
u=>x_u,
|
u=>x_u,
|
d=>x_d,
|
d=>x_d,
|
din=>alu_bus,
|
din=>alu_bus,
|
mul_msb=>mul_r_msb,
|
mul_msb=>mul_r_msb,
|
dout=>x_bus
|
dout=>x_bus
|
);
|
);
|
|
|
u7:yr port map(clk=>clk0,
|
u7:yr port map(clk=>clk0,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
size=>index_size,
|
size=>index_size,
|
ld_lsb=>y_l_lsb,
|
ld_lsb=>y_l_lsb,
|
ld_msb=>y_l_msb,
|
ld_msb=>y_l_msb,
|
u=>y_u,
|
u=>y_u,
|
d=>y_d,
|
d=>y_d,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>y_bus
|
dout=>y_bus
|
);
|
);
|
|
|
u8:dr port map(clk=>clk0,
|
u8:dr port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld_lsb=>d_l_lsb,
|
ld_lsb=>d_l_lsb,
|
ld_msb=>d_l_msb,
|
ld_msb=>d_l_msb,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>d_bus
|
dout=>d_bus
|
);
|
);
|
|
|
u9:spr port map(clk=>clk0,
|
u9:spr port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
em=>sp_emu,
|
em=>sp_emu,
|
ld_l=>sp_ll,
|
ld_l=>sp_ll,
|
ld_h=>sp_lh,
|
ld_h=>sp_lh,
|
u=>sp_u,
|
u=>sp_u,
|
d=>sp_d,
|
d=>sp_d,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>sp_bus
|
dout=>sp_bus
|
);
|
);
|
|
|
u10:pr port map(clk=>clk0,
|
u10:pr port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
n=>n_flg,
|
n=>n_flg,
|
v=>v_flg,
|
v=>v_flg,
|
z=>z_flg,
|
z=>z_flg,
|
c=>c_flg,
|
c=>c_flg,
|
mpy_z=>mul_z_flg,
|
mpy_z=>mul_z_flg,
|
mpy_n=>mul_n_flg,
|
mpy_n=>mul_n_flg,
|
swi=>sw_int,
|
swi=>sw_int,
|
acr_in=>pc_c_alu_flg,
|
acr_in=>pc_c_alu_flg,
|
fc=>p_op,
|
fc=>p_op,
|
din=>dbin,
|
din=>dbin,
|
dout=>p_bus,
|
dout=>p_bus,
|
acr_out=>acr_reg,
|
acr_out=>acr_reg,
|
em=>emu,
|
em=>emu,
|
two_op=>two_byte_op
|
two_op=>two_byte_op
|
);
|
);
|
|
|
u11:opr port map(clk=>clk0,
|
u11:opr port map(clk=>clk0,
|
clr=>fbrk,
|
clr=>fbrk,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>opfetch,
|
ld=>opfetch,
|
din=>dbin,
|
din=>dbin,
|
brk_f=>opbrk,
|
brk_f=>opbrk,
|
cop_f=>opcop,
|
cop_f=>opcop,
|
dout=>op_bus
|
dout=>op_bus
|
);
|
);
|
|
|
u12:oper port map(clk=>clk0,
|
u12:oper port map(clk=>clk0,
|
clr=>opfetch,
|
clr=>opfetch,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ld=>o_l,
|
ld=>o_l,
|
ld_lsb=>o_l_lsb,
|
ld_lsb=>o_l_lsb,
|
ld_msb=>o_l_msb,
|
ld_msb=>o_l_msb,
|
din=>alu_bus,
|
din=>alu_bus,
|
dout=>o_bus
|
dout=>o_bus
|
);
|
);
|
|
|
u13:alu_bin port map(alu_byp=>acr_reg,
|
u13:alu_bin port map(alu_byp=>acr_reg,
|
bcd=>p_bus(3),
|
bcd=>p_bus(3),
|
size=>m_size,
|
size=>m_size,
|
cin=>p_bus(0),
|
cin=>p_bus(0),
|
vin=>p_bus(6),
|
vin=>p_bus(6),
|
op1=>r_bus,
|
op1=>r_bus,
|
op2=>oper_bus,
|
op2=>oper_bus,
|
fc=>aluop,
|
fc=>aluop,
|
cf=>c_flg,
|
cf=>c_flg,
|
zf=>z_flg,
|
zf=>z_flg,
|
nf=>n_flg,
|
nf=>n_flg,
|
vf=>v_flg,
|
vf=>v_flg,
|
pc_cf=>pc_c_alu_flg,
|
pc_cf=>pc_c_alu_flg,
|
dout=>alu_bus
|
dout=>alu_bus
|
);
|
);
|
|
|
u14:addrmux port map(sel=>pcmp,
|
u14:addrmux port map(sel=>pcmp,
|
a=>i_addr_bus,
|
a=>i_addr_bus,
|
b=>mp_bus,
|
b=>mp_bus,
|
dbr=>b_bus,
|
dbr=>b_bus,
|
s=>sp_bus,
|
s=>sp_bus,
|
xr=>x_bus,
|
xr=>x_bus,
|
yr=>y_bus,
|
yr=>y_bus,
|
y=>addr
|
y=>addr
|
);
|
);
|
|
|
u15:regmux port map(sel=>rsel,
|
u15:regmux port map(sel=>rsel,
|
a=>dbin,
|
a=>dbin,
|
b=>a_bus,
|
b=>a_bus,
|
c=>x_bus,
|
c=>x_bus,
|
d=>y_bus,
|
d=>y_bus,
|
e=>sp_bus,
|
e=>sp_bus,
|
g=>p_bus,
|
g=>p_bus,
|
h=>pc_bus(7 downto 0),
|
h=>pc_bus(7 downto 0),
|
i=>pc_bus(15 downto 8),
|
i=>pc_bus(15 downto 8),
|
j=>o_bus,
|
j=>o_bus,
|
k=>d_bus,
|
k=>d_bus,
|
l=>k_bus,
|
l=>k_bus,
|
m=>b_bus,
|
m=>b_bus,
|
y=>r_bus
|
y=>r_bus
|
);
|
);
|
|
|
u16:dmux port map(sel=>dmux_sel,
|
u16:dmux port map(sel=>dmux_sel,
|
a=>o_bus,
|
a=>o_bus,
|
b=>dbin,
|
b=>dbin,
|
y=>oper_bus
|
y=>oper_bus
|
);
|
);
|
|
|
u17:mcseq port map(clk=>clk0,
|
u17:mcseq port map(clk=>clk0,
|
clr=>opdec,
|
clr=>opdec,
|
mc_nop=>mcn,
|
mc_nop=>mcn,
|
fwait=>i_rdy or mul_busy,
|
fwait=>i_rdy or mul_busy,
|
q=>mcscan
|
q=>mcscan
|
);
|
);
|
|
|
u18:mcpla port map(em=>emu,
|
u18:mcpla port map(em=>emu,
|
m=>m_bit,
|
m=>m_bit,
|
x=>x_bit,
|
x=>x_bit,
|
a=>mc_addr,
|
a=>mc_addr,
|
q=>mcbit
|
q=>mcbit
|
);
|
);
|
|
|
u19:decreg port map(r=>regop,
|
u19:decreg port map(r=>regop,
|
y=>regbit
|
y=>regbit
|
);
|
);
|
|
|
u20:cpufsm port map(clk=>clk0,
|
u20:cpufsm port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
fwait=>i_rdy,
|
fwait=>i_rdy,
|
ireq=>int,
|
ireq=>int,
|
aim=>ai_op,
|
aim=>ai_op,
|
bcarry=>pcc,
|
bcarry=>pcc,
|
icarry=>acr_reg,
|
icarry=>acr_reg,
|
p1=>pcmp_mc,
|
p1=>pcmp_mc,
|
e_ei=>e_eop,
|
e_ei=>e_eop,
|
mc_ei=>mc_eop,
|
mc_ei=>mc_eop,
|
addsub=>add_sub_op,
|
addsub=>add_sub_op,
|
dec_mode=>p_bus(3),
|
dec_mode=>p_bus(3),
|
fetch=>opfetch,
|
fetch=>opfetch,
|
op_sync=>i_sync,
|
op_sync=>i_sync,
|
pci=>pcinc,
|
pci=>pcinc,
|
pq=>pcmp,
|
pq=>pcmp,
|
fb=>fbrk,
|
fb=>fbrk,
|
od=>opdec,
|
od=>opdec,
|
mc_nop=>mcn
|
mc_nop=>mcn
|
);
|
);
|
|
|
u21:intlog port map(clk=>clk0,
|
u21:intlog port map(clk=>clk0,
|
iack=>clri,
|
iack=>clri,
|
r=>i_res,
|
r=>i_res,
|
n=>i_nmi,
|
n=>i_nmi,
|
i=>i_irq,
|
i=>i_irq,
|
brk=>opbrk,
|
brk=>opbrk,
|
cop=>opcop,
|
cop=>opcop,
|
e=>emu,
|
e=>emu,
|
gmask=>two_byte_op,
|
gmask=>two_byte_op,
|
imask=>ien,
|
imask=>ien,
|
ioffs=>mp_bus(7 downto 0),
|
ioffs=>mp_bus(7 downto 0),
|
ireq=>int,
|
ireq=>int,
|
voffs=>ivoffs
|
voffs=>ivoffs
|
);
|
);
|
|
|
u22:branch port map(op=>op_bus(7 downto 4),
|
u22:branch port map(op=>op_bus(7 downto 4),
|
n=>p_bus(7),
|
n=>p_bus(7),
|
v=>p_bus(6),
|
v=>p_bus(6),
|
z=>p_bus(1),
|
z=>p_bus(1),
|
c=>p_bus(0),
|
c=>p_bus(0),
|
bres=>branch_taken
|
bres=>branch_taken
|
);
|
);
|
|
|
u23:pre_dec port map(op=>dbin,
|
u23:pre_dec port map(op=>dbin,
|
fetch=>opfetch,
|
fetch=>opfetch,
|
ei=>e_eop,
|
ei=>e_eop,
|
dec=>add_sub_op
|
dec=>add_sub_op
|
);
|
);
|
|
|
u24:multiplier port map(clk=>clk0,
|
u24:multiplier port map(clk=>clk0,
|
clr=>i_res,
|
clr=>i_res,
|
init=>mul_init,
|
init=>mul_init,
|
start_u=>mul_start_u,
|
start_u=>mul_start_u,
|
start_s=>mul_start_s,
|
start_s=>mul_start_s,
|
mpcand=>a_bus,
|
mpcand=>a_bus,
|
mplier=>x_bus,
|
mplier=>x_bus,
|
busy=>mul_busy,
|
busy=>mul_busy,
|
res_lsb=>mul_r_lsb,
|
res_lsb=>mul_r_lsb,
|
res_msb=>mul_r_msb,
|
res_msb=>mul_r_msb,
|
z_flg=>mul_z_flg,
|
z_flg=>mul_z_flg,
|
n_flg=>mul_n_flg
|
n_flg=>mul_n_flg
|
);
|
);
|
|
|
-- asynchronous CPU link section
|
-- asynchronous CPU link section
|
mc_addr <= two_byte_op & mcad;
|
mc_addr <= two_byte_op & mcad;
|
e <= emu; -- emulation mode
|
e <= emu; -- emulation mode
|
ien <= p_bus(2); -- P(I) flag
|
ien <= p_bus(2); -- P(I) flag
|
i_res <= not res; -- internal reset
|
i_res <= not res; -- internal reset
|
i_nmi <= not nmi; -- internal NMI
|
i_nmi <= not nmi; -- internal NMI
|
i_irq <= not irq; -- internal IRQ
|
i_irq <= not irq; -- internal IRQ
|
e_rdy <= not rdy; -- external RDY inverted
|
e_rdy <= not rdy; -- external RDY inverted
|
i_rdy <= e_rdy or wai_ff or stp_ff; -- internal RDY
|
i_rdy <= e_rdy or wai_ff or stp_ff; -- internal RDY
|
mcad <= op_bus & mcscan; -- microcode address
|
mcad <= op_bus & mcscan; -- microcode address
|
rsel <= mcbit(4 downto 0); -- registers read microcode
|
rsel <= mcbit(4 downto 0); -- registers read microcode
|
regop <= mcbit(10 downto 5); -- registers operation microcode
|
regop <= mcbit(10 downto 5); -- registers operation microcode
|
aluop <= mcbit(15 downto 11); -- ALU microcode
|
aluop <= mcbit(15 downto 11); -- ALU microcode
|
p_op <= mcbit(20 downto 16); -- register P microcode
|
p_op <= mcbit(20 downto 16); -- register P microcode
|
mpr_fc <= mcbit(25 downto 21); -- MPR microcode
|
mpr_fc <= mcbit(25 downto 21); -- MPR microcode
|
pcr_fc <= mcbit(29 downto 26); -- PCR microcode
|
pcr_fc <= mcbit(29 downto 26); -- PCR microcode
|
pcmp_mc <= mcbit(32 downto 30); -- PCR/MPR multiplexer microcode
|
pcmp_mc <= mcbit(32 downto 30); -- PCR/MPR multiplexer microcode
|
clri <= mcbit(33); -- clear interrupt request
|
clri <= mcbit(33); -- clear interrupt request
|
we_mc <= mcbit(34); -- write enable (combinatorial) microcode
|
we_mc <= mcbit(34); -- write enable (combinatorial) microcode
|
we_mc_l <= mcbit(35); -- write enable (latched) microcode
|
we_mc_l <= mcbit(35); -- write enable (latched) microcode
|
mc_eop <= mcbit(36); -- end of instruction reached
|
mc_eop <= mcbit(36); -- end of instruction reached
|
mc_vda <= mcbit(37); -- microcode VDA
|
mc_vda <= mcbit(37); -- microcode VDA
|
mc_vpa <= mcbit(38); -- microcode VPA
|
mc_vpa <= mcbit(38); -- microcode VPA
|
mc_ml <= mcbit(39); -- microcode ML
|
mc_ml <= mcbit(39); -- microcode ML
|
i_vp <= mcbit(40); -- vector pull
|
i_vp <= mcbit(40); -- vector pull
|
ai_op <= mcbit(41); -- opcode with addressing indexed microcode
|
ai_op <= mcbit(41); -- opcode with addressing indexed microcode
|
dmux_sel <= mcbit(44 downto 42); -- data multiplexer microcode
|
dmux_sel <= mcbit(44 downto 42); -- data multiplexer microcode
|
ope <= eop;
|
ope <= eop;
|
i_addr_bus <= k_bus & pc_bus;
|
i_addr_bus <= k_bus & pc_bus;
|
eop <= '1' when mc_eop = '1' or e_eop = '1' else '0';
|
eop <= '1' when mc_eop = '1' or e_eop = '1' else '0';
|
vp <= not i_vp;
|
vp <= not i_vp;
|
op_exp <= two_byte_op;
|
op_exp <= two_byte_op;
|
vda <= m_sync or mc_vda;
|
vda <= m_sync or mc_vda;
|
vpa <= m_sync or mc_vpa;
|
vpa <= m_sync or mc_vpa;
|
ml <= mc_ml;
|
ml <= mc_ml;
|
sw_int <= opbrk or opcop;
|
sw_int <= opbrk or opcop;
|
|
|
-- ALU/memory size
|
-- ALU/memory size
|
m_size8 <= '1' when emu = '1' or m_bit = '1' else
|
m_size8 <= '1' when emu = '1' or m_bit = '1' else
|
'1' when op_bus = x"EB" or op_bus = x"AB" else -- when XBA and PLB opcodes the ALU size is always 8 bit
|
'1' when op_bus = x"EB" or op_bus = x"AB" else -- when XBA and PLB opcodes the ALU size is always 8 bit
|
'1' when (op_bus = x"AA" or op_bus = x"A8") and x_bit = '1' else -- when TAX and TAY opcodes and X is '1' the ALU size is 8 bit
|
'1' when (op_bus = x"AA" or op_bus = x"A8") and x_bit = '1' else -- when TAX and TAY opcodes and X is '1' the ALU size is 8 bit
|
'1' when (op_bus = x"8A" or op_bus = x"98") and m_bit = '1' else -- when TXA and TXA opcodes and M is '1' the ALU size is 8 bit
|
'1' when (op_bus = x"8A" or op_bus = x"98") and m_bit = '1' else -- when TXA and TXA opcodes and M is '1' the ALU size is 8 bit
|
'1' when op_bus = x"68" and m_bit = '1' else -- when PLA opcode and M is '1' the ALU size is 8 bit
|
'1' when op_bus = x"68" and m_bit = '1' else -- when PLA opcode and M is '1' the ALU size is 8 bit
|
'1' when (op_bus = x"FA" or op_bus = x"7A") and x_bit = '1' else -- when PLX or PLY opcode and X = '1' the ALU size is 8 bit
|
'1' when (op_bus = x"FA" or op_bus = x"7A") and x_bit = '1' else -- when PLX or PLY opcode and X = '1' the ALU size is 8 bit
|
'0';
|
'0';
|
m_size16 <= '0' when (op_bus = x"5B" or op_bus = x"7B") else -- when TCD or TDC opcodes the transfer size is always 16 bit
|
m_size16 <= '0' when (op_bus = x"5B" or op_bus = x"7B") else -- when TCD or TDC opcodes the transfer size is always 16 bit
|
'0' when (op_bus = x"1B" or op_bus = x"3B") else -- when TCS or TSC opcodes the transfer size is always 16 bit
|
'0' when (op_bus = x"1B" or op_bus = x"3B") else -- when TCS or TSC opcodes the transfer size is always 16 bit
|
'0' when (op_bus = x"82" or op_bus = x"62") else -- when BRL or PER opcodes the transfer size is always 16 bit
|
'0' when (op_bus = x"82" or op_bus = x"62") else -- when BRL or PER opcodes the transfer size is always 16 bit
|
'0' when op_bus = x"2B" else -- when PLD opcode the transfer size is always 16 bit
|
'0' when op_bus = x"2B" else -- when PLD opcode the transfer size is always 16 bit
|
'0' when (op_bus = x"AB" and two_byte_op = '1') and emu = '0' else -- when PLR opcode and native mode
|
'0' when (op_bus = x"AB" and two_byte_op = '1') and emu = '0' else -- when PLR opcode and native mode
|
'0' when ld_acc = '1' and m_bit = '0' else -- when load accumulator C register
|
'0' when ld_acc = '1' and m_bit = '0' else -- when load accumulator C register
|
'0' when ld_xy = '1' and x_bit = '0' else -- when load X/Y registers (16 bit size)
|
'0' when ld_xy = '1' and x_bit = '0' else -- when load X/Y registers (16 bit size)
|
'1';
|
'1';
|
s_size16 <= '0' when op_bus = x"EB" else '1'; -- special case for XBA: accumulator size is 16 bit so it can reloads itself swapped in only one cycle
|
s_size16 <= '0' when op_bus = x"EB" else '1'; -- special case for XBA: accumulator size is 16 bit so it can reloads itself swapped in only one cycle
|
m_size <= m_size8 and m_size16; -- ALU size
|
m_size <= m_size8 and m_size16; -- ALU size
|
acc_size <= m_size8 and m_size16 and s_size16; -- accumulator register C size
|
acc_size <= m_size8 and m_size16 and s_size16; -- accumulator register C size
|
index_size <= emu or x_bit; -- index registers size
|
index_size <= emu or x_bit; -- index registers size
|
|
|
-- S native/emulation mode (set by XCE opcode and E bit)
|
-- S native/emulation mode (set by XCE opcode and E bit)
|
sp_emu <= p_bus(0) when op_bus = x"FB" else emu;
|
sp_emu <= p_bus(0) when op_bus = x"FB" else emu;
|
|
|
-- register operations
|
-- register operations
|
a_l_lsb <= regbit(0); -- A load lsb
|
a_l_lsb <= regbit(0); -- A load lsb
|
a_l_msb <= regbit(1); -- A load msb
|
a_l_msb <= regbit(1); -- A load msb
|
a_dec <= regbit(2); -- A decrement
|
a_dec <= regbit(2); -- A decrement
|
x_l_lsb <= regbit(3); -- X load lsb
|
x_l_lsb <= regbit(3); -- X load lsb
|
x_l_msb <= regbit(4); -- X load msb
|
x_l_msb <= regbit(4); -- X load msb
|
x_d <= regbit(5); -- X -= 1
|
x_d <= regbit(5); -- X -= 1
|
x_u <= regbit(6); -- X += 1
|
x_u <= regbit(6); -- X += 1
|
y_l_lsb <= regbit(7); -- Y load lsb
|
y_l_lsb <= regbit(7); -- Y load lsb
|
y_l_msb <= regbit(8); -- Y load msb
|
y_l_msb <= regbit(8); -- Y load msb
|
y_d <= regbit(9); -- Y -= 1
|
y_d <= regbit(9); -- Y -= 1
|
y_u <= regbit(10); -- Y += 1
|
y_u <= regbit(10); -- Y += 1
|
d_l_lsb <= regbit(11); -- D load lsb
|
d_l_lsb <= regbit(11); -- D load lsb
|
d_l_msb <= regbit(12); -- D load msb
|
d_l_msb <= regbit(12); -- D load msb
|
o_l <= regbit(13); -- O load msb & lsb
|
o_l <= regbit(13); -- O load msb & lsb
|
o_l_lsb <= regbit(14); -- O load lsb
|
o_l_lsb <= regbit(14); -- O load lsb
|
o_l_msb <= regbit(15); -- O load msb
|
o_l_msb <= regbit(15); -- O load msb
|
sp_ll <= regbit(16); -- S load lsb
|
sp_ll <= regbit(16); -- S load lsb
|
sp_lh <= regbit(17); -- S load msb
|
sp_lh <= regbit(17); -- S load msb
|
sp_u <= regbit(18); -- S += 1
|
sp_u <= regbit(18); -- S += 1
|
sp_d <= regbit(19); -- S -= 1
|
sp_d <= regbit(19); -- S -= 1
|
k_l <= regbit(20); -- PBR K load
|
k_l <= regbit(20); -- PBR K load
|
b_l <= regbit(21); -- DBR B load
|
b_l <= regbit(21); -- DBR B load
|
k_cl <= regbit(22); -- PBR K clear
|
k_cl <= regbit(22); -- PBR K clear
|
b_cl <= regbit(23); -- DBR B clear
|
b_cl <= regbit(23); -- DBR B clear
|
mul_l_res <= regbit(24); -- load multiplication result on A/B and X
|
mul_l_res <= regbit(24); -- load multiplication result on A/B and X
|
mul_init <= regbit(25); -- init multiplier
|
mul_init <= regbit(25); -- init multiplier
|
mul_start_u <= regbit(26); -- start multiplier unsigned
|
mul_start_u <= regbit(26); -- start multiplier unsigned
|
mul_start_s <= regbit(27); -- start multiplier signed
|
mul_start_s <= regbit(27); -- start multiplier signed
|
wai_set <= regbit(28); -- WAI enter wait
|
wai_set <= regbit(28); -- WAI enter wait
|
stp_set <= regbit(29); -- STP enter wait
|
stp_set <= regbit(29); -- STP enter wait
|
we <= we_mc or opfetch; -- write enable
|
we <= we_mc or opfetch; -- write enable
|
m_bit <= p_bus(5) or emu; -- M bit
|
m_bit <= p_bus(5) or emu; -- M bit
|
x_bit <= p_bus(4) or emu; -- X bit
|
x_bit <= p_bus(4) or emu; -- X bit
|
m <= m_bit;
|
m <= m_bit;
|
x <= x_bit;
|
x <= x_bit;
|
kr_clear <= i_res or k_cl;
|
kr_clear <= i_res or k_cl;
|
br_clear <= i_res or b_cl;
|
br_clear <= i_res or b_cl;
|
ld_acc <= regbit(0) and regbit(1);
|
ld_acc <= regbit(0) and regbit(1);
|
ld_xy <= (regbit(3) and regbit(4)) or (regbit(7) and regbit(8));
|
ld_xy <= (regbit(3) and regbit(4)) or (regbit(7) and regbit(8));
|
-- VPA latched
|
-- VPA latched
|
process(clk0)
|
process(clk0)
|
begin
|
begin
|
if (clk0'event and clk0 = '1') then
|
if (clk0'event and clk0 = '1') then
|
if i_rdy = '0' then
|
if i_rdy = '0' then
|
m_sync <= i_sync;
|
m_sync <= i_sync;
|
else
|
else
|
m_sync <= m_sync;
|
m_sync <= m_sync;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- PC carry logic
|
-- PC carry logic
|
process(o_bus,pc_c_alu_flg)
|
process(o_bus,pc_c_alu_flg)
|
begin
|
begin
|
if o_bus(7) = '0' then -- check for positive/negative branch offset (bit 7)
|
if o_bus(7) = '0' then -- check for positive/negative branch offset (bit 7)
|
pcc <= pc_c_alu_flg;
|
pcc <= pc_c_alu_flg;
|
else
|
else
|
pcc <= not pc_c_alu_flg;
|
pcc <= not pc_c_alu_flg;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- write enable registered
|
-- write enable registered
|
process(clk0)
|
process(clk0)
|
begin
|
begin
|
if (clk0'event and clk0 = '1') then
|
if (clk0'event and clk0 = '1') then
|
if i_res = '1' then
|
if i_res = '1' then
|
we_r <= '1';
|
we_r <= '1';
|
else
|
else
|
if i_rdy = '0' then
|
if i_rdy = '0' then
|
we_r <= we_mc_l;
|
we_r <= we_mc_l;
|
else
|
else
|
we_r <= we_r;
|
we_r <= we_r;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
rw <= we and we_r;
|
rw <= we and we_r;
|
|
|
-- WAI
|
-- WAI
|
process(clk0)
|
process(clk0)
|
begin
|
begin
|
if (clk0'event and clk0 = '1') then
|
if (clk0'event and clk0 = '1') then
|
if wai_ff = '0' then
|
if wai_ff = '0' then
|
if wai_set then
|
if wai_set then
|
wai_ff <= '1';
|
wai_ff <= '1';
|
else
|
else
|
wai_ff <= wai_ff;
|
wai_ff <= wai_ff;
|
end if;
|
end if;
|
else
|
else
|
if i_res = '1' or i_nmi = '1' or i_irq = '1' then
|
if i_res = '1' or i_nmi = '1' or i_irq = '1' then
|
wai_ff <= '0';
|
wai_ff <= '0';
|
else
|
else
|
wai_ff <= wai_ff;
|
wai_ff <= wai_ff;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
rdy_out <= not wai_ff;
|
rdy_out <= not wai_ff;
|
|
|
-- STP
|
-- STP
|
process(clk0)
|
process(clk0)
|
begin
|
begin
|
if (clk0'event and clk0 = '1') then
|
if (clk0'event and clk0 = '1') then
|
if stp_ff = '0' then
|
if stp_ff = '0' then
|
if stp_set then
|
if stp_set then
|
stp_ff <= '1';
|
stp_ff <= '1';
|
else
|
else
|
stp_ff <= stp_ff;
|
stp_ff <= stp_ff;
|
end if;
|
end if;
|
else
|
else
|
if i_res = '1' then
|
if i_res = '1' then
|
stp_ff <= '0';
|
stp_ff <= '0';
|
else
|
else
|
stp_ff <= stp_ff;
|
stp_ff <= stp_ff;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
stp_out <= not stp_ff;
|
stp_out <= not stp_ff;
|
|
|
|
|
-- data bus tristate (buffer ring gated) control logic
|
-- data bus tristate (buffer ring gated) control logic
|
--process(clk0,we,we_r,alu_bus)
|
--process(clk0,we,we_r,alu_bus)
|
--begin
|
--begin
|
-- if clock = '0' and (we = '0' or we_r = '0') then
|
-- if clock = '0' and (we = '0' or we_r = '0') then
|
-- data <= alu_bus;
|
-- data <= alu_bus;
|
-- else
|
-- else
|
-- data <= "ZZZZZZZZ";
|
-- data <= "ZZZZZZZZ";
|
-- end if;
|
-- end if;
|
--end process;
|
--end process;
|
|
|
|
|
data_out <= alu_bus(7 downto 0);
|
data_out <= alu_bus(7 downto 0);
|
dbin <= data_in or "00000000";
|
dbin <= data_in or "00000000";
|
-- DEBUG
|
-- DEBUG
|
-- a_reg <= a_bus;
|
-- a_reg <= a_bus;
|
-- x_reg <= x_bus;
|
-- x_reg <= x_bus;
|
-- y_reg <= y_bus;
|
-- y_reg <= y_bus;
|
-- s_reg <= sp_bus;
|
-- s_reg <= sp_bus;
|
-- op_reg <= o_bus;
|
-- op_reg <= o_bus;
|
-- p_reg <= p_bus;
|
-- p_reg <= p_bus;
|
-- k_reg <= k_bus;
|
-- k_reg <= k_bus;
|
-- b_reg <= b_bus;
|
-- b_reg <= b_bus;
|
-- o_reg <= op_bus;
|
-- o_reg <= op_bus;
|
-- mcode <= mcscan;
|
-- mcode <= mcscan;
|
|
|
end struct;
|
end struct;
|
|
|
|
|
|
|
|
|
