`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 19:39:14 08/24/2011
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// Create Date: 19:39:14 08/24/2011
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// Design Name:
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// Design Name:
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// Module Name: divider
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// Module Name: divider
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments: Based on my description on youtube:
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// Additional Comments: Based on my description on youtube:
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// http://youtu.be/TEnaPMYiuR8
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// http://youtu.be/TEnaPMYiuR8
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module qdiv #(
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module qdiv #(
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//Parameterized values
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//Parameterized values
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parameter Q = 15,
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parameter Q = 15,
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parameter N = 32
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parameter N = 32
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)
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)
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(
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(
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input [N-1:0] i_dividend,
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input [N-1:0] i_dividend,
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input [N-1:0] i_divisor,
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input [N-1:0] i_divisor,
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input i_start,
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input i_start,
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input i_clk,
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input i_clk,
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output [N-1:0] o_quotient_out,
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output [N-1:0] o_quotient_out,
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output o_complete,
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output o_complete,
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output o_overflow
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output o_overflow
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);
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);
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reg [2*N+Q-3:0] reg_working_quotient; // Our working copy of the quotient
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reg [2*N+Q-3:0] reg_working_quotient; // Our working copy of the quotient
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reg [N-1:0] reg_quotient; // Final quotient
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reg [N-1:0] reg_quotient; // Final quotient
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reg [N-2+Q:0] reg_working_dividend; // Working copy of the dividend
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reg [N-2+Q:0] reg_working_dividend; // Working copy of the dividend
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reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor
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reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor
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reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
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reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
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// count to N-1+Q but, computing that number of bits requires a
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// count to N-1+Q but, computing that number of bits requires a
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// logarithm (base 2), and I don't know how to do that in a
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// logarithm (base 2), and I don't know how to do that in a
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// way that will work for everyone
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// way that will work for everyone
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reg reg_done; // Computation completed flag
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reg reg_done; // Computation completed flag
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reg reg_sign; // The quotient's sign bit
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reg reg_sign; // The quotient's sign bit
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reg reg_overflow; // Overflow flag
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reg reg_overflow; // Overflow flag
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initial reg_done = 1'b1; // Initial state is to not be doing anything
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initial reg_done = 1'b1; // Initial state is to not be doing anything
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initial reg_overflow = 1'b0; // And there should be no woverflow present
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initial reg_overflow = 1'b0; // And there should be no woverflow present
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initial reg_sign = 1'b0; // And the sign should be positive
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initial reg_sign = 1'b0; // And the sign should be positive
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assign o_quotient_out[N-2:0] = reg_working_quotient; // The division results
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initial reg_working_quotient = 0;
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initial reg_quotient = 0;
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initial reg_working_dividend = 0;
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initial reg_working_divisor = 0;
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initial reg_count = 0;
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assign o_quotient_out[N-2:0] = reg_quotient[N-2:0]; // The division results
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assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
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assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
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assign o_complete = reg_done;
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assign o_complete = reg_done;
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assign o_overflow = reg_overflow;
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assign o_overflow = reg_overflow;
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always @( posedge i_clk ) begin
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always @( posedge i_clk ) begin
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if( reg_done && i_start ) begin // This is our startup condition
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if( reg_done && i_start ) begin // This is our startup condition
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// Need to check for a divide by zero right here, I think....
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// Need to check for a divide by zero right here, I think....
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reg_done <= 1'b0; // We're not done
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reg_done <= 1'b0; // We're not done
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reg_count <= N+Q-2; // Set the count
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reg_count <= N+Q-1; // Set the count
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reg_working_quotient <= 0; // Clear out the quotient register
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reg_working_quotient <= 0; // Clear out the quotient register
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reg_working_dividend <= 0; // Clear out the dividend register
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reg_working_dividend <= 0; // Clear out the dividend register
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reg_working_divisor <= 0; // Clear out the divisor register
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reg_working_divisor <= 0; // Clear out the divisor register
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reg_overflow <= 1'b0; // Clear the overflow register
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reg_overflow <= 1'b0; // Clear the overflow register
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reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; // Left-align the dividend in its working register
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reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; // Left-align the dividend in its working register
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reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; // Left-align the divisor into its working register
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reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; // Left-align the divisor into its working register
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reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; // Set the sign bit
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reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; // Set the sign bit
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end
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end
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else if(!reg_done) begin
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else if(!reg_done) begin
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reg_working_divisor <= reg_working_divisor >> 1; // Right shift the divisor (that is, divide it by two - aka reduce the divisor)
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reg_working_divisor <= reg_working_divisor >> 1; // Right shift the divisor (that is, divide it by two - aka reduce the divisor)
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reg_count <= reg_count - 1; // Decrement the count
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reg_count <= reg_count - 1; // Decrement the count
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// If the dividend is greater than the divisor
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// If the dividend is greater than the divisor
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if(reg_working_dividend >= reg_working_divisor) begin
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if(reg_working_dividend >= reg_working_divisor) begin
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reg_working_quotient[reg_count] <= 1'b1; // Set the quotient bit
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reg_working_quotient[reg_count] <= 1'b1; // Set the quotient bit
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reg_working_dividend <= reg_working_dividend - reg_working_divisor; // and subtract the divisor from the dividend
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reg_working_dividend <= reg_working_dividend - reg_working_divisor; // and subtract the divisor from the dividend
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end
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end
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//stop condition
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//stop condition
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if(reg_count == 0) begin
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if(reg_count == 0) begin
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reg_done <= 1'b1; // If we're done, it's time to tell the calling process
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reg_done <= 1'b1; // If we're done, it's time to tell the calling process
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reg_quotient <= reg_working_quotient; // Move in our working copy to the outside world
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if (reg_working_quotient[2*N+Q-3:N]>0)
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if (reg_working_quotient[2*N+Q-3:N]>0)
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reg_overflow <= 1'b1;
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reg_overflow <= 1'b1;
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end
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end
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else
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else
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reg_count <= reg_count - 1;
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reg_count <= reg_count - 1;
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end
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end
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end
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end
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