module async_fifo_dw_simplex_top (
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module async_fifo_dw_simplex_top (
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// a side
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// a side
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a_d, a_wr, a_fifo_full,
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a_d, a_wr, a_fifo_full,
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a_q, a_rd, a_fifo_empty,
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a_q, a_rd, a_fifo_empty,
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a_clk, a_rst,
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a_clk, a_rst,
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// b side
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// b side
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b_d, b_wr, b_fifo_full,
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b_d, b_wr, b_fifo_full,
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b_q, b_rd, b_fifo_empty,
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b_q, b_rd, b_fifo_empty,
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b_clk, b_rst
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b_clk, b_rst
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);
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);
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parameter data_width = 18;
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parameter data_width = 18;
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parameter addr_width = 4;
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parameter addr_width = 4;
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// a side
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// a side
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input [data_width-1:0] a_d;
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input [data_width-1:0] a_d;
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input a_wr;
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input a_wr;
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output a_fifo_full;
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output a_fifo_full;
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output [data_width-1:0] a_q;
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output [data_width-1:0] a_q;
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input a_rd;
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input a_rd;
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output a_fifo_empty;
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output a_fifo_empty;
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input a_clk;
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input a_clk;
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input a_rst;
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input a_rst;
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// b side
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// b side
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input [data_width-1:0] b_d;
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input [data_width-1:0] b_d;
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input b_wr;
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input b_wr;
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output b_fifo_full;
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output b_fifo_full;
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output [data_width-1:0] b_q;
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output [data_width-1:0] b_q;
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input b_rd;
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input b_rd;
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output b_fifo_empty;
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output b_fifo_empty;
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input b_clk;
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input b_clk;
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input b_rst;
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input b_rst;
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// adr_gen
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// adr_gen
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wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
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wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
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wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
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wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
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// dpram
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// dpram
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wire [addr_width:0] a_dpram_adr, b_dpram_adr;
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wire [addr_width:0] a_dpram_adr, b_dpram_adr;
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adr_gen
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adr_gen
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# ( .length(addr_width))
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# ( .length(addr_width))
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fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
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fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
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adr_gen
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adr_gen
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# (.length(addr_width))
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# (.length(addr_width))
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fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_rst));
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fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
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adr_gen
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adr_gen
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# ( .length(addr_width))
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# ( .length(addr_width))
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fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
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fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
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adr_gen
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adr_gen
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# (.length(addr_width))
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# (.length(addr_width))
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fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_rst));
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fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clkt));
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// mux read or write adr to DPRAM
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// mux read or write adr to DPRAM
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assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
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assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
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assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
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assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
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vfifo_dual_port_ram_dc_dw
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vfifo_dual_port_ram_dc_dw
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# (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width+1))
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# (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width+1))
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dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
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dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
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.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
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.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
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versatile_fifo_async_cmp
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versatile_fifo_async_cmp
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# (.ADDR_WIDTH(addr_width))
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# (.ADDR_WIDTH(addr_width))
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cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
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cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
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versatile_fifo_async_cmp
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versatile_fifo_async_cmp
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# (.ADDR_WIDTH(addr_width))
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# (.ADDR_WIDTH(addr_width))
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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endmodule
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endmodule
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