// true dual port RAM, sync
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// true dual port RAM, sync
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module vfifo_dual_port_ram_`TYPE
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module vfifo_dual_port_ram_`TYPE
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(
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(
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// A side
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// A side
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d_a,
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d_a,
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`ifdef DW
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`ifdef DW
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q_a,
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q_a,
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`endif
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`endif
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adr_a,
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adr_a,
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we_a,
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we_a,
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`ifdef DC
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`ifdef DC
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clk_a,
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clk_a,
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`endif
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`endif
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// B side
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// B side
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q_b,
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q_b,
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adr_b,
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adr_b,
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`ifdef DW
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`ifdef DW
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d_b,
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d_b,
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we_b,
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we_b,
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`endif
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`endif
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`ifdef DC
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`ifdef DC
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clk_b
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clk_b
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`else
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`else
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clk
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clk
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`endif
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`endif
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);
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);
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parameter DATA_WIDTH = 8;
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parameter DATA_WIDTH = 8;
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parameter ADDR_WIDTH = 9;
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parameter ADDR_WIDTH = 9;
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input [(DATA_WIDTH-1):0] d_a;
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input [(DATA_WIDTH-1):0] d_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_b;
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input [(ADDR_WIDTH-1):0] adr_b;
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input we_a;
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input we_a;
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output [(DATA_WIDTH-1):0] q_b;
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output [(DATA_WIDTH-1):0] q_b;
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`ifdef DW
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`ifdef DW
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input [(DATA_WIDTH-1):0] d_b;
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input [(DATA_WIDTH-1):0] d_b;
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output reg [(DATA_WIDTH-1):0] q_a;
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output reg [(DATA_WIDTH-1):0] q_a;
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input we_b;
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input we_b;
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`endif
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`endif
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`ifdef DC
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`ifdef DC
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input clk_a, clk_b;
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input clk_a, clk_b;
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`else
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`else
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input clk;
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input clk;
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`endif
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`endif
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`ifndef DW
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`ifndef DW
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reg [(ADDR_WIDTH-1):0] adr_b_reg;
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reg [(ADDR_WIDTH-1):0] adr_b_reg;
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`else
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`else
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reg [(DATA_WIDTH-1):0] q_b;
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reg [(DATA_WIDTH-1):0] q_b;
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`endif
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`endif
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// Declare the RAM variable
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// Declare the RAM variable
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reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`ifdef DC
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`ifdef DC
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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`else
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`else
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always @ (posedge clk)
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always @ (posedge clk)
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`endif
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`endif
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`ifdef DW
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`ifdef DW
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begin // Port A
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begin // Port A
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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begin
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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q_a <= d_a;
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end
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else
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q_a <= ram[adr_a];
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end
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end
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`else
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`else
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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`endif
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`endif
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`ifdef DC
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`ifdef DC
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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`else
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`else
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always @ (posedge clk)
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always @ (posedge clk)
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`endif
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`endif
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`ifdef DW
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`ifdef DW
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begin // Port b
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begin // Port b
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q_b <= ram[adr_b];
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if (we_b)
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if (we_b)
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begin
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ram[adr_b] <= d_b;
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ram[adr_b] <= d_b;
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q_b <= d_b;
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end
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else
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q_b <= ram[adr_b];
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end
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end
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`else // !`ifdef DW
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`else // !`ifdef DW
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adr_b_reg <= adr_b;
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adr_b_reg <= adr_b;
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assign q_b = ram[adr_b_reg];
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assign q_b = ram[adr_b_reg];
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`endif // !`ifdef DW
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`endif // !`ifdef DW
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endmodule // true_dual_port_ram_sync
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endmodule // true_dual_port_ram_sync
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