URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Diff between revs 2 and 4
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 2 |
Rev 4 |
// true dual port RAM, sync
|
// true dual port RAM, sync
|
module versatile_fifo_dual_port_ram_dc_2w
|
module versatile_fifo_dual_port_ram_`TYPE
|
(
|
(
|
// A side
|
// A side
|
d_a,
|
d_a,
|
`ifdef DW
|
`ifdef DW
|
q_a,
|
q_a,
|
`endif
|
`endif
|
adr_a,
|
adr_a,
|
we_a,
|
we_a,
|
`ifdef DC
|
`ifdef DC
|
clk_a,
|
clk_a,
|
`endif
|
`endif
|
// B side
|
// B side
|
q_b
|
q_b,
|
adr_b,
|
adr_b,
|
`ifdef DW
|
`ifdef DW
|
d_b,
|
d_b,
|
we_b,
|
we_b,
|
`endif
|
`endif
|
`ifdef DC
|
`ifdef DC
|
clk_b
|
clk_b
|
`else
|
`else
|
clk
|
clk
|
`endif
|
`endif
|
);
|
);
|
|
|
parameter DATA_WIDTH = 8;
|
parameter DATA_WIDTH = 8;
|
parameter ADDR_WIDTH = 9;
|
parameter ADDR_WIDTH = 9;
|
|
|
input [(DATA_WIDTH-1):0] data_a;
|
input [(DATA_WIDTH-1):0] d_a;
|
input [(ADDR_WIDTH-1):0] addr_a;
|
input [(ADDR_WIDTH-1):0] adr_a;
|
input [(ADDR_WIDTH-1):0] addr_b;
|
input [(ADDR_WIDTH-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output reg [(DATA_WIDTH-1):0] q_b;
|
output [(DATA_WIDTH-1):0] q_b;
|
`ifdef DW
|
`ifdef DW
|
input [(DATA_WIDTH-1):0] data_b;
|
input [(DATA_WIDTH-1):0] d_b;
|
output reg [(DATA_WIDTH-1):0] q_a;
|
output reg [(DATA_WIDTH-1):0] q_a;
|
input we_b;
|
input we_b;
|
`endif
|
`endif
|
`ifdef DC
|
`ifdef DC
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
`else
|
`else
|
input clk;
|
input clk;
|
`endif
|
`endif
|
|
|
|
`ifndef DW
|
|
reg [(ADDR_WIDTH-1):0] adr_b_reg;
|
|
`else
|
|
reg [(DATA_WIDTH-1):0] q_b;
|
|
`endif
|
|
|
// Declare the RAM variable
|
// Declare the RAM variable
|
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
|
|
`ifdef DC
|
`ifdef DC
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
`else
|
`else
|
always @ (posedge clk)
|
always @ (posedge clk)
|
`endif
|
`endif
|
`ifdef DW
|
`ifdef DW
|
begin // Port A
|
begin // Port A
|
if (we_a)
|
if (we_a)
|
begin
|
begin
|
ram[addr_a] <= data_a;
|
ram[adr_a] <= d_a;
|
q_a <= data_a;
|
q_a <= d_a;
|
end
|
end
|
else
|
else
|
q_a <= ram[addr_a];
|
q_a <= ram[adr_a];
|
end
|
end
|
`else
|
`else
|
if (we_a)
|
if (we_a)
|
ram[addr_a] <= data_a;
|
ram[adr_a] <= d_a;
|
`endif
|
`endif
|
|
|
`ifdef DC
|
`ifdef DC
|
always @ (posedge clk_a)
|
always @ (posedge clk_b)
|
`else
|
`else
|
always @ (posedge clk)
|
always @ (posedge clk)
|
`endif
|
`endif
|
`ifdef DW
|
`ifdef DW
|
begin // Port b
|
begin // Port b
|
if (we_b)
|
if (we_b)
|
begin
|
begin
|
ram[addr_b] <= data_b;
|
ram[adr_b] <= d_b;
|
q_b <= data_b;
|
q_b <= d_b;
|
end
|
end
|
else
|
else
|
q_b <= ram[addr_b];
|
q_b <= ram[adr_b];
|
end
|
end
|
`else // !`ifdef DW
|
`else // !`ifdef DW
|
q_b <= ram[addr_b];
|
adr_b_reg <= adr_b;
|
|
|
|
assign q_b = ram[adr_b_reg];
|
`endif // !`ifdef DW
|
`endif // !`ifdef DW
|
|
|
endmodule // true_dual_port_ram_sync
|
endmodule // true_dual_port_ram_sync
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.