URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_dc_sw.v] - Diff between revs 4 and 12
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 4 |
Rev 12 |
module versatile_fifo_dual_port_ram_dc_sw
|
module vfifo_dual_port_ram_dc_sw
|
(
|
(
|
d_a,
|
d_a,
|
adr_a,
|
adr_a,
|
we_a,
|
we_a,
|
clk_a,
|
clk_a,
|
q_b,
|
q_b,
|
adr_b,
|
adr_b,
|
clk_b
|
clk_b
|
);
|
);
|
parameter DATA_WIDTH = 8;
|
parameter DATA_WIDTH = 8;
|
parameter ADDR_WIDTH = 9;
|
parameter ADDR_WIDTH = 9;
|
input [(DATA_WIDTH-1):0] d_a;
|
input [(DATA_WIDTH-1):0] d_a;
|
input [(ADDR_WIDTH-1):0] adr_a;
|
input [(ADDR_WIDTH-1):0] adr_a;
|
input [(ADDR_WIDTH-1):0] adr_b;
|
input [(ADDR_WIDTH-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(DATA_WIDTH-1):0] q_b;
|
output [(DATA_WIDTH-1):0] q_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(ADDR_WIDTH-1):0] adr_b_reg;
|
reg [(ADDR_WIDTH-1):0] adr_b_reg;
|
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
|
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
if (we_a)
|
if (we_a)
|
ram[adr_a] <= d_a;
|
ram[adr_a] <= d_a;
|
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
adr_b_reg <= adr_b;
|
adr_b_reg <= adr_b;
|
assign q_b = ram[adr_b_reg];
|
assign q_b = ram[adr_b_reg];
|
endmodule
|
endmodule
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.