module versatile_io (
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module versatile_io (
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input [31:0] wbs_dat_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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input [31:0] wbs_adr_i,
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input [3:0] wbs_sel_i,
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input [3:0] wbs_sel_i,
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input wbs_we_i, wbs_stb_i, wbs_cyc_i,
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input wbs_we_i, wbs_stb_i, wbs_cyc_i,
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output [31:0] wbs_dat_o,
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output [31:0] wbs_dat_o,
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output wbs_ack_o,
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output wbs_ack_o,
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`ifdef B4
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`ifdef B4
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output wbs_stall_o,
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output wbs_stall_o,
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`endif
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`endif
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`include "versatile_io_module.v"
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`include "versatile_io_module.v"
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`ifdef UART0
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`ifdef UART0
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output uart0_irq,
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output uart0_irq,
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`endif
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`endif
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input wbs_clk, wbs_rst,
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input wbs_clk, wbs_rst,
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input clk, rst
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input clk, rst
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);
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);
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`ifdef UART0
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`ifdef UART0
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parameter uart0_mem_map_hi = `UART0_MEM_MAP_HI;
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parameter uart0_mem_map_hi = `UART0_MEM_MAP_HI;
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parameter uart0_mem_map_lo = `UART0_MEM_MAP_LO;
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parameter uart0_mem_map_lo = `UART0_MEM_MAP_LO;
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parameter [31:0] uart0_base_adr = `UART0_BASE_ADR;
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parameter [31:0] uart0_base_adr = `UART0_BASE_ADR;
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`endif
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`endif
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function [7:0] tobyte;
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function [7:0] tobyte;
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input [3:0] sel_i;
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input [3:0] sel_i;
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input [31:0] dat_i;
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input [31:0] dat_i;
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begin
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begin
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tobyte = ({8{sel_i[3]}} & dat_i[31:24]) | ({8{sel_i[2]}} & dat_i[23:16]) | ({8{sel_i[1]}} & dat_i[15:8]) | ({8{sel_i[0]}} & dat_i[7:0]);
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tobyte = ({8{sel_i[3]}} & dat_i[31:24]) | ({8{sel_i[2]}} & dat_i[23:16]) | ({8{sel_i[1]}} & dat_i[15:8]) | ({8{sel_i[0]}} & dat_i[7:0]);
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end
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end
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endfunction
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endfunction
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function [31:0] toword;
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function [31:0] toword;
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input [7:0] dat_i;
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input [7:0] dat_i;
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begin
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begin
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toword = {4{dat_i}};
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toword = {4{dat_i}};
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end
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end
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endfunction
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endfunction
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function [31:0] mask;
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function [31:0] mask;
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input [31:0] dat_i;
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input [31:0] dat_i;
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input sel;
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input sel;
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begin
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begin
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mask = {32{sel}} & dat_i;
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mask = {32{sel}} & dat_i;
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end
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end
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endfunction
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endfunction
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`ifdef UART0
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`ifdef UART0
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wire uart0_cs;
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wire uart0_cs;
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assign uart0_cs = wbs_adr_i[uart0_mem_map_hi:uart0_mem_map_lo] == uart0_base_adr[uart0_mem_map_hi:uart0_mem_map_lo];
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assign uart0_cs = wbs_adr_i[uart0_mem_map_hi:uart0_mem_map_lo] == uart0_base_adr[uart0_mem_map_hi:uart0_mem_map_lo];
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wire [7:0] uart0_temp;
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wire [7:0] uart0_temp;
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wire uart0_ack_o;
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wire uart0_ack_o;
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/*
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/*
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uart_top uart0 (
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uart_top uart0 (
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.wb_clk_i(wbs_clk), .wb_rst_i(wbs_rst),
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.wb_clk_i(wbs_clk), .wb_rst_i(wbs_rst),
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// Wishbone signals
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// Wishbone signals
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.wb_adr_i(wbs_adr_i[2:0]), .wb_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), .wb_dat_o(uart0_temp), .wb_we_i(wbs_we_i), .wb_stb_i(wbs_stb_i), .wb_cyc_i(wbs_cyc_i & uart0_cs), .wb_ack_o(uart0_ack_o), .wb_sel_i(4'b0),
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.wb_adr_i(wbs_adr_i[2:0]), .wb_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), .wb_dat_o(uart0_temp), .wb_we_i(wbs_we_i), .wb_stb_i(wbs_stb_i), .wb_cyc_i(wbs_cyc_i & uart0_cs), .wb_ack_o(uart0_ack_o), .wb_sel_i(4'b0),
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.int_o(uart0_irq), // interrupt request
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.int_o(uart0_irq), // interrupt request
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// UART signals
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// UART signals
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// serial input/output
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// serial input/output
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.stx_pad_o(uart0_tx_pad_o), .srx_pad_i(uart0_rx_pad_i),
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.stx_pad_o(uart0_tx_pad_o), .srx_pad_i(uart0_rx_pad_i),
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// modem signals
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// modem signals
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.rts_pad_o(), .cts_pad_i(1'b0), .dtr_pad_o(), .dsr_pad_i(1'b0), .ri_pad_i(1'b0), .dcd_pad_i(1'b0) );
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.rts_pad_o(), .cts_pad_i(1'b0), .dtr_pad_o(), .dsr_pad_i(1'b0), .ri_pad_i(1'b0), .dcd_pad_i(1'b0) );
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*/
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*/
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uart16750_wb uart0(
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uart16750_wb uart0(
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// UART signals
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// UART signals
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.rx(uart0_rx_pad_i),
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.rx(uart0_rx_pad_i),
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.tx(uart0_tx_pad_o),
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.tx(uart0_tx_pad_o),
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.int(uart0_irq),
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.irq(uart0_irq),
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// wishbone slave
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// wishbone slave
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.wbs_dat_i(tobyte(wbs_sel_i,wbs_dat_i)),
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.wbs_dat_i(tobyte(wbs_sel_i,wbs_dat_i)),
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.wbs_adr_i(wbs_adr_i[2:0]),
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.wbs_adr_i(wbs_adr_i[2:0]),
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.wbs_we_i(wbs_we_i),
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.wbs_we_i(wbs_we_i),
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.wbs_cyc_i(wbs_cyc_i & uart0_cs),
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.wbs_cyc_i(wbs_cyc_i & uart0_cs),
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.wbs_stb_i(wbs_stb_i),
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.wbs_stb_i(wbs_stb_i),
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.wbs_dat_o(uart0_temp),
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.wbs_dat_o(uart0_temp),
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.wbs_ack_o(uart0_ack_o),
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.wbs_ack_o(uart0_ack_o),
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.wb_clk_i(wbs_clk),
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.wb_clk_i(wbs_clk),
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.wb_rst_i(wbs_rst) );
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.wb_rst_i(wbs_rst) );
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assign uart0_dat_o = mask( toword(uart0_temp), uart0_ack_o);
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assign uart0_dat_o = mask( toword(uart0_temp), uart0_ack_o);
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`else
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`else
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assign uart0_dat_o = 32'h0;
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assign uart0_dat_o = 32'h0;
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assign uart0_ack_o = 1'b0;
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assign uart0_ack_o = 1'b0;
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`endif
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`endif
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assign wbs_dat_o = uart0_dat_o;
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assign wbs_dat_o = uart0_dat_o;
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assign wbs_ack_o = uart0_ack_o;
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assign wbs_ack_o = uart0_ack_o;
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`ifdef WB4
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`ifdef WB4
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assign wbs_stall_o = 1'b0;
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assign wbs_stall_o = 1'b0;
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`endif
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`endif
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endmodule
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endmodule
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