//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// IO functions ////
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//// IO functions ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// IO functions such as IOB flip-flops ////
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//// IO functions such as IOB flip-flops ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - ////
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//// - ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ORSoC AB ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ns
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`ifdef O_DFF
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`ifdef O_DFF
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`define MODULE o_dff
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`define MODULE o_dff
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module `BASE`MODULE (d_i, o_pad, clk, rst);
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module `BASE`MODULE (d_i, o_pad, clk, rst);
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`undef MODULE
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`undef MODULE
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parameter width = 1;
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parameter width = 1;
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parameter reset_value = {width{1'b0}};
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input [width-1:0] d_i;
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input [width-1:0] d_i;
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output [width-1:0] o_pad;
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output [width-1:0] o_pad;
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input clk, rst;
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input clk, rst;
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wire [width-1:0] d_i_int `SYN_KEEP;
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wire [width-1:0] d_i_int `SYN_KEEP;
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reg [width-1:0] o_pad_int;
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assign d_i_int = d_i;
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assign d_i_int = d_i;
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genvar i;
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genvar i;
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generate
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for (i=0;i<width;i=i+1) begin
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for (i=0;i<width;i=i+1) begin
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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o_pad[i] <= 1'b0;
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o_pad_int[i] <= reset_value[i];
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else
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else
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o_pad[i] <= d_i_int[i];
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o_pad_int[i] <= d_i_int[i];
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assign #1 o_pad[i] = o_pad_int[i];
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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`endif
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`endif
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`timescale 1ns/1ns
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`ifdef IO_DFF_OE
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`ifdef IO_DFF_OE
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`define MODULE io_dff_oe
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`define MODULE io_dff_oe
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module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
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module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
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`undef MODULE
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`undef MODULE
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parameter width = 1;
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parameter width = 1;
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input [width-1:0] d_o;
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input [width-1:0] d_o;
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output reg [width-1:0] d_i;
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output reg [width-1:0] d_i;
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input oe;
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input oe;
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inout [width-1:0] io_pad;
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inout [width-1:0] io_pad;
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input clk, rst;
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input clk, rst;
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wire [width-1:0] oe_d `SYN_KEEP;
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wire [width-1:0] oe_d `SYN_KEEP;
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reg [width-1:0] oe_q;
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reg [width-1:0] oe_q;
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reg [width-1:0] d_o_q;
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reg [width-1:0] d_o_q;
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assign oe_d = {width{oe}};
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assign oe_d = {width{oe}};
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genvar i;
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genvar i;
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generate
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generate
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for (i=0;i<width;i=i+1) begin
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for (i=0;i<width;i=i+1) begin
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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oe_q[i] <= 1'b0;
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oe_q[i] <= 1'b0;
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else
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else
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oe_q[i] <= oe_d[i];
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oe_q[i] <= oe_d[i];
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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d_o_q[i] <= 1'b0;
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d_o_q[i] <= 1'b0;
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else
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else
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d_o_q[i] <= d_o[i];
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d_o_q[i] <= d_o[i];
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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d_i[i] <= 1'b0;
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d_i[i] <= 1'b0;
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else
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else
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d_i[i] <= io_pad[i];
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d_i[i] <= io_pad[i];
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assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
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assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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`endif
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`endif
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