//`include "tb_defines.v"
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//`include "tb_defines.v"
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module versatile_mem_ctrl_tb
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module versatile_mem_ctrl_tb
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(
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(
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output OK
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output OK
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);
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);
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`ifdef NR_OF_WBM
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`ifdef NR_OF_WBM
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parameter nr_of_wbm = `NR_OF_WBM;
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parameter nr_of_wbm = `NR_OF_WBM;
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`else
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`else
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parameter nr_of_wbm = 1;
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parameter nr_of_wbm = 1;
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`endif
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`endif
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`ifdef SDRAM_CLK_PERIOD
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`ifdef SDRAM_CLK_PERIOD
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parameter sdram_clk_period = `SDRAM_CLK_PERIOD;
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parameter sdram_clk_period = `SDRAM_CLK_PERIOD;
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`else
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`else
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parameter sdram_clk_period = 8;
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parameter sdram_clk_period = 8;
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`endif
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`endif
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`ifdef WB_CLK_PERIODS
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`ifdef WB_CLK_PERIODS
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parameter [1:nr_of_wbm] wb_clk_periods = {`WB_CLK_PERIODS};
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parameter [1:nr_of_wbm] wb_clk_periods = {`WB_CLK_PERIODS};
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`else
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`else
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parameter [1:nr_of_wbm] wb_clk_periods = (20);
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parameter [1:nr_of_wbm] wb_clk_periods = (20);
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`endif
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`endif
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parameter wb_clk_period = 20;
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parameter wb_clk_period = 20;
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wire [31:0] wbm_a_dat_o;
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wire [31:0] wbm_a_dat_o;
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wire [3:0] wbm_a_sel_o;
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wire [3:0] wbm_a_sel_o;
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wire [31:0] wbm_a_adr_o;
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wire [31:0] wbm_a_adr_o;
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wire [2:0] wbm_a_cti_o;
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wire [2:0] wbm_a_cti_o;
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wire [1:0] wbm_a_bte_o;
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wire [1:0] wbm_a_bte_o;
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wire wbm_a_we_o ;
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wire wbm_a_we_o ;
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wire wbm_a_cyc_o;
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wire wbm_a_cyc_o;
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wire wbm_a_stb_o;
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wire wbm_a_stb_o;
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wire [31:0] wbm_a_dat_i;
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wire [31:0] wbm_a_dat_i;
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wire wbm_a_ack_i;
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wire wbm_a_ack_i;
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reg wbm_a_clk ;
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reg wbm_a_clk ;
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reg wbm_a_rst ;
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reg wbm_a_rst ;
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wire [31:0] wbm_b_dat_o;
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wire [31:0] wbm_b_dat_o;
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wire [3:0] wbm_b_sel_o;
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wire [3:0] wbm_b_sel_o;
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wire [31:2] wbm_b_adr_o;
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wire [31:2] wbm_b_adr_o;
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wire [2:0] wbm_b_cti_o;
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wire [2:0] wbm_b_cti_o;
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wire [1:0] wbm_b_bte_o;
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wire [1:0] wbm_b_bte_o;
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wire wbm_b_we_o ;
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wire wbm_b_we_o ;
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wire wbm_b_cyc_o;
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wire wbm_b_cyc_o;
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wire wbm_b_stb_o;
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wire wbm_b_stb_o;
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wire [31:0] wbm_b_dat_i;
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wire [31:0] wbm_b_dat_i;
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wire wbm_b_ack_i;
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wire wbm_b_ack_i;
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wire [31:0] wb_sdram_dat_i;
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wire [31:0] wb_sdram_dat_i;
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wire [3:0] wb_sdram_sel_i;
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wire [3:0] wb_sdram_sel_i;
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wire [31:2] wb_sdram_adr_i;
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wire [31:2] wb_sdram_adr_i;
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wire [2:0] wb_sdram_cti_i;
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wire [2:0] wb_sdram_cti_i;
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wire [1:0] wb_sdram_bte_i;
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wire [1:0] wb_sdram_bte_i;
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wire wb_sdram_we_i;
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wire wb_sdram_we_i;
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wire wb_sdram_cyc_i;
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wire wb_sdram_cyc_i;
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wire wb_sdram_stb_i;
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wire wb_sdram_stb_i;
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wire [31:0] wb_sdram_dat_o;
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wire [31:0] wb_sdram_dat_o;
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wire wb_sdram_ack_o;
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wire wb_sdram_ack_o;
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reg wb_sdram_clk;
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reg wb_sdram_clk;
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reg wb_sdram_rst;
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reg wb_sdram_rst;
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wire wbm_OK;
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wire wbm_OK;
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genvar i;
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genvar i;
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`define DUT sdr_sdram_16_ctrl
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`define DUT sdr_sdram_16_ctrl
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`define SDR 16
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`define SDR 16
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`ifdef SDR
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`ifdef SDR
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wire [1:0] ba, ba_pad;
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wire [1:0] ba, ba_pad;
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wire [12:0] a, a_pad;
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wire [12:0] a, a_pad;
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wire [`SDR-1:0] dq_i, dq_o, dq_pad;
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wire [`SDR-1:0] dq_i, dq_o, dq_pad;
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wire dq_oe;
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wire dq_oe;
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wire [1:0] dqm, dqm_pad;
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wire [1:0] dqm, dqm_pad;
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wire cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad;
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wire cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad;
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vl_o_dff # ( .width(20), .reset_value({2'b00, 13'h0,3'b111,2'b11})) o0(
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vl_o_dff # ( .width(20), .reset_value({2'b00, 13'h0,3'b111,2'b11})) o0(
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.d_i({ba,a,ras,cas,we,dqm}),
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.d_i({ba,a,ras,cas,we,dqm}),
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.o_pad({ba_pad,a_pad,ras_pad, cas_pad, we_pad, dqm_pad}),
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.o_pad({ba_pad,a_pad,ras_pad, cas_pad, we_pad, dqm_pad}),
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.clk(wb_sdram_clk),
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.clk(wb_sdram_clk),
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.rst(wb_sdram_rst));
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.rst(wb_sdram_rst));
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/*
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/*
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assign #1 {ba_pad,a_pad} = {ba,a};
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assign #1 {ba_pad,a_pad} = {ba,a};
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assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we};
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assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we};
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assign #1 dqm_pad = dqm;*/
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assign #1 dqm_pad = dqm;*/
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assign #1 cke_pad = cke;
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assign #1 cke_pad = cke;
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assign cs_n_pad = cs_n;
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assign cs_n_pad = cs_n;
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vl_io_dff_oe # ( .width(16)) io0 (
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vl_io_dff_oe # ( .width(16)) io0 (
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.d_i(dq_i),
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.d_i(dq_i),
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.d_o(dq_o),
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.d_o(dq_o),
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.oe(dq_oe),
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.oe(dq_oe),
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.io_pad(dq_pad),
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.io_pad(dq_pad),
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.clk(wb_sdram_clk),
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.clk(wb_sdram_clk),
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.rst(wb_sdram_rst));
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.rst(wb_sdram_rst));
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mt48lc16m16a2 mem(
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mt48lc16m16a2 mem(
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.Dq(dq_pad),
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.Dq(dq_pad),
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.Addr(a_pad),
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.Addr(a_pad),
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.Ba(ba_pad),
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.Ba(ba_pad),
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.Clk(wb_sdram_clk),
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.Clk(wb_sdram_clk),
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.Cke(cke_pad),
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.Cke(cke_pad),
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.Cs_n(cs_n_pad),
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.Cs_n(cs_n_pad),
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.Ras_n(ras_pad),
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.Ras_n(ras_pad),
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.Cas_n(cas_pad),
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.Cas_n(cas_pad),
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.We_n(we_pad),
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.We_n(we_pad),
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.Dqm(dqm_pad));
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.Dqm(dqm_pad));
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`DUT
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`DUT
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# (.tRFC(9), .cl(3))
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# (.tRFC(9), .cl(3))
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DUT(
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DUT(
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// wisbone i/f
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// wisbone i/f
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.dat_i(wbm_b_dat_o),
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.dat_i(wbm_b_dat_o),
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.adr_i({wbm_b_adr_o[24:2],1'b0}),
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.adr_i({wbm_b_adr_o[24:2],1'b0}),
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.sel_i(wbm_b_sel_o),
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.sel_i(wbm_b_sel_o),
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`ifndef NO_BURST
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`ifndef NO_BURST
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.bte_i(wbm_b_bte_o),
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.bte_i(wbm_b_bte_o),
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`endif
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`endif
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.we_i (wbm_b_we_o),
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.we_i (wbm_b_we_o),
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.cyc_i(wbm_b_cyc_o),
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.cyc_i(wbm_b_cyc_o),
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.stb_i(wbm_b_stb_o),
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.stb_i(wbm_b_stb_o),
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.dat_o(wbm_b_dat_i),
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.dat_o(wbm_b_dat_i),
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.ack_o(wbm_b_ack_i),
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.ack_o(wbm_b_ack_i),
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// SDR SDRAM
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// SDR SDRAM
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.ba(ba),
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.ba(ba),
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.a(a),
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.a(a),
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.cmd({ras, cas, we}),
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.cmd({ras, cas, we}),
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.cke(cke),
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.cke(cke),
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.cs_n(cs_n),
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.cs_n(cs_n),
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.dqm(dqm),
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.dqm(dqm),
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.dq_i(dq_i),
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.dq_i(dq_i),
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.dq_o(dq_o),
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.dq_o(dq_o),
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.dq_oe(dq_oe),
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.dq_oe(dq_oe),
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// system
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// system
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.clk(wb_sdram_clk), .rst(wb_sdram_rst));
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.clk(wb_sdram_clk), .rst(wb_sdram_rst));
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`endif
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`endif
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// wishbone master
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// wishbone master
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wbm wbmi(
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wbm wbmi(
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.adr_o(wbm_a_adr_o),
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.adr_o(wbm_a_adr_o),
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.bte_o(wbm_a_bte_o),
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.bte_o(wbm_a_bte_o),
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.cti_o(wbm_a_cti_o),
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.cti_o(wbm_a_cti_o),
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.dat_o(wbm_a_dat_o),
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.dat_o(wbm_a_dat_o),
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.sel_o(wbm_a_sel_o),
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.sel_o(wbm_a_sel_o),
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.we_o (wbm_a_we_o),
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.we_o (wbm_a_we_o),
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.cyc_o(wbm_a_cyc_o),
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.cyc_o(wbm_a_cyc_o),
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.stb_o(wbm_a_stb_o),
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.stb_o(wbm_a_stb_o),
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.dat_i(wbm_a_dat_i),
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.dat_i(wbm_a_dat_i),
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.ack_i(wbm_a_ack_i),
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.ack_i(wbm_a_ack_i),
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.clk(wbm_a_clk),
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.clk(wbm_a_clk),
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.reset(wbm_a_rst),
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.reset(wbm_a_rst),
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.OK(wbm_OK)
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.OK(wbm_OK)
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);
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);
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vl_wb3wb3_bridge wbwb_bridgei (
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vl_wb3wb3_bridge wbwb_bridgei (
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// wishbone slave side
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// wishbone slave side
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.wbs_dat_i(wbm_a_dat_o),
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.wbs_dat_i(wbm_a_dat_o),
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.wbs_adr_i(wbm_a_adr_o[31:2]),
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.wbs_adr_i(wbm_a_adr_o[31:2]),
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.wbs_sel_i(wbm_a_sel_o),
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.wbs_sel_i(wbm_a_sel_o),
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.wbs_bte_i(wbm_a_bte_o),
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.wbs_bte_i(wbm_a_bte_o),
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.wbs_cti_i(wbm_a_cti_o),
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.wbs_cti_i(wbm_a_cti_o),
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.wbs_we_i (wbm_a_we_o),
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.wbs_we_i (wbm_a_we_o),
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.wbs_cyc_i(wbm_a_cyc_o),
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.wbs_cyc_i(wbm_a_cyc_o),
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.wbs_stb_i(wbm_a_stb_o),
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.wbs_stb_i(wbm_a_stb_o),
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.wbs_dat_o(wbm_a_dat_i),
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.wbs_dat_o(wbm_a_dat_i),
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.wbs_ack_o(wbm_a_ack_i),
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.wbs_ack_o(wbm_a_ack_i),
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.wbs_clk(wbm_a_clk),
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.wbs_clk(wbm_a_clk),
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.wbs_rst(wbm_a_rst),
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.wbs_rst(wbm_a_rst),
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// wishbone master side
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// wishbone master side
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.wbm_dat_o(wbm_b_dat_o),
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.wbm_dat_o(wbm_b_dat_o),
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.wbm_adr_o(wbm_b_adr_o),
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.wbm_adr_o(wbm_b_adr_o),
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.wbm_sel_o(wbm_b_sel_o),
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.wbm_sel_o(wbm_b_sel_o),
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.wbm_bte_o(wbm_b_bte_o),
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.wbm_bte_o(wbm_b_bte_o),
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.wbm_cti_o(wbm_b_cti_o),
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.wbm_cti_o(wbm_b_cti_o),
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.wbm_we_o (wbm_b_we_o),
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.wbm_we_o (wbm_b_we_o),
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.wbm_cyc_o(wbm_b_cyc_o),
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.wbm_cyc_o(wbm_b_cyc_o),
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.wbm_stb_o(wbm_b_stb_o),
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.wbm_stb_o(wbm_b_stb_o),
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.wbm_dat_i(wbm_b_dat_i),
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.wbm_dat_i(wbm_b_dat_i),
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.wbm_ack_i(wbm_b_ack_i),
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.wbm_ack_i(wbm_b_ack_i),
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.wbm_clk(wb_sdram_clk),
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.wbm_clk(wb_sdram_clk),
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.wbm_rst(wb_sdram_rst));
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.wbm_rst(wb_sdram_rst));
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assign OK = wbm_OK;
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assign OK = wbm_OK;
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// Wishbone reset
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// Wishbone reset
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initial
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initial
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begin
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begin
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#0 wbm_a_rst = 1'b1;
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#0 wbm_a_rst = 1'b1;
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#200 wbm_a_rst = 1'b0;
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#200 wbm_a_rst = 1'b0;
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end
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end
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// Wishbone clock
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// Wishbone clock
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initial
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initial
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begin
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begin
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#0 wbm_a_clk = 1'b0;
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#0 wbm_a_clk = 1'b0;
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forever
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forever
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#(wb_clk_period/2) wbm_a_clk = !wbm_a_clk;
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#(wb_clk_period/2) wbm_a_clk = !wbm_a_clk;
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end
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end
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// SDRAM reset
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// SDRAM reset
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initial
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initial
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begin
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begin
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#0 wb_sdram_rst = 1'b1;
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#0 wb_sdram_rst = 1'b1;
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#200 wb_sdram_rst = 1'b0;
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#200 wb_sdram_rst = 1'b0;
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end
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end
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// SDRAM clock
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// SDRAM clock
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initial
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initial
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begin
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begin
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#0 wb_sdram_clk = 1'b0;
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#0 wb_sdram_clk = 1'b0;
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forever
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forever
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#(sdram_clk_period/2) wb_sdram_clk = !wb_sdram_clk;
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#(sdram_clk_period/2) wb_sdram_clk = !wb_sdram_clk;
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end
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end
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endmodule // versatile_mem_ctrl_tb
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endmodule // versatile_mem_ctrl_tb
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