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`timescale 1ns/1ns
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module wbm (
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module wbm (
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output [31:0] adr_o,
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output [31:0] adr_o,
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output [1:0] bte_o,
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output [1:0] bte_o,
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output [2:0] cti_o,
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output [2:0] cti_o,
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output [31:0] dat_o,
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output [31:0] dat_o,
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output [3:0] sel_o,
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output [3:0] sel_o,
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output we_o,
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output we_o,
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output cyc_o,
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output cyc_o,
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output stb_o,
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output stb_o,
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input wire [31:0] dat_i,
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input wire [31:0] dat_i,
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input wire ack_i,
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input wire ack_i,
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input wire clk,
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input wire clk,
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input wire reset,
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input wire reset,
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output reg OK
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output reg OK
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);
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);
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parameter [1:0] linear = 2'b00,
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parameter [1:0] linear = 2'b00,
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beat4 = 2'b01,
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beat4 = 2'b01,
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beat8 = 2'b10,
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beat8 = 2'b10,
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beat16 = 2'b11;
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beat16 = 2'b11;
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parameter [2:0] classic = 3'b000,
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parameter [2:0] classic = 3'b000,
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inc = 3'b010,
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inc = 3'b010,
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eob = 3'b111;
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eob = 3'b111;
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parameter instructions = 32;
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parameter instructions = 32;
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// {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o}
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parameter [32+2+3+32+4+1+1+1:1] inst_rom [0:instructions-1]= {
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parameter [32+2+3+32+4+1+1+1:1] inst_rom [0:instructions-1]= {
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h100,linear,classic,32'h12345678,4'b1111,1'b1,1'b1,1'b1},
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{32'h100,linear,classic,32'h0,4'b1111,1'b0,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA000,beat4,inc,32'h00010002,4'b1111,1'b1,1'b1,1'b1}, // write burst
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA004,beat4,inc,32'h00030004,4'b1111,1'b1,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA008,beat4,inc,32'h00050006,4'b1111,1'b1,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA00C,beat4,eob,32'h00070008,4'b1111,1'b1,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA008,linear,classic,32'hA1FFFFFF,4'b1000,1'b1,1'b1,1'b1},// write byte
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA000,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read burst
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA004,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA008,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA00C,beat4,eob,32'h0,4'b1111,1'b0,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h1000,linear,inc,32'hdeaddead,4'b1111,1'b1,1'b1,1'b1}, // write
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h1004,linear,eob,32'h55555555,4'b1111,1'b1,1'b1,1'b1}, //
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h1000,linear,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h1004,linear,eob,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'hA008,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read burst
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{32'hA00C,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
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{32'hA000,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
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{32'hA004,beat4,eob,32'h0,4'b1111,1'b0,1'b1,1'b1},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}};
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{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}};
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parameter [31:0] dat [0:instructions-1] = {
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parameter [31:0] dat [0:instructions-1] = {
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h12345678,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h00010002,
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32'h00030004,
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32'ha1050006,
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32'h00070008,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'hdeaddead,
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32'h0,
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32'h55555555,
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32'h0,
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32'ha1050006,
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32'h0,
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32'h00070008,
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32'h0,
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32'h00010002,
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32'h0,
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32'h00030004,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0,
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32'h0};
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32'h0};
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// parameter idle = 1'b0;
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// parameter idle = 1'b0;
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// parameter active = 1'b1;
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// parameter active = 1'b1;
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//
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//
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// reg state;
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// reg state;
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integer i;
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integer i;
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assign {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o} = inst_rom[i];
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assign {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o} = inst_rom[i];
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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if (reset)
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if (reset)
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i = 0;
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i = 0;
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else
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else
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if ((!stb_o | ack_i) & i < instructions)
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if ((!stb_o | ack_i) & i < instructions - 1)
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i = i + 1;
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i = i + 1;
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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if (reset)
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if (reset)
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OK <= 1'b1;
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OK <= 1'b1;
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else
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else
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if (ack_i & !we_o & (dat_i != dat[i]))
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if (ack_i & !we_o & (dat_i != dat[i])) begin
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OK <= 1'b0;
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OK <= 1'b0;
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//assert "Read error";
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$display ("wrong read value %h at %t", dat_i, $time);
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end
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// always @ (posedge clk or posedge reset)
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// always @ (posedge clk or posedge reset)
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// if (reset)
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// if (reset)
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// state <= idle;
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// state <= idle;
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// else
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// else
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// if (state==idle & cyc_o)
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// if (state==idle & cyc_o)
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// state <= active;
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// state <= active;
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// else if ((cti_o==3'b000 | cti_o==3'b111) & cyc_o & stb_o & ack_i)
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// else if ((cti_o==3'b000 | cti_o==3'b111) & cyc_o & stb_o & ack_i)
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// state <= idle;
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// state <= idle;
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endmodule
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endmodule
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