# Usage:
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# Usage:
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# cd /versatile_mem_ctrl/trunk/sim/rtl_sim/run/
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# cd /versatile_mem_ctrl/trunk/sim/rtl_sim/run/
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# vsim -gui -do ../bin/sim_xilinx.tcl
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# vsim -gui -do ../bin/sim_xilinx.tcl
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set DESIGN_NAME "versatile_memory_controller"
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set DESIGN_NAME "versatile_memory_controller"
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set WAVE_FILE wave_ddr.do
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set WAVE_FILE wave_ddr.do
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set FORCE_LIBRARY_RECOMPILE 0
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set FORCE_LIBRARY_RECOMPILE 0
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# Quit simulation if you are running one
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# Quit simulation if you are running one
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quit -sim
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quit -sim
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# Create and open project
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# Create and open project
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if {[file exists ${DESIGN_NAME}_sim_xilinx.mpf]} {
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if {[file exists ${DESIGN_NAME}_sim_xilinx.mpf]} {
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project open ${DESIGN_NAME}_sim_xilinx
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project open ${DESIGN_NAME}_sim_xilinx
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} else {
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} else {
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project new . ${DESIGN_NAME}_sim_xilinx
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project new . ${DESIGN_NAME}_sim_xilinx
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}
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}
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# Compile Xilinx libraries
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# Compile Xilinx libraries
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if {![file exists unisims_ver] || $FORCE_LIBRARY_RECOMPILE} {
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if {![file exists unisims_ver] || $FORCE_LIBRARY_RECOMPILE} {
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vlib unisims_ver
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vlib unisims_ver
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vmap unisims_ver unisims_ver
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vmap unisims_ver unisims_ver
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vlog -work unisims_ver /opt/Xilinx/11.1/ISE/verilog/src/unisims/*.v
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vlog -work unisims_ver /opt/Xilinx/11.1/ISE/verilog/src/unisims/*.v
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}
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}
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if {![file exists simprims_ver] || $FORCE_LIBRARY_RECOMPILE} {
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if {![file exists simprims_ver] || $FORCE_LIBRARY_RECOMPILE} {
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vlib simprims_ver
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vlib simprims_ver
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vmap simprims_ver simprims_ver
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vmap simprims_ver simprims_ver
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vlog -work simprims_ver /opt/Xilinx/11.1/ISE/verilog/src/simprims/*.v
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vlog -work simprims_ver /opt/Xilinx/11.1/ISE/verilog/src/simprims/*.v
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}
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}
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if {![file exists xilinxcorelib_ver] || $FORCE_LIBRARY_RECOMPILE} {
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if {![file exists xilinxcorelib_ver] || $FORCE_LIBRARY_RECOMPILE} {
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vlib xilinxcorelib_ver
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vlib xilinxcorelib_ver
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vmap xilinxcorelib_ver xilinxcorelib_ver
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vmap xilinxcorelib_ver xilinxcorelib_ver
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vlog -work xilinxcorelib_ver /opt/Xilinx/11.1/ISE/verilog/src/XilinxCoreLib/*.v
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vlog -work xilinxcorelib_ver /opt/Xilinx/11.1/ISE/verilog/src/XilinxCoreLib/*.v
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}
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}
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# Compile the glbl.v module
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# Compile the glbl.v module
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vlog /opt/Xilinx/11.1/ISE/verilog/src/glbl.v
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vlog /opt/Xilinx/11.1/ISE/verilog/src/glbl.v
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# Compile project source code
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# Compile project source code
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vlog ../../../rtl/verilog/versatile_mem_ctrl_ip.v +incdir+../../../rtl/verilog/
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vlog ../../../rtl/verilog/versatile_mem_ctrl_ip.v +incdir+../../../rtl/verilog/
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# Compile test bench source code
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# Compile test bench source code
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vlog ../../../bench/ddr/ddr2.v +incdir+../../../bench/ddr/
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vlog ../../../bench/ddr/ddr2.v +incdir+../../../bench/ddr/
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vlog ../../../bench/wb0_ddr.v ../../../bench/wb1_ddr.v ../../../bench/wb4_ddr.v +define+x16 ../../../bench/tb_top.v +incdir+../../../bench/
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vlog ../../../bench/wb0_ddr.v ../../../bench/wb1_ddr.v ../../../bench/wb4_ddr.v +define+x16 ../../../bench/tb_top.v +incdir+../../../bench/
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# Quit without asking
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# Quit without asking
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set PrefMain(forceQuit) 1
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set PrefMain(forceQuit) 1
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# Invoke the simulator
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# Invoke the simulator
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# -gui Open the GUI without loading a design
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# -gui Open the GUI without loading a design
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# -novopt Force incremental mode (pre-6.0 behavior)
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# -novopt Force incremental mode (pre-6.0 behavior)
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# -L Search library for design units instantiated from Verilog and for VHDL default component binding
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# -L Search library for design units instantiated from Verilog and for VHDL default component binding
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vsim -gui -novopt -L unisims_ver -L xilinxcorelib_ver work.versatile_mem_ctrl_tb work.glbl
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vsim -gui -novopt -L unisims_ver -L xilinxcorelib_ver work.versatile_mem_ctrl_tb work.glbl
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# Open waveform viewer
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# Open waveform viewer
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view wave -title "${DESIGN_NAME}"
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view wave -title "${DESIGN_NAME}"
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# Open signal viewer
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# Open signal viewer
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view signals
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view signals
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# Run the .do file to load signals to the waveform viewer
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# Run the .do file to load signals to the waveform viewer
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#do $WAVE_FILE
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do $WAVE_FILE
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# Run the simulation
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# Run the simulation
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run 330 us
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run 330 us
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