--
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--
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-- File tgen.vhd, Video Horizontal and Vertical Timing Generator
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-- File tgen.vhd, Video Horizontal and Vertical Timing Generator
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-- Project: VGA
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-- Project: VGA
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-- Author : Richard Herveille
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-- Author : Richard Herveille
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-- rev.: 0.1 April 13th, 2001
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-- rev.: 0.1 April 13th, 2001
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--
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--
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity Tgen is
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entity Tgen is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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-- horizontal timing settings
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-- horizontal timing settings
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HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg)
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HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg)
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Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels)
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Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels)
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Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels)
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Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels)
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Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line)
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Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line)
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Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line)
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Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line)
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-- vertical timing settings
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-- vertical timing settings
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VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg)
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VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg)
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Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines)
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Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines)
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Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines)
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Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines)
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Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame)
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Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame)
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Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame)
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Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame)
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CSyncL : in std_logic; -- composite sync pulse polarization level (pos/neg)
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CSyncL : in std_logic; -- composite sync pulse polarization level (pos/neg)
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BlankL : in std_logic; -- blank signals polarizatio level
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BlankL : in std_logic; -- blank signals polarizatio level
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eol, -- end of line
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eol, -- end of line
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eof, -- end of frame
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eof, -- end of frame
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gate, -- vertical AND horizontal gate (logical and function)
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gate, -- vertical AND horizontal gate (logical and function)
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Hsync, -- horizontal sync pulse
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Hsync, -- horizontal sync pulse
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Vsync, -- vertical sync pulse
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Vsync, -- vertical sync pulse
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Csync, -- composite sync
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Csync, -- composite sync
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Blank : out std_logic -- blank signal
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Blank : out std_logic -- blank signal
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);
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);
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end entity Tgen;
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end entity Tgen;
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architecture dataflow of Tgen is
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architecture dataflow of Tgen is
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--
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--
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-- Component declarations
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-- Component declarations
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--
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--
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component vtim is
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component vtim is
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port(
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port(
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clk : in std_logic; -- master clock
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clk : in std_logic; -- master clock
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ena : in std_logic := '1'; -- count enable
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ena : in std_logic := '1'; -- count enable
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rst : in std_logic; -- synchronous active high reset
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rst : in std_logic; -- synchronous active high reset
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Tsync : in unsigned(7 downto 0); -- sync duration
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Tsync : in unsigned(7 downto 0); -- sync duration
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Tgdel : in unsigned(7 downto 0); -- gate delay
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Tgdel : in unsigned(7 downto 0); -- gate delay
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Tgate : in unsigned(15 downto 0); -- gate length
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Tgate : in unsigned(15 downto 0); -- gate length
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Tlen : in unsigned(15 downto 0); -- line time / frame time
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Tlen : in unsigned(15 downto 0); -- line time / frame time
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Sync : out std_logic; -- synchronization pulse
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Sync : out std_logic; -- synchronization pulse
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Gate : out std_logic; -- gate
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Gate : out std_logic; -- gate
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Done : out std_logic -- done with line/frame
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Done : out std_logic -- done with line/frame
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);
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);
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end component vtim;
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end component vtim;
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--
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--
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-- signals
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-- signals
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--
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--
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signal Hgate, Vgate : std_logic;
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signal Hgate, Vgate : std_logic;
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signal Hdone : std_logic;
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signal Hdone : std_logic;
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signal iHsync, iVsync, igate : std_logic;
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signal iHsync, iVsync, igate : std_logic;
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begin
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begin
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-- hookup horizontal timing generator
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-- hookup horizontal timing generator
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hor_gen: vtim port map (clk => clk, rst => rst,
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hor_gen: vtim port map (clk => clk, rst => rst,
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Tsync => Thsync, Tgdel => Thgdel, Tgate => Thgate, Tlen => Thlen,
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Tsync => Thsync, Tgdel => Thgdel, Tgate => Thgate, Tlen => Thlen,
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Sync => iHsync, Gate => Hgate, Done => Hdone);
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Sync => iHsync, Gate => Hgate, Done => Hdone);
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-- hookup vertical timing generator
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-- hookup vertical timing generator
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ver_gen: vtim port map (clk => clk, ena => Hdone, rst => rst,
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ver_gen: vtim port map (clk => clk, ena => Hdone, rst => rst,
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Tsync => Tvsync, Tgdel => Tvgdel, Tgate => Tvgate, Tlen => Tvlen,
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Tsync => Tvsync, Tgdel => Tvgdel, Tgate => Tvgate, Tlen => Tvlen,
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Sync => iVsync, Gate => Vgate, Done => eof);
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Sync => iVsync, Gate => Vgate, Done => eof);
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-- assign outputs
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-- assign outputs
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eol <= Hdone;
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eol <= Hdone;
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igate <= Hgate and Vgate;
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igate <= Hgate and Vgate;
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gate <= igate;
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gate <= igate;
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Hsync <= iHsync xor HsyncL;
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Hsync <= iHsync xor HsyncL;
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Vsync <= iVsync xor VsyncL;
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Vsync <= iVsync xor VsyncL;
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Csync <= (iHsync or iVsync) xor CsyncL;
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Csync <= (iHsync or iVsync) xor CsyncL;
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Blank <= igate xnor BlankL;
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Blank <= igate xnor BlankL;
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end architecture dataflow;
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end architecture dataflow;
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