library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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entity eDither is
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entity eDither is
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generic
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generic
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(
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(
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img_width : integer := 512;
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img_width : integer := 512;
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img_height : integer := 512;
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img_height : integer := 512;
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color_width : integer := 8;
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color_width : integer := 8;
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reduced_width : integer := 4
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reduced_width : integer := 4
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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x : in integer range 0 to img_width-1;
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x : in integer range 0 to img_width-1;
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din_r : in std_logic_vector(color_width-1 downto 0);
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din_r : in std_logic_vector(color_width-1 downto 0);
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din_g : in std_logic_vector(color_width-1 downto 0);
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din_g : in std_logic_vector(color_width-1 downto 0);
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din_b : in std_logic_vector(color_width-1 downto 0);
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din_b : in std_logic_vector(color_width-1 downto 0);
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dout_r : out std_logic_vector(color_width-1 downto 0) := (others => '0');
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dout_r : out std_logic_vector(color_width-1 downto 0) := (others => '0');
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dout_g : out std_logic_vector(color_width-1 downto 0) := (others => '0');
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dout_g : out std_logic_vector(color_width-1 downto 0) := (others => '0');
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dout_b : out std_logic_vector(color_width-1 downto 0) := (others => '0')
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dout_b : out std_logic_vector(color_width-1 downto 0) := (others => '0')
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);
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);
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end entity;
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end entity;
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architecture arch of eDither is
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architecture arch of eDither is
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constant dither_bits : integer := color_width - reduced_width;
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constant dither_bits : integer := color_width - reduced_width;
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-- intermediate signals for caclulation
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-- intermediate signals for caclulation
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type t_dither_rgb is array(1 to 3) of unsigned(dither_bits-1 downto 0);
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type t_dither_rgb is array(1 to 3) of unsigned(dither_bits-1 downto 0);
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signal dither_buffer_next : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_next : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_newline : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_newline : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_toRam : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_toRam : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_fromRam : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_fromRam : t_dither_rgb := (others => (others =>'0'));
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-- infered ram for holding old pixel information
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-- infered ram for holding old pixel information
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type t_dither_buffer is array(0 to img_width-1) of unsigned((dither_bits * 3)-1 downto 0);
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type t_dither_buffer is array(0 to img_width-1) of unsigned((dither_bits * 3)-1 downto 0);
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signal dither_buffer : t_dither_buffer := (others => (others => '0'));
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signal dither_buffer : t_dither_buffer := (others => (others => '0'));
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signal index : integer range 0 to img_width-1 := 0;
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signal index : integer range 0 to img_width-1 := 0;
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signal AddrA : integer range 0 to img_width-1 := 0;
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signal AddrA : integer range 0 to img_width-1 := 0;
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signal AddrB : integer range 0 to img_width-1 := 0;
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signal AddrB : integer range 0 to img_width-1 := 0;
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signal WEA : std_logic := '0';
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signal WEA : std_logic := '0';
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begin
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begin
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process (clk)
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process (clk)
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type t_intermediate is array(1 to 3) of unsigned(color_width downto 0);
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type t_intermediate is array(1 to 3) of unsigned(color_width downto 0);
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variable intermediate_color : t_intermediate;
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variable intermediate_color : t_intermediate;
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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-- calculate dithered colors
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-- calculate dithered colors
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if (enable = '1') then
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if (enable = '1') then
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intermediate_color(1) := ("0" & unsigned(din_r)) + dither_buffer_next(1) + unsigned(dither_buffer_fromRam(1));
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intermediate_color(1) := ("0" & unsigned(din_r)) + dither_buffer_next(1) + unsigned(dither_buffer_fromRam(1));
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intermediate_color(2) := ("0" & unsigned(din_g)) + dither_buffer_next(2) + unsigned(dither_buffer_fromRam(2));
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intermediate_color(2) := ("0" & unsigned(din_g)) + dither_buffer_next(2) + unsigned(dither_buffer_fromRam(2));
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intermediate_color(3) := ("0" & unsigned(din_b)) + dither_buffer_next(3) + unsigned(dither_buffer_fromRam(2));
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intermediate_color(3) := ("0" & unsigned(din_b)) + dither_buffer_next(3) + unsigned(dither_buffer_fromRam(3));
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for c in 1 to 3 loop
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for c in 1 to 3 loop
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if (intermediate_color(c)(8) = '1') then intermediate_color(c) := '0' & to_unsigned((2**color_width) - 1, color_width); end if;
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if (intermediate_color(c)(8) = '1') then intermediate_color(c) := '0' & to_unsigned((2**color_width) - 1, color_width); end if;
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dither_buffer_next(c) <= "0" & intermediate_color(c)(dither_bits-1 downto 1);
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dither_buffer_next(c) <= "0" & intermediate_color(c)(dither_bits-1 downto 1);
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dither_buffer_newline(c) <= "00" & intermediate_color(c)(dither_bits-1 downto 2);
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dither_buffer_newline(c) <= "00" & intermediate_color(c)(dither_bits-1 downto 2);
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dither_buffer_toRam(c) <= ("00" & intermediate_color(c)(dither_bits-1 downto 2)) + dither_buffer_newline(c);
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dither_buffer_toRam(c) <= ("00" & intermediate_color(c)(dither_bits-1 downto 2)) + dither_buffer_newline(c);
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end loop;
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end loop;
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else
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else
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intermediate_color(1) := "0" & unsigned(din_r);
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intermediate_color(1) := "0" & unsigned(din_r);
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intermediate_color(2) := "0" & unsigned(din_g);
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intermediate_color(2) := "0" & unsigned(din_g);
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intermediate_color(3) := "0" & unsigned(din_b);
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intermediate_color(3) := "0" & unsigned(din_b);
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end if;
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end if;
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-- calculate address for line buffer + enable
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-- calculate address for line buffer + enable
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if (x<img_width-2) then
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if (x<img_width-2) then
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AddrB <= x+2;
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AddrB <= x+2;
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elsif (x=img_width-2) then
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elsif (x=img_width-2) then
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AddrB <= 0;
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AddrB <= 0;
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else
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else
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AddrB <= 1;
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AddrB <= 1;
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end if;
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end if;
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index <= x;
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index <= x;
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AddrA <= index;
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AddrA <= index;
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if (enable = '1') then
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if (enable = '1') then
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WEA <= '1';
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WEA <= '1';
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else
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else
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WEA <= '0';
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WEA <= '0';
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end if;
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end if;
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-- line buffer memory
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-- line buffer memory
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if (WEA = '1') then
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if (WEA = '1') then
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dither_buffer(AddrA) <= dither_buffer_toRam(1) & dither_buffer_toRam(2) & dither_buffer_toRam(3);
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dither_buffer(AddrA) <= dither_buffer_toRam(1) & dither_buffer_toRam(2) & dither_buffer_toRam(3);
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end if;
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end if;
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dither_buffer_fromRam(1) <= dither_buffer(AddrB)((dither_bits * 3)-1 downto (dither_bits * 2));
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dither_buffer_fromRam(1) <= dither_buffer(AddrB)((dither_bits * 3)-1 downto (dither_bits * 2));
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dither_buffer_fromRam(2) <= dither_buffer(AddrB)((dither_bits * 2)-1 downto dither_bits);
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dither_buffer_fromRam(2) <= dither_buffer(AddrB)((dither_bits * 2)-1 downto dither_bits);
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dither_buffer_fromRam(3) <= dither_buffer(AddrB)(dither_bits-1 downto 0);
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dither_buffer_fromRam(3) <= dither_buffer(AddrB)(dither_bits-1 downto 0);
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-- map outputs
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-- map outputs
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dout_r <= std_logic_vector(intermediate_color(1)(color_width-1 downto 0));
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dout_r <= std_logic_vector(intermediate_color(1)(color_width-1 downto 0));
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dout_g <= std_logic_vector(intermediate_color(2)(color_width-1 downto 0));
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dout_g <= std_logic_vector(intermediate_color(2)(color_width-1 downto 0));
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dout_b <= std_logic_vector(intermediate_color(3)(color_width-1 downto 0));
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dout_b <= std_logic_vector(intermediate_color(3)(color_width-1 downto 0));
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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