--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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--! @brief Add-compare-select unit for trellis processing.
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--! @brief Add-compare-select unit for trellis processing.
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--! @author Markus Fehrenz
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--! @author Markus Fehrenz
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--! @date 2011/07/04
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--! @date 2011/07/04
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--!
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--!
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--! @details The ACS decides which path is the the surviving trellis path.
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--! @details The ACS decides which path is the the surviving trellis path.
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--! In the design there are 2^{K-1} ACS instances.
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--! In the design there are 2^{K-1} ACS instances.
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--!
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--!
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library dec_viterbi;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_helper.all;
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use dec_viterbi.pkg_helper.all;
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entity acs is
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entity acs is
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generic(
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generic(
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-- Reset value
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-- Reset value
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INITIALIZE_VALUE : in signed(BW_MAX_PROBABILITY - 1 downto 0)
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INITIALIZE_VALUE : in signed(BW_MAX_PROBABILITY - 1 downto 0)
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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--
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--
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-- Values from branch distance, signed values in std_logic_vector
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-- Values from branch distance, signed values in std_logic_vector
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-- high is located in the upper half.
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-- high is located in the upper half.
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--
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--
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s_axis_inbranch_tvalid : in std_logic;
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s_axis_inbranch_tvalid : in std_logic;
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s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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s_axis_inbranch_tlast : in std_logic;
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s_axis_inbranch_tlast : in std_logic;
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s_axis_inbranch_tready : out std_logic;
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s_axis_inbranch_tready : out std_logic;
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--
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--
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-- Probabilities from previous nodes, signed values in std_logic_vector
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-- Probabilities from previous nodes, signed values in std_logic_vector
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-- high is located in the upper half.
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-- high is located in the upper half.
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--
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--
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s_axis_inprev_tvalid : in std_logic;
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s_axis_inprev_tvalid : in std_logic;
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s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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s_axis_inprev_tready : out std_logic;
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s_axis_inprev_tready : out std_logic;
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-- probability result of the add compare and select
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-- probability result of the add compare and select
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m_axis_outprob_tvalid : out std_logic;
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m_axis_outprob_tvalid : out std_logic;
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m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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m_axis_outprob_tready : in std_logic;
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m_axis_outprob_tready : in std_logic;
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-- decision result of the add compare and select
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-- decision result of the add compare and select
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m_axis_outdec_tvalid : out std_logic;
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m_axis_outdec_tvalid : out std_logic;
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m_axis_outdec_tdata : out std_logic;
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m_axis_outdec_tdata : out std_logic;
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m_axis_outdec_tlast : out std_logic;
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m_axis_outdec_tlast : out std_logic;
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m_axis_outdec_tready : in std_logic
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m_axis_outdec_tready : in std_logic
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);
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);
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end entity acs;
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end entity acs;
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architecture rtl of acs is
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architecture rtl of acs is
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signal s_axis_inbranch_tlast_d : std_logic;
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signal s_axis_inbranch_tlast_d : std_logic;
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signal m_axis_outdec_tvalid_int : std_logic;
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signal m_axis_outdec_tvalid_int : std_logic;
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signal s_axis_inbranch_tready_int : std_logic;
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signal s_axis_inbranch_tready_int : std_logic;
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begin
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begin
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s_axis_inbranch_tready_int <= '1' when m_axis_outdec_tready = '1' or m_axis_outdec_tvalid_int = '0' else
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s_axis_inbranch_tready_int <= '1' when m_axis_outdec_tready = '1' or m_axis_outdec_tvalid_int = '0' else
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'0';
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'0';
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s_axis_inbranch_tready <= s_axis_inbranch_tready_int;
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s_axis_inbranch_tready <= s_axis_inbranch_tready_int;
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m_axis_outdec_tvalid <= m_axis_outdec_tvalid_int;
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m_axis_outdec_tvalid <= m_axis_outdec_tvalid_int;
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-- Add branch to previous, compare both paths and select survivor.
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-- Add branch to previous, compare both paths and select survivor.
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pr_add_compare : process(clk) is
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pr_add_compare : process(clk) is
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variable v_diff, v_high, v_low : signed(BW_MAX_PROBABILITY - 1 downto 0);
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variable v_diff, v_high, v_low : signed(BW_MAX_PROBABILITY - 1 downto 0);
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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m_axis_outdec_tvalid_int <= '0';
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m_axis_outdec_tvalid_int <= '0';
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m_axis_outdec_tdata <= '0';
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m_axis_outdec_tdata <= '0';
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m_axis_outdec_tlast <= '0';
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m_axis_outdec_tlast <= '0';
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m_axis_outprob_tvalid <= '0';
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s_axis_inprev_tready <= '0';
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s_axis_inprev_tready <= '0';
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s_axis_inbranch_tlast_d <= '0';
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s_axis_inbranch_tlast_d <= '0';
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m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
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m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
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else
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else
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-- If this is the last value, prepare for processing of next incoming value.
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-- If this is the last value, prepare for processing of next incoming value.
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if s_axis_inbranch_tlast_d = '1' then
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if s_axis_inbranch_tlast_d = '1' then
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m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
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m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
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s_axis_inbranch_tlast_d <= '0';
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s_axis_inbranch_tlast_d <= '0';
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m_axis_outdec_tvalid_int <= '0';
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m_axis_outdec_tvalid_int <= '0';
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end if;
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end if;
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if m_axis_outdec_tvalid_int = '1' and m_axis_outdec_tready = '1' then
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m_axis_outdec_tvalid_int <= '0';
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end if;
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-- Process only if we receive valid data.
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-- Process only if we receive valid data.
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if s_axis_inbranch_tvalid = '1' and s_axis_inbranch_tready_int = '1' then
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if s_axis_inbranch_tvalid = '1' and s_axis_inbranch_tready_int = '1' then
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s_axis_inbranch_tlast_d <= s_axis_inbranch_tlast;
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s_axis_inbranch_tlast_d <= s_axis_inbranch_tlast;
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-- Add.
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-- Add.
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v_low := signed(s_axis_inbranch_tdata_low) + signed(s_axis_inprev_tdata_low);
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v_low := signed(s_axis_inbranch_tdata_low) + signed(s_axis_inprev_tdata_low);
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v_high := signed(s_axis_inbranch_tdata_high) + signed(s_axis_inprev_tdata_high);
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v_high := signed(s_axis_inbranch_tdata_high) + signed(s_axis_inprev_tdata_high);
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-- Use modulo normalization, do not extend the sign here!
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-- Use modulo normalization, do not extend the sign here!
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v_diff := v_low - v_high;
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v_diff := v_low - v_high;
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-- Compare, select the correct path.
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-- Compare, select the correct path.
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if v_diff < 0 then
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if v_diff < 0 then
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m_axis_outdec_tdata <= '1';
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m_axis_outdec_tdata <= '1';
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m_axis_outprob_tdata <= std_logic_vector(v_high);
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m_axis_outprob_tdata <= std_logic_vector(v_high);
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else
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else
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m_axis_outdec_tdata <= '0';
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m_axis_outdec_tdata <= '0';
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m_axis_outprob_tdata <= std_logic_vector(v_low);
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m_axis_outprob_tdata <= std_logic_vector(v_low);
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end if;
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end if;
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m_axis_outdec_tvalid_int <= s_axis_inbranch_tvalid;
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m_axis_outdec_tvalid_int <= '1';
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end if;
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end if;
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m_axis_outdec_tlast <= s_axis_inbranch_tlast;
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m_axis_outdec_tlast <= s_axis_inbranch_tlast;
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end if;
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end if;
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end if;
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end if;
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end process pr_add_compare;
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end process pr_add_compare;
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end architecture rtl;
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end architecture rtl;
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