-- $Id: gen_crc8_tbl_check.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: gen_crc8_tbl_check.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: gen_crc8_tbl - sim
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-- Module Name: gen_crc8_tbl - sim
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-- Description: stand-alone program to test crc8 transition table
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-- Description: stand-alone program to test crc8 transition table
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-07-08 65 1.0 Initial version
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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--use work.slvtypes.all;
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--use work.slvtypes.all;
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--use work.comlib.all;
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--use work.comlib.all;
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entity gen_crc8_tbl_check is
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entity gen_crc8_tbl_check is
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end gen_crc8_tbl_check;
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end gen_crc8_tbl_check;
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architecture sim of gen_crc8_tbl_check is
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architecture sim of gen_crc8_tbl_check is
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begin
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begin
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process
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process
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type crc8_tbl_type is array (0 to 255) of integer;
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type crc8_tbl_type is array (0 to 255) of integer;
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variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
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variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
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( 0, 29, 58, 39, 116, 105, 78, 83,
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( 0, 29, 58, 39, 116, 105, 78, 83,
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232, 245, 210, 207, 156, 129, 166, 187,
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232, 245, 210, 207, 156, 129, 166, 187,
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205, 208, 247, 234, 185, 164, 131, 158,
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205, 208, 247, 234, 185, 164, 131, 158,
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37, 56, 31, 2, 81, 76, 107, 118,
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37, 56, 31, 2, 81, 76, 107, 118,
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135, 154, 189, 160, 243, 238, 201, 212,
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135, 154, 189, 160, 243, 238, 201, 212,
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111, 114, 85, 72, 27, 6, 33, 60,
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111, 114, 85, 72, 27, 6, 33, 60,
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74, 87, 112, 109, 62, 35, 4, 25,
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74, 87, 112, 109, 62, 35, 4, 25,
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162, 191, 152, 133, 214, 203, 236, 241,
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162, 191, 152, 133, 214, 203, 236, 241,
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19, 14, 41, 52, 103, 122, 93, 64,
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19, 14, 41, 52, 103, 122, 93, 64,
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251, 230, 193, 220, 143, 146, 181, 168,
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251, 230, 193, 220, 143, 146, 181, 168,
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222, 195, 228, 249, 170, 183, 144, 141,
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222, 195, 228, 249, 170, 183, 144, 141,
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54, 43, 12, 17, 66, 95, 120, 101,
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54, 43, 12, 17, 66, 95, 120, 101,
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148, 137, 174, 179, 224, 253, 218, 199,
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148, 137, 174, 179, 224, 253, 218, 199,
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124, 97, 70, 91, 8, 21, 50, 47,
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124, 97, 70, 91, 8, 21, 50, 47,
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89, 68, 99, 126, 45, 48, 23, 10,
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89, 68, 99, 126, 45, 48, 23, 10,
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177, 172, 139, 150, 197, 216, 255, 226,
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177, 172, 139, 150, 197, 216, 255, 226,
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38, 59, 28, 1, 82, 79, 104, 117,
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38, 59, 28, 1, 82, 79, 104, 117,
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206, 211, 244, 233, 186, 167, 128, 157,
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206, 211, 244, 233, 186, 167, 128, 157,
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235, 246, 209, 204, 159, 130, 165, 184,
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235, 246, 209, 204, 159, 130, 165, 184,
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3, 30, 57, 36, 119, 106, 77, 80,
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3, 30, 57, 36, 119, 106, 77, 80,
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161, 188, 155, 134, 213, 200, 239, 242,
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161, 188, 155, 134, 213, 200, 239, 242,
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73, 84, 115, 110, 61, 32, 7, 26,
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73, 84, 115, 110, 61, 32, 7, 26,
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108, 113, 86, 75, 24, 5, 34, 63,
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108, 113, 86, 75, 24, 5, 34, 63,
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132, 153, 190, 163, 240, 237, 202, 215,
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132, 153, 190, 163, 240, 237, 202, 215,
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53, 40, 15, 18, 65, 92, 123, 102,
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53, 40, 15, 18, 65, 92, 123, 102,
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221, 192, 231, 250, 169, 180, 147, 142,
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221, 192, 231, 250, 169, 180, 147, 142,
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248, 229, 194, 223, 140, 145, 182, 171,
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248, 229, 194, 223, 140, 145, 182, 171,
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16, 13, 42, 55, 100, 121, 94, 67,
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16, 13, 42, 55, 100, 121, 94, 67,
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178, 175, 136, 149, 198, 219, 252, 225,
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178, 175, 136, 149, 198, 219, 252, 225,
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90, 71, 96, 125, 46, 51, 20, 9,
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90, 71, 96, 125, 46, 51, 20, 9,
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127, 98, 69, 88, 11, 22, 49, 44,
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127, 98, 69, 88, 11, 22, 49, 44,
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151, 138, 173, 176, 227, 254, 217, 196
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151, 138, 173, 176, 227, 254, 217, 196
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);
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);
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variable crc : integer := 0;
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variable crc : integer := 0;
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variable oline : line;
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variable oline : line;
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begin
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begin
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loop_i: for i in 0 to 255 loop
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loop_i: for i in 0 to 255 loop
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write(oline, i, right, 4);
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write(oline, i, right, 4);
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write(oline, string'(": cycle length = "));
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write(oline, string'(": cycle length = "));
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crc := i;
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crc := i;
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loop_n: for n in 1 to 256 loop
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loop_n: for n in 1 to 256 loop
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crc := crc8_tbl(crc);
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crc := crc8_tbl(crc);
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if crc = i then
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if crc = i then
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write(oline, n, right, 4);
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write(oline, n, right, 4);
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writeline(output, oline);
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writeline(output, oline);
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exit loop_n;
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exit loop_n;
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end if;
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end if;
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end loop; -- n
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end loop; -- n
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end loop; -- i
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end loop; -- i
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wait;
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wait;
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end process;
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end process;
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end sim;
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end sim;
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