-- $Id: pdp11_mmu.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: pdp11_mmu.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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--
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-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: pdp11_mmu - syn
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-- Module Name: pdp11_mmu - syn
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-- Description: pdp11: mmu - memory management unit
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-- Description: pdp11: mmu - memory management unit
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--
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--
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-- Dependencies: pdp11_mmu_sadr
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-- Dependencies: pdp11_mmu_sadr
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-- pdp11_mmu_ssr12
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-- pdp11_mmu_ssr12
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-- ibus/ib_sres_or_3
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-- ibus/ib_sres_or_3
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--
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--
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
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-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
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-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
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-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
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-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
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-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
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-- BUGFIX: set ssr0 trap_mmu even when traps disabled
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-- BUGFIX: set ssr0 trap_mmu even when traps disabled
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-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
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-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
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-- 2008-04-27 139 1.3.3 allow ssr1/2 tracing even with mmu_ena=0
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-- 2008-04-27 139 1.3.3 allow ssr1/2 tracing even with mmu_ena=0
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-- 2008-04-25 138 1.3.2 add BRESET port, clear ssr0/3 with BRESET
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-- 2008-04-25 138 1.3.2 add BRESET port, clear ssr0/3 with BRESET
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-- 2008-03-02 121 1.3.1 remove snoopers
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-- 2008-03-02 121 1.3.1 remove snoopers
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-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
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-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
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-- cpacc handling; PADDR generation now on _vmbox
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-- cpacc handling; PADDR generation now on _vmbox
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-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
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-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
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-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
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-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
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-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
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-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
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-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
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-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.iblib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity pdp11_mmu is -- mmu - memory management unit
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entity pdp11_mmu is -- mmu - memory management unit
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CRESET : in slbit; -- console reset
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CRESET : in slbit; -- console reset
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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CNTL : in mmu_cntl_type; -- control port
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CNTL : in mmu_cntl_type; -- control port
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VADDR : in slv16; -- virtual address
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VADDR : in slv16; -- virtual address
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MONI : in mmu_moni_type; -- monitor port
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MONI : in mmu_moni_type; -- monitor port
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STAT : out mmu_stat_type; -- status port
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STAT : out mmu_stat_type; -- status port
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PADDRH : out slv16; -- physical address (upper 16 bit)
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PADDRH : out slv16; -- physical address (upper 16 bit)
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IB_MREQ: in ib_mreq_type; -- ibus request
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IB_MREQ: in ib_mreq_type; -- ibus request
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IB_SRES: out ib_sres_type -- ibus response
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IB_SRES: out ib_sres_type -- ibus response
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);
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);
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end pdp11_mmu;
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end pdp11_mmu;
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architecture syn of pdp11_mmu is
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architecture syn of pdp11_mmu is
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constant ibaddr_ssr0 : slv16 := conv_std_logic_vector(8#177572#,16);
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constant ibaddr_ssr0 : slv16 := conv_std_logic_vector(8#177572#,16);
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constant ibaddr_ssr3 : slv16 := conv_std_logic_vector(8#172516#,16);
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constant ibaddr_ssr3 : slv16 := conv_std_logic_vector(8#172516#,16);
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constant ssr0_ibf_abo_nonres : integer := 15;
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constant ssr0_ibf_abo_nonres : integer := 15;
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constant ssr0_ibf_abo_length : integer := 14;
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constant ssr0_ibf_abo_length : integer := 14;
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constant ssr0_ibf_abo_rdonly : integer := 13;
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constant ssr0_ibf_abo_rdonly : integer := 13;
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constant ssr0_ibf_trap_mmu : integer := 12;
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constant ssr0_ibf_trap_mmu : integer := 12;
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constant ssr0_ibf_ena_trap : integer := 9;
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constant ssr0_ibf_ena_trap : integer := 9;
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constant ssr0_ibf_inst_compl : integer := 7;
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constant ssr0_ibf_inst_compl : integer := 7;
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subtype ssr0_ibf_seg_mode is integer range 6 downto 5;
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subtype ssr0_ibf_seg_mode is integer range 6 downto 5;
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constant ssr0_ibf_dspace : integer := 4;
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constant ssr0_ibf_dspace : integer := 4;
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subtype ssr0_ibf_seg_num is integer range 3 downto 1;
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subtype ssr0_ibf_seg_num is integer range 3 downto 1;
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constant ssr0_ibf_ena_mmu : integer := 0;
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constant ssr0_ibf_ena_mmu : integer := 0;
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constant ssr3_ibf_ena_ubmap : integer := 5;
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constant ssr3_ibf_ena_ubmap : integer := 5;
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constant ssr3_ibf_ena_22bit : integer := 4;
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constant ssr3_ibf_ena_22bit : integer := 4;
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constant ssr3_ibf_dspace_km : integer := 2;
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constant ssr3_ibf_dspace_km : integer := 2;
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constant ssr3_ibf_dspace_sm : integer := 1;
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constant ssr3_ibf_dspace_sm : integer := 1;
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constant ssr3_ibf_dspace_um : integer := 0;
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constant ssr3_ibf_dspace_um : integer := 0;
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signal IBSEL_SSR0 : slbit := '0'; -- ibus select SSR0
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signal IBSEL_SSR0 : slbit := '0'; -- ibus select SSR0
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signal IBSEL_SSR3 : slbit := '0'; -- ibus select SSR3
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signal IBSEL_SSR3 : slbit := '0'; -- ibus select SSR3
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signal R_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
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signal R_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
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signal N_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
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signal N_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
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signal R_SSR3 : mmu_ssr3_type := mmu_ssr3_init;
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signal R_SSR3 : mmu_ssr3_type := mmu_ssr3_init;
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signal ASN : slv4 := "0000"; -- augmented segment number (1+3 bit)
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signal ASN : slv4 := "0000"; -- augmented segment number (1+3 bit)
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signal AIB_WE : slbit := '0'; -- update AIB
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signal AIB_WE : slbit := '0'; -- update AIB
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signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
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signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
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signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
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signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
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signal TRACE : slbit := '0'; -- enable tracing in ssr1/2
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signal TRACE : slbit := '0'; -- enable tracing in ssr1/2
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signal DSPACE : slbit := '0'; -- use dspace
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signal DSPACE : slbit := '0'; -- use dspace
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signal IB_SRES_SADR : ib_sres_type := ib_sres_init;
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signal IB_SRES_SADR : ib_sres_type := ib_sres_init;
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signal IB_SRES_SSR12 : ib_sres_type := ib_sres_init;
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signal IB_SRES_SSR12 : ib_sres_type := ib_sres_init;
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signal IB_SRES_SSR03 : ib_sres_type := ib_sres_init;
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signal IB_SRES_SSR03 : ib_sres_type := ib_sres_init;
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signal SARSDR : sarsdr_type := sarsdr_init;
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signal SARSDR : sarsdr_type := sarsdr_init;
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begin
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begin
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SADR : pdp11_mmu_sadr port map (
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SADR : pdp11_mmu_sadr port map (
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CLK => CLK,
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CLK => CLK,
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MODE => CNTL.mode,
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MODE => CNTL.mode,
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ASN => ASN,
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ASN => ASN,
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AIB_WE => AIB_WE,
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AIB_WE => AIB_WE,
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AIB_SETA => AIB_SETA,
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AIB_SETA => AIB_SETA,
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AIB_SETW => AIB_SETW,
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AIB_SETW => AIB_SETW,
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SARSDR => SARSDR,
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SARSDR => SARSDR,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_SADR);
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IB_SRES => IB_SRES_SADR);
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SSR12 : pdp11_mmu_ssr12 port map (
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SSR12 : pdp11_mmu_ssr12 port map (
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CLK => CLK,
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CLK => CLK,
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CRESET => CRESET,
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CRESET => CRESET,
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TRACE => TRACE,
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TRACE => TRACE,
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MONI => MONI,
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MONI => MONI,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_SSR12);
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IB_SRES => IB_SRES_SSR12);
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IB_SRES_OR : ib_sres_or_3
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IB_SRES_OR : ib_sres_or_3
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port map (
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port map (
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IB_SRES_1 => IB_SRES_SADR,
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IB_SRES_1 => IB_SRES_SADR,
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IB_SRES_2 => IB_SRES_SSR12,
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IB_SRES_2 => IB_SRES_SSR12,
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IB_SRES_3 => IB_SRES_SSR03,
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IB_SRES_3 => IB_SRES_SSR03,
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IB_SRES_OR => IB_SRES);
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IB_SRES_OR => IB_SRES);
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proc_ibsel: process (IB_MREQ)
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proc_ibsel: process (IB_MREQ)
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variable issr0 : slbit := '0';
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variable issr0 : slbit := '0';
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variable issr3 : slbit := '0';
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variable issr3 : slbit := '0';
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begin
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begin
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issr0 := '0';
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issr0 := '0';
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issr3 := '0';
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issr3 := '0';
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if IB_MREQ.req = '1' then
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if IB_MREQ.req = '1' then
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if IB_MREQ.addr = ibaddr_ssr0(12 downto 1) then issr0 := '1'; end if;
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if IB_MREQ.addr = ibaddr_ssr0(12 downto 1) then issr0 := '1'; end if;
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if IB_MREQ.addr = ibaddr_ssr3(12 downto 1) then issr3 := '1'; end if;
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if IB_MREQ.addr = ibaddr_ssr3(12 downto 1) then issr3 := '1'; end if;
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end if;
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end if;
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IBSEL_SSR0 <= issr0;
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IBSEL_SSR0 <= issr0;
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IBSEL_SSR3 <= issr3;
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IBSEL_SSR3 <= issr3;
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IB_SRES_SSR03.ack <= issr0 or issr3;
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IB_SRES_SSR03.ack <= issr0 or issr3;
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IB_SRES_SSR03.busy <= '0';
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IB_SRES_SSR03.busy <= '0';
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end process proc_ibsel;
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end process proc_ibsel;
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proc_ibdout : process (IBSEL_SSR0, IBSEL_SSR3, R_SSR0, R_SSR3)
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proc_ibdout : process (IBSEL_SSR0, IBSEL_SSR3, R_SSR0, R_SSR3)
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variable ssr0out : slv16 := (others=>'0');
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variable ssr0out : slv16 := (others=>'0');
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variable ssr3out : slv16 := (others=>'0');
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variable ssr3out : slv16 := (others=>'0');
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begin
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begin
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ssr0out := (others=>'0');
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ssr0out := (others=>'0');
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if IBSEL_SSR0 = '1' then
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if IBSEL_SSR0 = '1' then
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ssr0out(ssr0_ibf_abo_nonres) := R_SSR0.abo_nonres;
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ssr0out(ssr0_ibf_abo_nonres) := R_SSR0.abo_nonres;
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ssr0out(ssr0_ibf_abo_length) := R_SSR0.abo_length;
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ssr0out(ssr0_ibf_abo_length) := R_SSR0.abo_length;
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ssr0out(ssr0_ibf_abo_rdonly) := R_SSR0.abo_rdonly;
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ssr0out(ssr0_ibf_abo_rdonly) := R_SSR0.abo_rdonly;
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ssr0out(ssr0_ibf_trap_mmu) := R_SSR0.trap_mmu;
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ssr0out(ssr0_ibf_trap_mmu) := R_SSR0.trap_mmu;
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ssr0out(ssr0_ibf_ena_trap) := R_SSR0.ena_trap;
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ssr0out(ssr0_ibf_ena_trap) := R_SSR0.ena_trap;
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ssr0out(ssr0_ibf_inst_compl) := R_SSR0.inst_compl;
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ssr0out(ssr0_ibf_inst_compl) := R_SSR0.inst_compl;
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ssr0out(ssr0_ibf_seg_mode) := R_SSR0.seg_mode;
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ssr0out(ssr0_ibf_seg_mode) := R_SSR0.seg_mode;
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ssr0out(ssr0_ibf_dspace) := R_SSR0.dspace;
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ssr0out(ssr0_ibf_dspace) := R_SSR0.dspace;
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ssr0out(ssr0_ibf_seg_num) := R_SSR0.seg_num;
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ssr0out(ssr0_ibf_seg_num) := R_SSR0.seg_num;
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ssr0out(ssr0_ibf_ena_mmu) := R_SSR0.ena_mmu;
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ssr0out(ssr0_ibf_ena_mmu) := R_SSR0.ena_mmu;
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end if;
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end if;
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ssr3out := (others=>'0');
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ssr3out := (others=>'0');
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if IBSEL_SSR3 = '1' then
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if IBSEL_SSR3 = '1' then
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ssr3out(ssr3_ibf_ena_ubmap) := R_SSR3.ena_ubmap;
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ssr3out(ssr3_ibf_ena_ubmap) := R_SSR3.ena_ubmap;
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ssr3out(ssr3_ibf_ena_22bit) := R_SSR3.ena_22bit;
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ssr3out(ssr3_ibf_ena_22bit) := R_SSR3.ena_22bit;
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ssr3out(ssr3_ibf_dspace_km) := R_SSR3.dspace_km;
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ssr3out(ssr3_ibf_dspace_km) := R_SSR3.dspace_km;
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ssr3out(ssr3_ibf_dspace_sm) := R_SSR3.dspace_sm;
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ssr3out(ssr3_ibf_dspace_sm) := R_SSR3.dspace_sm;
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ssr3out(ssr3_ibf_dspace_um) := R_SSR3.dspace_um;
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ssr3out(ssr3_ibf_dspace_um) := R_SSR3.dspace_um;
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end if;
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end if;
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IB_SRES_SSR03.dout <= ssr0out or ssr3out;
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IB_SRES_SSR03.dout <= ssr0out or ssr3out;
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end process proc_ibdout;
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end process proc_ibdout;
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proc_ssr0 : process (CLK)
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proc_ssr0 : process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if CLK'event and CLK='1' then
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if BRESET = '1' then
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if BRESET = '1' then
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R_SSR0 <= mmu_ssr0_init;
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R_SSR0 <= mmu_ssr0_init;
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else
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else
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R_SSR0 <= N_SSR0;
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R_SSR0 <= N_SSR0;
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end if;
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end if;
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end if;
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end if;
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end process proc_ssr0;
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end process proc_ssr0;
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proc_ssr3 : process (CLK)
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proc_ssr3 : process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if CLK'event and CLK='1' then
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if BRESET = '1' then
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if BRESET = '1' then
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R_SSR3 <= mmu_ssr3_init;
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R_SSR3 <= mmu_ssr3_init;
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elsif IB_MREQ.we='1' and IBSEL_SSR3='1' then
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elsif IB_MREQ.we='1' and IBSEL_SSR3='1' then
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if IB_MREQ.be0 = '1' then
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if IB_MREQ.be0 = '1' then
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R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap);
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R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap);
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R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit);
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R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit);
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R_SSR3.dspace_km <= IB_MREQ.din(ssr3_ibf_dspace_km);
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R_SSR3.dspace_km <= IB_MREQ.din(ssr3_ibf_dspace_km);
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R_SSR3.dspace_sm <= IB_MREQ.din(ssr3_ibf_dspace_sm);
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R_SSR3.dspace_sm <= IB_MREQ.din(ssr3_ibf_dspace_sm);
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R_SSR3.dspace_um <= IB_MREQ.din(ssr3_ibf_dspace_um);
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R_SSR3.dspace_um <= IB_MREQ.din(ssr3_ibf_dspace_um);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process proc_ssr3;
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end process proc_ssr3;
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proc_paddr : process (R_SSR0, R_SSR3, CNTL, SARSDR, VADDR)
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proc_paddr : process (R_SSR0, R_SSR3, CNTL, SARSDR, VADDR)
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variable ipaddrh : slv16 := (others=>'0');
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variable ipaddrh : slv16 := (others=>'0');
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variable dspace_ok : slbit := '0';
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variable dspace_ok : slbit := '0';
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variable dspace_en : slbit := '0';
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variable dspace_en : slbit := '0';
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variable asf : slv3 := (others=>'0'); -- va: active segment field
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variable asf : slv3 := (others=>'0'); -- va: active segment field
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variable bn : slv7 := (others=>'0'); -- va: block number
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variable bn : slv7 := (others=>'0'); -- va: block number
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variable iasn : slv4 := (others=>'0');-- augmented segment number
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variable iasn : slv4 := (others=>'0');-- augmented segment number
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begin
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begin
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asf := VADDR(15 downto 13);
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asf := VADDR(15 downto 13);
|
bn := VADDR(12 downto 6);
|
bn := VADDR(12 downto 6);
|
|
|
dspace_en := '0';
|
dspace_en := '0';
|
case CNTL.mode is
|
case CNTL.mode is
|
when "00" => dspace_en := R_SSR3.dspace_km;
|
when "00" => dspace_en := R_SSR3.dspace_km;
|
when "01" => dspace_en := R_SSR3.dspace_sm;
|
when "01" => dspace_en := R_SSR3.dspace_sm;
|
when "11" => dspace_en := R_SSR3.dspace_um;
|
when "11" => dspace_en := R_SSR3.dspace_um;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
dspace_ok := CNTL.dspace and dspace_en;
|
dspace_ok := CNTL.dspace and dspace_en;
|
|
|
iasn(3) := dspace_ok;
|
iasn(3) := dspace_ok;
|
iasn(2 downto 0) := asf;
|
iasn(2 downto 0) := asf;
|
|
|
ipaddrh := unsigned("000000000"&bn) + unsigned(SARSDR.saf);
|
ipaddrh := unsigned("000000000"&bn) + unsigned(SARSDR.saf);
|
|
|
DSPACE <= dspace_ok;
|
DSPACE <= dspace_ok;
|
ASN <= iasn;
|
ASN <= iasn;
|
PADDRH <= ipaddrh;
|
PADDRH <= ipaddrh;
|
|
|
end process proc_paddr;
|
end process proc_paddr;
|
|
|
proc_nssr0 : process (R_SSR0, R_SSR3, IB_MREQ, IBSEL_SSR0, DSPACE,
|
proc_nssr0 : process (R_SSR0, R_SSR3, IB_MREQ, IBSEL_SSR0, DSPACE,
|
CNTL, MONI, SARSDR, VADDR)
|
CNTL, MONI, SARSDR, VADDR)
|
|
|
variable nssr0 : mmu_ssr0_type := mmu_ssr0_init;
|
variable nssr0 : mmu_ssr0_type := mmu_ssr0_init;
|
variable asf : slv3 := (others=>'0');
|
variable asf : slv3 := (others=>'0');
|
variable bn : slv7 := (others=>'0');
|
variable bn : slv7 := (others=>'0');
|
variable abo_nonres : slbit := '0';
|
variable abo_nonres : slbit := '0';
|
variable abo_length : slbit := '0';
|
variable abo_length : slbit := '0';
|
variable abo_rdonly : slbit := '0';
|
variable abo_rdonly : slbit := '0';
|
variable ssr_freeze : slbit := '0';
|
variable ssr_freeze : slbit := '0';
|
variable doabort : slbit := '0';
|
variable doabort : slbit := '0';
|
variable dotrap : slbit := '0';
|
variable dotrap : slbit := '0';
|
variable dotrace : slbit := '0';
|
variable dotrace : slbit := '0';
|
|
|
begin
|
begin
|
|
|
nssr0 := R_SSR0;
|
nssr0 := R_SSR0;
|
|
|
AIB_WE <= '0';
|
AIB_WE <= '0';
|
AIB_SETA <= '0';
|
AIB_SETA <= '0';
|
AIB_SETW <= '0';
|
AIB_SETW <= '0';
|
|
|
ssr_freeze := R_SSR0.abo_nonres or R_SSR0.abo_length or R_SSR0.abo_rdonly;
|
ssr_freeze := R_SSR0.abo_nonres or R_SSR0.abo_length or R_SSR0.abo_rdonly;
|
dotrace := not(CNTL.cacc or ssr_freeze);
|
dotrace := not(CNTL.cacc or ssr_freeze);
|
|
|
asf := VADDR(15 downto 13);
|
asf := VADDR(15 downto 13);
|
bn := VADDR(12 downto 6);
|
bn := VADDR(12 downto 6);
|
|
|
abo_nonres := '0';
|
abo_nonres := '0';
|
abo_length := '0';
|
abo_length := '0';
|
abo_rdonly := '0';
|
abo_rdonly := '0';
|
doabort := '0';
|
doabort := '0';
|
dotrap := '0';
|
dotrap := '0';
|
|
|
if SARSDR.ed = '0' then -- ed=0: upward expansion
|
if SARSDR.ed = '0' then -- ed=0: upward expansion
|
if unsigned(bn) > unsigned(SARSDR.slf) then
|
if unsigned(bn) > unsigned(SARSDR.slf) then
|
abo_length := '1';
|
abo_length := '1';
|
end if;
|
end if;
|
else -- ed=0: downward expansion
|
else -- ed=0: downward expansion
|
if unsigned(bn) < unsigned(SARSDR.slf) then
|
if unsigned(bn) < unsigned(SARSDR.slf) then
|
abo_length := '1';
|
abo_length := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
case SARSDR.acf is -- evaluate accecc control field
|
case SARSDR.acf is -- evaluate accecc control field
|
|
|
when "000" => -- segment non-resident
|
when "000" => -- segment non-resident
|
abo_nonres := '1';
|
abo_nonres := '1';
|
|
|
when "001" => -- read-only; trap on read
|
when "001" => -- read-only; trap on read
|
if CNTL.wacc='1' or CNTL.macc='1' then
|
if CNTL.wacc='1' or CNTL.macc='1' then
|
abo_rdonly := '1';
|
abo_rdonly := '1';
|
end if;
|
end if;
|
dotrap := '1';
|
dotrap := '1';
|
|
|
when "010" => -- read-only
|
when "010" => -- read-only
|
if CNTL.wacc='1' or CNTL.macc='1' then
|
if CNTL.wacc='1' or CNTL.macc='1' then
|
abo_rdonly := '1';
|
abo_rdonly := '1';
|
end if;
|
end if;
|
|
|
when "100" => -- read/write; trap on read&write
|
when "100" => -- read/write; trap on read&write
|
dotrap := '1';
|
dotrap := '1';
|
|
|
when "101" => -- read/write; trap on write
|
when "101" => -- read/write; trap on write
|
dotrap := CNTL.wacc or CNTL.macc;
|
dotrap := CNTL.wacc or CNTL.macc;
|
|
|
when "110" => null; -- read/write;
|
when "110" => null; -- read/write;
|
|
|
when others => -- unused codes: abort access
|
when others => -- unused codes: abort access
|
abo_nonres := '1';
|
abo_nonres := '1';
|
end case;
|
end case;
|
|
|
if IB_MREQ.we='1' and IBSEL_SSR0='1' then
|
if IB_MREQ.we='1' and IBSEL_SSR0='1' then
|
|
|
if IB_MREQ.be1 = '1' then
|
if IB_MREQ.be1 = '1' then
|
nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres);
|
nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres);
|
nssr0.abo_length := IB_MREQ.din(ssr0_ibf_abo_length);
|
nssr0.abo_length := IB_MREQ.din(ssr0_ibf_abo_length);
|
nssr0.abo_rdonly := IB_MREQ.din(ssr0_ibf_abo_rdonly);
|
nssr0.abo_rdonly := IB_MREQ.din(ssr0_ibf_abo_rdonly);
|
nssr0.trap_mmu := IB_MREQ.din(ssr0_ibf_trap_mmu);
|
nssr0.trap_mmu := IB_MREQ.din(ssr0_ibf_trap_mmu);
|
nssr0.ena_trap := IB_MREQ.din(ssr0_ibf_ena_trap);
|
nssr0.ena_trap := IB_MREQ.din(ssr0_ibf_ena_trap);
|
end if;
|
end if;
|
if IB_MREQ.be0 = '1' then
|
if IB_MREQ.be0 = '1' then
|
nssr0.ena_mmu := IB_MREQ.din(ssr0_ibf_ena_mmu);
|
nssr0.ena_mmu := IB_MREQ.din(ssr0_ibf_ena_mmu);
|
end if;
|
end if;
|
|
|
elsif nssr0.ena_mmu='1' and CNTL.cacc='0' then
|
elsif nssr0.ena_mmu='1' and CNTL.cacc='0' then
|
|
|
if dotrace = '1' then
|
if dotrace = '1' then
|
if MONI.istart = '1' then
|
if MONI.istart = '1' then
|
nssr0.inst_compl := '0';
|
nssr0.inst_compl := '0';
|
elsif MONI.idone = '1' then
|
elsif MONI.idone = '1' then
|
nssr0.inst_compl := '0'; -- disable instr.compl logic
|
nssr0.inst_compl := '0'; -- disable instr.compl logic
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if CNTL.req = '1' then
|
if CNTL.req = '1' then
|
AIB_WE <= '1';
|
AIB_WE <= '1';
|
if ssr_freeze = '0' then
|
if ssr_freeze = '0' then
|
nssr0.abo_nonres := abo_nonres;
|
nssr0.abo_nonres := abo_nonres;
|
nssr0.abo_length := abo_length;
|
nssr0.abo_length := abo_length;
|
nssr0.abo_rdonly := abo_rdonly;
|
nssr0.abo_rdonly := abo_rdonly;
|
end if;
|
end if;
|
doabort := abo_nonres or abo_length or abo_rdonly;
|
doabort := abo_nonres or abo_length or abo_rdonly;
|
|
|
if doabort = '0' then
|
if doabort = '0' then
|
AIB_SETA <= '1';
|
AIB_SETA <= '1';
|
AIB_SETW <= CNTL.wacc or CNTL.macc;
|
AIB_SETW <= CNTL.wacc or CNTL.macc;
|
end if;
|
end if;
|
|
|
if ssr_freeze = '0' then
|
if ssr_freeze = '0' then
|
nssr0.dspace := DSPACE;
|
nssr0.dspace := DSPACE;
|
nssr0.seg_num := asf;
|
nssr0.seg_num := asf;
|
nssr0.seg_mode := CNTL.mode;
|
nssr0.seg_mode := CNTL.mode;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if CNTL.req='1' and R_SSR0.ena_mmu='1' and CNTL.cacc='0' and
|
if CNTL.req='1' and R_SSR0.ena_mmu='1' and CNTL.cacc='0' and
|
dotrap='1' then
|
dotrap='1' then
|
nssr0.trap_mmu := '1';
|
nssr0.trap_mmu := '1';
|
end if;
|
end if;
|
|
|
nssr0.trace_prev := dotrace;
|
nssr0.trace_prev := dotrace;
|
|
|
if MONI.trace_prev = '0' then
|
if MONI.trace_prev = '0' then
|
TRACE <= dotrace;
|
TRACE <= dotrace;
|
else
|
else
|
TRACE <= R_SSR0.trace_prev;
|
TRACE <= R_SSR0.trace_prev;
|
end if;
|
end if;
|
|
|
N_SSR0 <= nssr0;
|
N_SSR0 <= nssr0;
|
|
|
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' then
|
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' then
|
STAT.vaok <= not doabort;
|
STAT.vaok <= not doabort;
|
else
|
else
|
STAT.vaok <= '1';
|
STAT.vaok <= '1';
|
end if;
|
end if;
|
|
|
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
|
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
|
R_SSR0.ena_trap='1' and R_SSR0.trap_mmu='0' and dotrap='1' then
|
R_SSR0.ena_trap='1' and R_SSR0.trap_mmu='0' and dotrap='1' then
|
STAT.trap <= '1';
|
STAT.trap <= '1';
|
else
|
else
|
STAT.trap <= '0';
|
STAT.trap <= '0';
|
end if;
|
end if;
|
|
|
STAT.ena_mmu <= R_SSR0.ena_mmu;
|
STAT.ena_mmu <= R_SSR0.ena_mmu;
|
STAT.ena_22bit <= R_SSR3.ena_22bit;
|
STAT.ena_22bit <= R_SSR3.ena_22bit;
|
STAT.ena_ubmap <= R_SSR3.ena_ubmap;
|
STAT.ena_ubmap <= R_SSR3.ena_ubmap;
|
|
|
end process proc_nssr0;
|
end process proc_nssr0;
|
|
|
end syn;
|
end syn;
|
|
|