-- $Id: pdp11_tmu.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: pdp11_tmu.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: pdp11_tmu - sim
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-- Module Name: pdp11_tmu - sim
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-- Description: pdp11: trace and monitor unit
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-- Description: pdp11: trace and monitor unit
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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--
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--
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ghdl 0.18-0.25
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-- Tool versions: ghdl 0.18-0.25
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
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-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
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-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
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-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
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-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
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-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
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-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
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-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
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-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
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-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
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-- 2008-04-19 137 1.0 Initial version
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-- 2008-04-19 137 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simlib.all;
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use work.simbus.all;
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use work.simbus.all;
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use work.pdp11.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity pdp11_tmu is -- trace and monitor unit
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entity pdp11_tmu is -- trace and monitor unit
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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ENA : in slbit := '0'; -- enable trace output
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ENA : in slbit := '0'; -- enable trace output
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DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
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DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
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DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
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DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
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DM_STAT_CO : in dm_stat_co_type; -- DM core
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DM_STAT_CO : in dm_stat_co_type; -- DM core
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DM_STAT_SY : in dm_stat_sy_type -- DM system
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DM_STAT_SY : in dm_stat_sy_type -- DM system
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);
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);
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end pdp11_tmu;
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end pdp11_tmu;
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architecture sim of pdp11_tmu is
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architecture sim of pdp11_tmu is
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signal R_FIRST : slbit := '1';
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signal R_FIRST : slbit := '1';
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begin
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begin
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proc_tm: process (CLK)
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proc_tm: process (CLK)
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variable oline : line;
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variable oline : line;
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variable ipsw : slv16 := (others=>'0');
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variable ipsw : slv16 := (others=>'0');
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variable ibaddr : slv16 := (others=>'0');
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variable ibaddr : slv16 := (others=>'0');
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variable emaddr : slv22 := (others=>'0');
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variable emaddr : slv22 := (others=>'0');
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variable dp_ireg_we_last : slbit := '0';
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variable dp_ireg_we_last : slbit := '0';
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variable vm_ibsres_busy_last : slbit := '0';
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variable vm_ibsres_busy_last : slbit := '0';
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variable vm_ibsres_ack_last : slbit := '0';
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variable vm_ibsres_ack_last : slbit := '0';
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variable wcycle : boolean := false;
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variable wcycle : boolean := false;
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file ofile : text open write_mode is "tmu_ofile";
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file ofile : text open write_mode is "tmu_ofile";
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begin
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begin
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if CLK'event and CLK='1' then
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if CLK'event and CLK='1' then
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if R_FIRST = '1' then
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if R_FIRST = '1' then
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R_FIRST <= '0';
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R_FIRST <= '0';
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write(oline, string'("#"));
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write(oline, string'("#"));
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write(oline, string'(" clkcycle:d"));
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write(oline, string'(" clkcycle:d"));
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write(oline, string'(" cpu:o"));
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write(oline, string'(" cpu:o"));
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write(oline, string'(" dp.pc:o"));
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write(oline, string'(" dp.pc:o"));
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write(oline, string'(" dp.psw:o"));
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write(oline, string'(" dp.psw:o"));
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write(oline, string'(" dp.ireg:o"));
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write(oline, string'(" dp.ireg:o"));
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write(oline, string'(" dp.ireg_we:b"));
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write(oline, string'(" dp.ireg_we:b"));
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write(oline, string'(" dp.ireg_we_last:b")); -- is ireg_we last cycle
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write(oline, string'(" dp.ireg_we_last:b")); -- is ireg_we last cycle
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write(oline, string'(" dp.dsrc:o"));
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write(oline, string'(" dp.dsrc:o"));
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write(oline, string'(" dp.ddst:o"));
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write(oline, string'(" dp.ddst:o"));
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write(oline, string'(" dp.dtmp:o"));
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write(oline, string'(" dp.dtmp:o"));
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write(oline, string'(" dp.dres:o"));
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write(oline, string'(" dp.dres:o"));
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write(oline, string'(" dp.gpr_adst:o"));
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write(oline, string'(" dp.gpr_adst:o"));
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write(oline, string'(" dp.gpr_mode:o"));
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write(oline, string'(" dp.gpr_mode:o"));
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write(oline, string'(" dp.gpr_bytop:b"));
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write(oline, string'(" dp.gpr_bytop:b"));
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write(oline, string'(" dp.gpr_we:b"));
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write(oline, string'(" dp.gpr_we:b"));
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write(oline, string'(" vm.ibmreq.req:b"));
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write(oline, string'(" vm.ibmreq.req:b"));
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write(oline, string'(" vm.ibmreq.we:b"));
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write(oline, string'(" vm.ibmreq.we:b"));
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write(oline, string'(" vm.ibmreq.be0:b"));
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write(oline, string'(" vm.ibmreq.be0:b"));
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write(oline, string'(" vm.ibmreq.be1:b"));
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write(oline, string'(" vm.ibmreq.be1:b"));
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write(oline, string'(" vm.ibmreq.dip:b"));
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write(oline, string'(" vm.ibmreq.dip:b"));
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write(oline, string'(" vm.ibmreq.cacc:b"));
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write(oline, string'(" vm.ibmreq.cacc:b"));
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write(oline, string'(" vm.ibmreq.racc:b"));
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write(oline, string'(" vm.ibmreq.racc:b"));
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write(oline, string'(" vm.ibmreq.addr:o"));
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write(oline, string'(" vm.ibmreq.addr:o"));
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write(oline, string'(" vm.ibmreq.din:o"));
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write(oline, string'(" vm.ibmreq.din:o"));
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write(oline, string'(" vm.ibsres.ack:b"));
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write(oline, string'(" vm.ibsres.ack:b"));
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write(oline, string'(" vm.ibsres.busy:b"));
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write(oline, string'(" vm.ibsres.busy:b"));
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write(oline, string'(" vm.ibsres.dout:o"));
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write(oline, string'(" vm.ibsres.dout:o"));
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write(oline, string'(" co.cpugo:b"));
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write(oline, string'(" co.cpugo:b"));
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write(oline, string'(" co.cpuhalt:b"));
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write(oline, string'(" co.cpuhalt:b"));
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write(oline, string'(" sy.emmreq.req:b"));
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write(oline, string'(" sy.emmreq.req:b"));
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write(oline, string'(" sy.emmreq.we:b"));
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write(oline, string'(" sy.emmreq.we:b"));
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write(oline, string'(" sy.emmreq.be:b"));
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write(oline, string'(" sy.emmreq.be:b"));
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write(oline, string'(" sy.emmreq.cancel:b"));
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write(oline, string'(" sy.emmreq.cancel:b"));
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write(oline, string'(" sy.emmreq.addr:o"));
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write(oline, string'(" sy.emmreq.addr:o"));
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write(oline, string'(" sy.emmreq.din:o"));
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write(oline, string'(" sy.emmreq.din:o"));
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write(oline, string'(" sy.emsres.ack_r:b"));
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write(oline, string'(" sy.emsres.ack_r:b"));
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write(oline, string'(" sy.emsres.ack_w:b"));
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write(oline, string'(" sy.emsres.ack_w:b"));
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write(oline, string'(" sy.emsres.dout:o"));
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write(oline, string'(" sy.emsres.dout:o"));
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write(oline, string'(" sy.chit:b"));
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write(oline, string'(" sy.chit:b"));
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writeline(ofile, oline);
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writeline(ofile, oline);
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end if;
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end if;
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ipsw := (others=>'0');
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ipsw := (others=>'0');
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ipsw(psw_ibf_cmode) := DM_STAT_DP.psw.cmode;
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ipsw(psw_ibf_cmode) := DM_STAT_DP.psw.cmode;
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ipsw(psw_ibf_pmode) := DM_STAT_DP.psw.pmode;
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ipsw(psw_ibf_pmode) := DM_STAT_DP.psw.pmode;
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ipsw(psw_ibf_rset) := DM_STAT_DP.psw.rset;
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ipsw(psw_ibf_rset) := DM_STAT_DP.psw.rset;
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ipsw(psw_ibf_pri) := DM_STAT_DP.psw.pri;
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ipsw(psw_ibf_pri) := DM_STAT_DP.psw.pri;
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ipsw(psw_ibf_tflag) := DM_STAT_DP.psw.tflag;
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ipsw(psw_ibf_tflag) := DM_STAT_DP.psw.tflag;
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ipsw(psw_ibf_cc) := DM_STAT_DP.psw.cc;
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ipsw(psw_ibf_cc) := DM_STAT_DP.psw.cc;
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ibaddr := "1110000000000000";
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ibaddr := "1110000000000000";
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ibaddr(DM_STAT_VM.ibmreq.addr'range) := DM_STAT_VM.ibmreq.addr;
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ibaddr(DM_STAT_VM.ibmreq.addr'range) := DM_STAT_VM.ibmreq.addr;
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emaddr := (others=>'0');
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emaddr := (others=>'0');
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emaddr(DM_STAT_SY.emmreq.addr'range) := DM_STAT_SY.emmreq.addr;
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emaddr(DM_STAT_SY.emmreq.addr'range) := DM_STAT_SY.emmreq.addr;
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wcycle := false;
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wcycle := false;
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if dp_ireg_we_last='1' or
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if dp_ireg_we_last='1' or
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DM_STAT_DP.gpr_we='1' or
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DM_STAT_DP.gpr_we='1' or
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DM_STAT_SY.emmreq.req='1' or
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DM_STAT_SY.emmreq.req='1' or
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DM_STAT_SY.emsres.ack_r='1' or
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DM_STAT_SY.emsres.ack_r='1' or
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DM_STAT_SY.emsres.ack_w='1' or
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DM_STAT_SY.emsres.ack_w='1' or
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DM_STAT_SY.emmreq.cancel='1' or
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DM_STAT_SY.emmreq.cancel='1' or
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DM_STAT_VM.ibmreq.req='1' or
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DM_STAT_VM.ibmreq.req='1' or
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DM_STAT_VM.ibsres.ack='1'
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DM_STAT_VM.ibsres.ack='1'
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then
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then
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wcycle := true;
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wcycle := true;
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end if;
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end if;
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if DM_STAT_VM.ibsres.busy='0' and
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if DM_STAT_VM.ibsres.busy='0' and
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(vm_ibsres_busy_last='1' and vm_ibsres_ack_last='0')
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(vm_ibsres_busy_last='1' and vm_ibsres_ack_last='0')
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then
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then
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wcycle := true;
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wcycle := true;
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end if;
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end if;
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if ENA = '0' then -- if not enabled
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if ENA = '0' then -- if not enabled
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wcycle := false; -- force to not logged...
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wcycle := false; -- force to not logged...
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end if;
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end if;
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if wcycle then
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if wcycle then
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write(oline, conv_integer(unsigned(SB_CLKCYCLE)), right, 9);
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write(oline, conv_integer(unsigned(SB_CLKCYCLE)), right, 9);
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write(oline, string'(" 0"));
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write(oline, string'(" 0"));
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writeoct(oline, DM_STAT_DP.pc, right, 7);
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writeoct(oline, DM_STAT_DP.pc, right, 7);
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writeoct(oline, ipsw, right, 7);
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writeoct(oline, ipsw, right, 7);
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writeoct(oline, DM_STAT_DP.ireg, right, 7);
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writeoct(oline, DM_STAT_DP.ireg, right, 7);
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write(oline, DM_STAT_DP.ireg_we, right, 2);
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write(oline, DM_STAT_DP.ireg_we, right, 2);
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write(oline, dp_ireg_we_last, right, 2);
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write(oline, dp_ireg_we_last, right, 2);
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writeoct(oline, DM_STAT_DP.dsrc, right, 7);
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writeoct(oline, DM_STAT_DP.dsrc, right, 7);
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writeoct(oline, DM_STAT_DP.ddst, right, 7);
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writeoct(oline, DM_STAT_DP.ddst, right, 7);
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writeoct(oline, DM_STAT_DP.dtmp, right, 7);
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writeoct(oline, DM_STAT_DP.dtmp, right, 7);
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writeoct(oline, DM_STAT_DP.dres, right, 7);
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writeoct(oline, DM_STAT_DP.dres, right, 7);
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writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
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writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
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writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
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writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
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write(oline, DM_STAT_DP.gpr_bytop, right, 2);
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write(oline, DM_STAT_DP.gpr_bytop, right, 2);
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write(oline, DM_STAT_DP.gpr_we, right, 2);
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write(oline, DM_STAT_DP.gpr_we, right, 2);
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write(oline, DM_STAT_VM.ibmreq.req, right, 2);
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write(oline, DM_STAT_VM.ibmreq.req, right, 2);
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write(oline, DM_STAT_VM.ibmreq.we, right, 2);
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write(oline, DM_STAT_VM.ibmreq.we, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
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write(oline, DM_STAT_VM.ibmreq.dip, right, 2);
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write(oline, DM_STAT_VM.ibmreq.dip, right, 2);
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write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
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write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
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write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
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write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
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writeoct(oline, ibaddr, right, 7);
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writeoct(oline, ibaddr, right, 7);
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writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
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writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
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write(oline, DM_STAT_VM.ibsres.ack, right, 2);
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write(oline, DM_STAT_VM.ibsres.ack, right, 2);
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write(oline, DM_STAT_VM.ibsres.busy, right, 2);
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write(oline, DM_STAT_VM.ibsres.busy, right, 2);
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writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7);
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writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7);
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write(oline, DM_STAT_CO.cpugo, right, 2);
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write(oline, DM_STAT_CO.cpugo, right, 2);
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write(oline, DM_STAT_CO.cpuhalt, right, 2);
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write(oline, DM_STAT_CO.cpuhalt, right, 2);
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write(oline, DM_STAT_SY.emmreq.req, right, 2);
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write(oline, DM_STAT_SY.emmreq.req, right, 2);
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write(oline, DM_STAT_SY.emmreq.we, right, 2);
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write(oline, DM_STAT_SY.emmreq.we, right, 2);
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write(oline, DM_STAT_SY.emmreq.be, right, 3);
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write(oline, DM_STAT_SY.emmreq.be, right, 3);
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write(oline, DM_STAT_SY.emmreq.cancel, right, 2);
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write(oline, DM_STAT_SY.emmreq.cancel, right, 2);
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writeoct(oline, emaddr, right, 9);
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writeoct(oline, emaddr, right, 9);
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writeoct(oline, DM_STAT_SY.emmreq.din, right, 7);
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writeoct(oline, DM_STAT_SY.emmreq.din, right, 7);
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write(oline, DM_STAT_SY.emsres.ack_r, right, 2);
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write(oline, DM_STAT_SY.emsres.ack_r, right, 2);
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write(oline, DM_STAT_SY.emsres.ack_w, right, 2);
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write(oline, DM_STAT_SY.emsres.ack_w, right, 2);
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writeoct(oline, DM_STAT_SY.emsres.dout, right, 7);
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writeoct(oline, DM_STAT_SY.emsres.dout, right, 7);
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write(oline, DM_STAT_SY.chit, right, 2);
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write(oline, DM_STAT_SY.chit, right, 2);
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writeline(ofile, oline);
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writeline(ofile, oline);
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end if;
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end if;
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dp_ireg_we_last := DM_STAT_DP.ireg_we;
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dp_ireg_we_last := DM_STAT_DP.ireg_we;
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vm_ibsres_busy_last := DM_STAT_VM.ibsres.busy;
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vm_ibsres_busy_last := DM_STAT_VM.ibsres.busy;
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vm_ibsres_ack_last := DM_STAT_VM.ibsres.ack;
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vm_ibsres_ack_last := DM_STAT_VM.ibsres.ack;
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end if;
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end if;
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end process proc_tm;
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end process proc_tm;
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end sim;
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end sim;
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