-- $Id: pdp11_vmbox.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: pdp11_vmbox.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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--
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-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: pdp11_vmbox - syn
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-- Module Name: pdp11_vmbox - syn
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-- Description: pdp11: virtual memory
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-- Description: pdp11: virtual memory
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--
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--
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-- Dependencies: pdp11_mmu
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-- Dependencies: pdp11_mmu
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-- pdp11_ubmap
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-- pdp11_ubmap
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-- ibus/ib_sres_or_4
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-- ibus/ib_sres_or_4
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-- ibus/ib_sres_or_2
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-- ibus/ib_sres_or_2
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--
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--
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
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-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
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-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
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-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
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-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
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-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
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-- from CP_ADDR; now all ibr handling via vmbox
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-- from CP_ADDR; now all ibr handling via vmbox
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-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
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-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
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-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
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-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
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-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
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-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
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-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
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-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
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-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
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-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
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-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
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-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
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-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
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-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
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-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
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-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
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-- 2008-03-02 121 1.3.1 remove snoopers
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-- 2008-03-02 121 1.3.1 remove snoopers
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-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
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-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
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-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
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-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
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-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
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-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
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-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
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-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
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-- 2008-01-05 110 1.1.3 update snooper.
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-- 2008-01-05 110 1.1.3 update snooper.
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-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
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-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
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-- all status into regs_type. add intbus HOLD support.
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-- all status into regs_type. add intbus HOLD support.
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-- 2007-12-30 108 1.1.1 use ubf_byte[01]
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-- 2007-12-30 108 1.1.1 use ubf_byte[01]
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-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
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-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
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-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
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-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
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-- 2nd port was unused, connected ADDR caused slow net
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-- 2nd port was unused, connected ADDR caused slow net
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.iblib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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use work.sys_conf.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity pdp11_vmbox is -- virtual memory
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entity pdp11_vmbox is -- virtual memory
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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GRESET : in slbit; -- global reset
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GRESET : in slbit; -- global reset
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CRESET : in slbit; -- console reset
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CRESET : in slbit; -- console reset
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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CP_ADDR : in cp_addr_type; -- console port address
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CP_ADDR : in cp_addr_type; -- console port address
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VM_CNTL : in vm_cntl_type; -- vm control port
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VM_CNTL : in vm_cntl_type; -- vm control port
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VM_ADDR : in slv16; -- vm address
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VM_ADDR : in slv16; -- vm address
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VM_DIN : in slv16; -- vm data in
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VM_DIN : in slv16; -- vm data in
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VM_STAT : out vm_stat_type; -- vm status port
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VM_STAT : out vm_stat_type; -- vm status port
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VM_DOUT : out slv16; -- vm data out
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VM_DOUT : out slv16; -- vm data out
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EM_MREQ : out em_mreq_type; -- external memory: request
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EM_MREQ : out em_mreq_type; -- external memory: request
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EM_SRES : in em_sres_type; -- external memory: response
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EM_SRES : in em_sres_type; -- external memory: response
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MMU_MONI : in mmu_moni_type; -- mmu monitor port
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MMU_MONI : in mmu_moni_type; -- mmu monitor port
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IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
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IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
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IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
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IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
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IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
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IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
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DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
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DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
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);
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);
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end pdp11_vmbox;
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end pdp11_vmbox;
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architecture syn of pdp11_vmbox is
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architecture syn of pdp11_vmbox is
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constant ibaddr_slim : slv16 := conv_std_logic_vector(8#177774#,16);
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constant ibaddr_slim : slv16 := conv_std_logic_vector(8#177774#,16);
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constant atowidth : natural := 5; -- size of access timeout counter
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constant atowidth : natural := 5; -- size of access timeout counter
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: wait for vm_cntl request
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s_idle, -- s_idle: wait for vm_cntl request
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s_mem_w, -- s_mem_w: check mmu, wait for memory
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s_mem_w, -- s_mem_w: check mmu, wait for memory
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s_ib_w, -- s_ib_w: wait for ibus
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s_ib_w, -- s_ib_w: wait for ibus
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s_ib_wend, -- s_ib_wend: ibus write completion
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s_ib_wend, -- s_ib_wend: ibus write completion
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s_ib_rend, -- s_ib_rend: ibus read completion
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s_ib_rend, -- s_ib_rend: ibus read completion
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s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
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s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
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s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
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s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
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s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
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s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
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s_fail, -- s_fail: vmbox fatal error catcher
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s_fail, -- s_fail: vmbox fatal error catcher
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s_errrsv, -- s_errrsv: red stack violation
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s_errrsv, -- s_errrsv: red stack violation
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s_errib -- s_errib: ibus error handler
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s_errib -- s_errib: ibus error handler
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);
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);
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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state : state_type; -- state
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state : state_type; -- state
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wacc : slbit; -- write access
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wacc : slbit; -- write access
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macc : slbit; -- modify access (r-m-w sequence)
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macc : slbit; -- modify access (r-m-w sequence)
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cacc : slbit; -- console access
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cacc : slbit; -- console access
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bytop : slbit; -- byte operation
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bytop : slbit; -- byte operation
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kstack : slbit; -- access through kernel stack
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kstack : slbit; -- access through kernel stack
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ysv : slbit; -- yellow stack violation detected
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ysv : slbit; -- yellow stack violation detected
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vaok : slbit; -- virtual address valid (from MMU)
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vaok : slbit; -- virtual address valid (from MMU)
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trap_mmu : slbit; -- mmu trace trap requested
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trap_mmu : slbit; -- mmu trace trap requested
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mdin : slv16; -- data input (memory order)
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mdin : slv16; -- data input (memory order)
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paddr : slv22; -- physical address register
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paddr : slv22; -- physical address register
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atocnt : slv(atowidth-1 downto 0); -- access timeout counter
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atocnt : slv(atowidth-1 downto 0); -- access timeout counter
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ibreq : slbit; -- ibus req signal
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ibreq : slbit; -- ibus req signal
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ibwe : slbit; -- ibus we signal
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ibwe : slbit; -- ibus we signal
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ibbe : slv2; -- ibus be0,be1 signals
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ibbe : slv2; -- ibus be0,be1 signals
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ibdip : slbit; -- ibus dip signal
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ibdip : slbit; -- ibus dip signal
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ibcacc : slbit; -- ibus cacc signal
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ibcacc : slbit; -- ibus cacc signal
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ibracc : slbit; -- ibus racc signal
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ibracc : slbit; -- ibus racc signal
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ibaddr : slv13_1; -- ibus addr signal
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ibaddr : slv13_1; -- ibus addr signal
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ibdout : slv16; -- ibus dout register
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ibdout : slv16; -- ibus dout register
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end record regs_type;
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end record regs_type;
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constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
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constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle, -- state
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s_idle, -- state
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'0','0','0','0', -- wacc,macc,cacc,bytop
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'0','0','0','0', -- wacc,macc,cacc,bytop
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'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
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'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
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(others=>'0'), -- mdin
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(others=>'0'), -- mdin
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(others=>'0'), -- paddr
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(others=>'0'), -- paddr
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atocnt_init, -- atocnt
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atocnt_init, -- atocnt
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'0','0',"00", -- ibreq,ibwe,ibbe
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'0','0',"00", -- ibreq,ibwe,ibbe
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'0','0','0', -- ibdip,ibcacc,ibracc
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'0','0','0', -- ibdip,ibcacc,ibracc
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(others=>'0'), -- ibaddr
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(others=>'0'), -- ibaddr
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(others=>'0') -- ibdout
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(others=>'0') -- ibdout
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);
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);
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signal R_REGS : regs_type := regs_init;
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
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signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
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signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
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signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
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signal MMU_STAT : mmu_stat_type := mmu_stat_init;
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signal MMU_STAT : mmu_stat_type := mmu_stat_init;
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signal PADDRH : slv16 := (others=>'0');
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signal PADDRH : slv16 := (others=>'0');
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signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
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signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
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signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
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signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
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signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
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signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
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signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
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signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
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signal UBMAP_MREQ : slbit := '0';
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signal UBMAP_MREQ : slbit := '0';
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signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
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signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
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signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
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signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
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signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
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signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
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signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
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signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
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begin
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begin
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MMU : pdp11_mmu
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MMU : pdp11_mmu
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CRESET => CRESET,
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CRESET => CRESET,
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BRESET => BRESET,
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BRESET => BRESET,
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CNTL => MMU_CNTL,
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CNTL => MMU_CNTL,
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VADDR => VM_ADDR,
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VADDR => VM_ADDR,
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MONI => MMU_MONI,
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MONI => MMU_MONI,
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STAT => MMU_STAT,
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STAT => MMU_STAT,
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PADDRH => PADDRH,
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PADDRH => PADDRH,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_MMU
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IB_SRES => IB_SRES_MMU
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);
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);
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UBMAP : pdp11_ubmap
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UBMAP : pdp11_ubmap
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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MREQ => UBMAP_MREQ,
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MREQ => UBMAP_MREQ,
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ADDR_UB => CP_ADDR.addr(17 downto 1),
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ADDR_UB => CP_ADDR.addr(17 downto 1),
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ADDR_PM => UBMAP_ADDR_PM,
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ADDR_PM => UBMAP_ADDR_PM,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_UBMAP
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IB_SRES => IB_SRES_UBMAP
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);
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);
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IB_SRES_OR_INT : ib_sres_or_4
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IB_SRES_OR_INT : ib_sres_or_4
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port map (
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port map (
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IB_SRES_1 => IB_SRES_CPU,
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IB_SRES_1 => IB_SRES_CPU,
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IB_SRES_2 => IB_SRES_SLIM,
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IB_SRES_2 => IB_SRES_SLIM,
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IB_SRES_3 => IB_SRES_MMU,
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IB_SRES_3 => IB_SRES_MMU,
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IB_SRES_4 => IB_SRES_UBMAP,
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IB_SRES_4 => IB_SRES_UBMAP,
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IB_SRES_OR => IB_SRES_INT
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IB_SRES_OR => IB_SRES_INT
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);
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);
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IB_SRES_OR_ALL : ib_sres_or_2
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IB_SRES_OR_ALL : ib_sres_or_2
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port map (
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port map (
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IB_SRES_1 => IB_SRES_INT,
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IB_SRES_1 => IB_SRES_INT,
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IB_SRES_2 => IB_SRES_EXT,
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IB_SRES_2 => IB_SRES_EXT,
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IB_SRES_OR => IB_SRES
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IB_SRES_OR => IB_SRES
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);
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);
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proc_ibsel: process (IB_MREQ)
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proc_ibsel: process (IB_MREQ)
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variable islim : slbit := '0';
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variable islim : slbit := '0';
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begin
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begin
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islim := '0';
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islim := '0';
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if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_slim(12 downto 1) then
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if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_slim(12 downto 1) then
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islim := '1';
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islim := '1';
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end if;
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end if;
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IBSEL_SLIM <= islim;
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IBSEL_SLIM <= islim;
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IB_SRES_SLIM.ack <= islim;
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IB_SRES_SLIM.ack <= islim;
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IB_SRES_SLIM.busy <= '0';
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IB_SRES_SLIM.busy <= '0';
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end process proc_ibsel;
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end process proc_ibsel;
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proc_ibdout : process (IBSEL_SLIM, R_SLIM)
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proc_ibdout : process (IBSEL_SLIM, R_SLIM)
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variable slimout : slv16 := (others=>'0');
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variable slimout : slv16 := (others=>'0');
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begin
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begin
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slimout := (others=>'0');
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slimout := (others=>'0');
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if IBSEL_SLIM = '1' then
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if IBSEL_SLIM = '1' then
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slimout(ibf_byte1) := R_SLIM;
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slimout(ibf_byte1) := R_SLIM;
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end if;
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end if;
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IB_SRES_SLIM.dout <= slimout;
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IB_SRES_SLIM.dout <= slimout;
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end process proc_ibdout;
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end process proc_ibdout;
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proc_slim: process (CLK)
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proc_slim: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if CLK'event and CLK='1' then
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if BRESET = '1' then
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if BRESET = '1' then
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R_SLIM <= (others=>'0');
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R_SLIM <= (others=>'0');
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elsif IB_MREQ.we='1' and IBSEL_SLIM='1' then
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elsif IB_MREQ.we='1' and IBSEL_SLIM='1' then
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if IB_MREQ.be1 = '1' then
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if IB_MREQ.be1 = '1' then
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R_SLIM <= IB_MREQ.din(ibf_byte1);
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R_SLIM <= IB_MREQ.din(ibf_byte1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
|
end process proc_slim;
|
end process proc_slim;
|
|
|
proc_regs: process (CLK)
|
proc_regs: process (CLK)
|
begin
|
begin
|
if CLK'event and CLK='1' then
|
if CLK'event and CLK='1' then
|
if GRESET = '1' then
|
if GRESET = '1' then
|
R_REGS <= regs_init;
|
R_REGS <= regs_init;
|
else
|
else
|
R_REGS <= N_REGS;
|
R_REGS <= N_REGS;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process proc_regs;
|
end process proc_regs;
|
|
|
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
|
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
|
IB_SRES, UBMAP_ADDR_PM,
|
IB_SRES, UBMAP_ADDR_PM,
|
EM_SRES, MMU_STAT, PADDRH)
|
EM_SRES, MMU_STAT, PADDRH)
|
|
|
variable r : regs_type := regs_init;
|
variable r : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
|
|
variable ivm_stat : vm_stat_type := vm_stat_init;
|
variable ivm_stat : vm_stat_type := vm_stat_init;
|
variable ivm_dout : slv16 := (others=>'0');
|
variable ivm_dout : slv16 := (others=>'0');
|
variable ipaddr : slv22 := (others=>'0');
|
variable ipaddr : slv22 := (others=>'0');
|
variable iem_mreq : em_mreq_type := em_mreq_init;
|
variable iem_mreq : em_mreq_type := em_mreq_init;
|
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
|
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
|
|
|
variable ato_go : slbit := '0';
|
variable ato_go : slbit := '0';
|
variable ato_end : slbit := '0';
|
variable ato_end : slbit := '0';
|
|
|
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
|
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
|
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
|
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
|
|
|
variable iubmap_mreq : slbit := '0';
|
variable iubmap_mreq : slbit := '0';
|
variable paddr_mmu : slbit := '0';
|
variable paddr_mmu : slbit := '0';
|
variable paddr_sel : slv2 := "00";
|
variable paddr_sel : slv2 := "00";
|
constant c_paddr_sel_vmaddr : slv2 := "00";
|
constant c_paddr_sel_vmaddr : slv2 := "00";
|
constant c_paddr_sel_rpaddr : slv2 := "01";
|
constant c_paddr_sel_rpaddr : slv2 := "01";
|
constant c_paddr_sel_cacc : slv2 := "10";
|
constant c_paddr_sel_cacc : slv2 := "10";
|
constant c_paddr_sel_ubmap : slv2 := "11";
|
constant c_paddr_sel_ubmap : slv2 := "11";
|
|
|
variable paddr_iopage : slv9 := (others=>'0');
|
variable paddr_iopage : slv9 := (others=>'0');
|
|
|
begin
|
begin
|
|
|
r := R_REGS;
|
r := R_REGS;
|
n := R_REGS;
|
n := R_REGS;
|
|
|
n.state := s_fail;
|
n.state := s_fail;
|
|
|
ivm_stat := vm_stat_init;
|
ivm_stat := vm_stat_init;
|
ivm_dout := EM_SRES.dout;
|
ivm_dout := EM_SRES.dout;
|
immu_cntl := mmu_cntl_init;
|
immu_cntl := mmu_cntl_init;
|
|
|
iem_mreq := em_mreq_init;
|
iem_mreq := em_mreq_init;
|
iem_mreq.din := VM_DIN;
|
iem_mreq.din := VM_DIN;
|
|
|
if VM_CNTL.bytop = '0' then -- if word access
|
if VM_CNTL.bytop = '0' then -- if word access
|
iem_mreq.be := "11"; -- both be's
|
iem_mreq.be := "11"; -- both be's
|
else
|
else
|
if VM_ADDR(0) = '0' then -- if low byte
|
if VM_ADDR(0) = '0' then -- if low byte
|
iem_mreq.be := "01";
|
iem_mreq.be := "01";
|
else -- if high byte
|
else -- if high byte
|
iem_mreq.be := "10";
|
iem_mreq.be := "10";
|
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
|
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
iubmap_mreq :='0';
|
iubmap_mreq :='0';
|
|
|
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
|
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
|
-- and overwritten in s_idle_mw_mem
|
-- and overwritten in s_idle_mw_mem
|
paddr_sel := "00";
|
paddr_sel := "00";
|
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
|
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
|
paddr_mmu := '0';
|
paddr_mmu := '0';
|
paddr_sel := c_paddr_sel_vmaddr;
|
paddr_sel := c_paddr_sel_vmaddr;
|
if VM_CNTL.cacc = '1' then
|
if VM_CNTL.cacc = '1' then
|
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
|
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
|
paddr_sel := c_paddr_sel_ubmap;
|
paddr_sel := c_paddr_sel_ubmap;
|
else
|
else
|
paddr_sel := c_paddr_sel_cacc;
|
paddr_sel := c_paddr_sel_cacc;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
paddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
|
paddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
|
if r.cacc = '1' then
|
if r.cacc = '1' then
|
if CP_ADDR.ena_22bit = '0' then
|
if CP_ADDR.ena_22bit = '0' then
|
paddr_iopage := "000000111"; -- 16 bit cacc
|
paddr_iopage := "000000111"; -- 16 bit cacc
|
end if;
|
end if;
|
else
|
else
|
if MMU_STAT.ena_mmu = '0' then
|
if MMU_STAT.ena_mmu = '0' then
|
paddr_iopage := "000000111"; -- 16 bit mode
|
paddr_iopage := "000000111"; -- 16 bit mode
|
else
|
else
|
if MMU_STAT.ena_22bit = '0' then
|
if MMU_STAT.ena_22bit = '0' then
|
paddr_iopage := "000011111"; -- 18 bit mode
|
paddr_iopage := "000011111"; -- 18 bit mode
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
ato_go := '0'; -- default: keep access timeout in reset
|
ato_go := '0'; -- default: keep access timeout in reset
|
ato_end := '0';
|
ato_end := '0';
|
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
|
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
|
ato_end := '1'; -- signal expiration
|
ato_end := '1'; -- signal expiration
|
end if;
|
end if;
|
|
|
is_stackyellow := '0';
|
is_stackyellow := '0';
|
is_stackred := '0';
|
is_stackred := '0';
|
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
|
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
|
is_stackyellow := '1';
|
is_stackyellow := '1';
|
if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
|
if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
|
is_stackred := '1';
|
is_stackred := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
|
if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
|
is_stackred := '1';
|
is_stackred := '1';
|
end if;
|
end if;
|
|
|
immu_cntl.wacc := VM_CNTL.wacc;
|
immu_cntl.wacc := VM_CNTL.wacc;
|
immu_cntl.macc := VM_CNTL.macc;
|
immu_cntl.macc := VM_CNTL.macc;
|
immu_cntl.cacc := VM_CNTL.cacc;
|
immu_cntl.cacc := VM_CNTL.cacc;
|
immu_cntl.dspace := VM_CNTL.dspace;
|
immu_cntl.dspace := VM_CNTL.dspace;
|
immu_cntl.mode := VM_CNTL.mode;
|
immu_cntl.mode := VM_CNTL.mode;
|
immu_cntl.trap_done := VM_CNTL.trap_done;
|
immu_cntl.trap_done := VM_CNTL.trap_done;
|
|
|
case r.state is
|
case r.state is
|
when s_idle => -- s_idle: wait for vm_cntl request --
|
when s_idle => -- s_idle: wait for vm_cntl request --
|
n.state := s_idle;
|
n.state := s_idle;
|
iubmap_mreq := '1'; -- activate ubmap always in s_idle
|
iubmap_mreq := '1'; -- activate ubmap always in s_idle
|
|
|
if VM_CNTL.req = '1' then
|
if VM_CNTL.req = '1' then
|
n.wacc := VM_CNTL.wacc;
|
n.wacc := VM_CNTL.wacc;
|
n.macc := VM_CNTL.macc;
|
n.macc := VM_CNTL.macc;
|
n.cacc := VM_CNTL.cacc;
|
n.cacc := VM_CNTL.cacc;
|
n.bytop := VM_CNTL.bytop;
|
n.bytop := VM_CNTL.bytop;
|
n.kstack := VM_CNTL.kstack;
|
n.kstack := VM_CNTL.kstack;
|
n.ysv := '0';
|
n.ysv := '0';
|
n.vaok := MMU_STAT.vaok;
|
n.vaok := MMU_STAT.vaok;
|
n.trap_mmu := MMU_STAT.trap;
|
n.trap_mmu := MMU_STAT.trap;
|
n.mdin := iem_mreq.din;
|
n.mdin := iem_mreq.din;
|
-- n.paddr assignment handled separately in 'if state=s_idle' at the
|
-- n.paddr assignment handled separately in 'if state=s_idle' at the
|
-- end.
|
-- end.
|
|
|
immu_cntl.req := '1';
|
immu_cntl.req := '1';
|
|
|
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
|
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
|
n.state := s_fail;
|
n.state := s_fail;
|
|
|
elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
|
elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
|
is_stackred='1' then
|
is_stackred='1' then
|
n.state := s_errrsv;
|
n.state := s_errrsv;
|
|
|
else
|
else
|
iem_mreq.req := '1';
|
iem_mreq.req := '1';
|
iem_mreq.we := VM_CNTL.wacc;
|
iem_mreq.we := VM_CNTL.wacc;
|
if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
|
if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
|
n.ysv := is_stackyellow;
|
n.ysv := is_stackyellow;
|
end if;
|
end if;
|
n.state := s_mem_w;
|
n.state := s_mem_w;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_mem_w => -- s_mem_w: check mmu, wait for memory
|
when s_mem_w => -- s_mem_w: check mmu, wait for memory
|
|
|
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
|
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
|
ivm_stat.err := '1';
|
ivm_stat.err := '1';
|
ivm_stat.err_odd := '1';
|
ivm_stat.err_odd := '1';
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
elsif r.vaok = '0' then -- MMU abort ?
|
elsif r.vaok = '0' then -- MMU abort ?
|
ivm_stat.err := '1';
|
ivm_stat.err := '1';
|
ivm_stat.err_mmu := '1';
|
ivm_stat.err_mmu := '1';
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
else
|
else
|
if r.paddr(21 downto 13) = paddr_iopage then
|
if r.paddr(21 downto 13) = paddr_iopage then
|
-- I/O page decoded
|
-- I/O page decoded
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
n.ibreq := '1'; -- setup ibus request
|
n.ibreq := '1'; -- setup ibus request
|
n.ibwe := r.wacc;
|
n.ibwe := r.wacc;
|
n.ibcacc := r.cacc;
|
n.ibcacc := r.cacc;
|
n.ibracc := r.cacc and CP_ADDR.racc;
|
n.ibracc := r.cacc and CP_ADDR.racc;
|
n.ibbe := "11";
|
n.ibbe := "11";
|
if r.cacc = '1' then -- console access ?
|
if r.cacc = '1' then -- console access ?
|
n.ibbe := CP_ADDR.be;
|
n.ibbe := CP_ADDR.be;
|
else -- cpu access ?
|
else -- cpu access ?
|
if r.bytop = '1' then
|
if r.bytop = '1' then
|
if r.paddr(0) = '0' then
|
if r.paddr(0) = '0' then
|
n.ibbe(1) := '0';
|
n.ibbe(1) := '0';
|
else
|
else
|
n.ibbe(0) := '0';
|
n.ibbe(0) := '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
n.ibdip := r.macc;
|
n.ibdip := r.macc;
|
n.ibaddr := r.paddr(12 downto 1);
|
n.ibaddr := r.paddr(12 downto 1);
|
n.state := s_ib_w;
|
n.state := s_ib_w;
|
|
|
else
|
else
|
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
|
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
|
ivm_stat.err := '1';
|
ivm_stat.err := '1';
|
ivm_stat.err_nxm := '1';
|
ivm_stat.err_nxm := '1';
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
iem_mreq.cancel := '1'; -- cancel pending mem request
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
else
|
else
|
|
|
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
|
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
|
ivm_stat.ack := '1';
|
ivm_stat.ack := '1';
|
ivm_stat.trap_ysv := r.ysv;
|
ivm_stat.trap_ysv := r.ysv;
|
ivm_stat.trap_mmu := r.trap_mmu;
|
ivm_stat.trap_mmu := r.trap_mmu;
|
if r.macc='1' and r.wacc='0' then
|
if r.macc='1' and r.wacc='0' then
|
n.state := s_idle_mw_mem;
|
n.state := s_idle_mw_mem;
|
else
|
else
|
n.state := s_idle;
|
n.state := s_idle;
|
end if;
|
end if;
|
else
|
else
|
n.state := s_mem_w; -- keep waiting
|
n.state := s_mem_w; -- keep waiting
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_ib_w => -- s_ib_w: wait for ibus -------------
|
when s_ib_w => -- s_ib_w: wait for ibus -------------
|
ato_go := '1'; -- activate timeout counter
|
ato_go := '1'; -- activate timeout counter
|
|
|
n.ibreq := '0'; -- end cycle, unless busy seen
|
n.ibreq := '0'; -- end cycle, unless busy seen
|
n.ibwe := '0';
|
n.ibwe := '0';
|
|
|
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
|
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
|
if r.wacc = '1' then
|
if r.wacc = '1' then
|
n.state := s_ib_wend;
|
n.state := s_ib_wend;
|
else
|
else
|
n.ibdout := IB_SRES.dout;
|
n.ibdout := IB_SRES.dout;
|
n.state := s_ib_rend;
|
n.state := s_ib_rend;
|
end if;
|
end if;
|
elsif IB_SRES.busy='1' and ato_end='0' then
|
elsif IB_SRES.busy='1' and ato_end='0' then
|
n.ibreq := r.ibreq; -- continue ibus cycle
|
n.ibreq := r.ibreq; -- continue ibus cycle
|
n.ibwe := r.ibwe;
|
n.ibwe := r.ibwe;
|
n.state := s_ib_w;
|
n.state := s_ib_w;
|
else
|
else
|
n.state := s_errib;
|
n.state := s_errib;
|
end if;
|
end if;
|
|
|
when s_ib_wend => -- s_ib_wend: ibus write completion --
|
when s_ib_wend => -- s_ib_wend: ibus write completion --
|
ivm_stat.ack := '1';
|
ivm_stat.ack := '1';
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
when s_ib_rend => -- s_ib_rend: ibus read completion ---
|
when s_ib_rend => -- s_ib_rend: ibus read completion ---
|
ivm_stat.ack := '1';
|
ivm_stat.ack := '1';
|
ivm_dout := r.ibdout;
|
ivm_dout := r.ibdout;
|
if r.macc='1' and r.wacc='0' then -- first part of read-mod-write
|
if r.macc='1' and r.wacc='0' then -- first part of read-mod-write
|
n.state := s_idle_mw_ib;
|
n.state := s_idle_mw_ib;
|
else
|
else
|
n.state := s_idle;
|
n.state := s_idle;
|
end if;
|
end if;
|
|
|
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
|
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
|
n.state := s_idle_mw_ib;
|
n.state := s_idle_mw_ib;
|
if r.ibbe = "10" then
|
if r.ibbe = "10" then
|
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
|
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
|
end if;
|
end if;
|
if VM_CNTL.req = '1' then
|
if VM_CNTL.req = '1' then
|
n.wacc := VM_CNTL.wacc;
|
n.wacc := VM_CNTL.wacc;
|
n.macc := VM_CNTL.macc;
|
n.macc := VM_CNTL.macc;
|
n.mdin := iem_mreq.din;
|
n.mdin := iem_mreq.din;
|
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
|
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
|
n.state := s_fail;
|
n.state := s_fail;
|
else
|
else
|
n.ibreq := '1'; -- start ibus write cycle
|
n.ibreq := '1'; -- start ibus write cycle
|
n.ibwe := '1'; -- Note: all other ibus drivers
|
n.ibwe := '1'; -- Note: all other ibus drivers
|
-- already set in 1st part
|
-- already set in 1st part
|
n.state := s_ib_w;
|
n.state := s_ib_w;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
|
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
|
n.state := s_idle_mw_mem;
|
n.state := s_idle_mw_mem;
|
|
|
paddr_mmu := '0';
|
paddr_mmu := '0';
|
paddr_sel := c_paddr_sel_rpaddr;
|
paddr_sel := c_paddr_sel_rpaddr;
|
|
|
if VM_CNTL.bytop = '0' then -- if word access
|
if VM_CNTL.bytop = '0' then -- if word access
|
iem_mreq.be := "11"; -- both be's
|
iem_mreq.be := "11"; -- both be's
|
else
|
else
|
if r.paddr(0) = '0' then -- if low byte
|
if r.paddr(0) = '0' then -- if low byte
|
iem_mreq.be := "01";
|
iem_mreq.be := "01";
|
else -- if high byte
|
else -- if high byte
|
iem_mreq.be := "10";
|
iem_mreq.be := "10";
|
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
|
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if VM_CNTL.req = '1' then
|
if VM_CNTL.req = '1' then
|
n.wacc := VM_CNTL.wacc;
|
n.wacc := VM_CNTL.wacc;
|
n.macc := VM_CNTL.macc;
|
n.macc := VM_CNTL.macc;
|
n.bytop := VM_CNTL.bytop;
|
n.bytop := VM_CNTL.bytop;
|
n.mdin := iem_mreq.din;
|
n.mdin := iem_mreq.din;
|
|
|
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
|
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
|
n.state := s_fail;
|
n.state := s_fail;
|
else
|
else
|
iem_mreq.req := '1';
|
iem_mreq.req := '1';
|
iem_mreq.we := '1';
|
iem_mreq.we := '1';
|
n.state := s_mem_mw_w;
|
n.state := s_mem_mw_w;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
|
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
|
if EM_SRES.ack_w = '1' then
|
if EM_SRES.ack_w = '1' then
|
ivm_stat.ack := '1';
|
ivm_stat.ack := '1';
|
n.state := s_idle;
|
n.state := s_idle;
|
else
|
else
|
n.state := s_mem_mw_w; -- keep waiting
|
n.state := s_mem_mw_w; -- keep waiting
|
end if;
|
end if;
|
|
|
when s_fail => -- s_fail: vmbox fatal error catcher
|
when s_fail => -- s_fail: vmbox fatal error catcher
|
ivm_stat.fail := '1';
|
ivm_stat.fail := '1';
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
when s_errrsv => -- s_errrsv: red stack violation -----
|
when s_errrsv => -- s_errrsv: red stack violation -----
|
ivm_stat.err := '1';
|
ivm_stat.err := '1';
|
ivm_stat.err_rsv := '1';
|
ivm_stat.err_rsv := '1';
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
when s_errib => -- s_errib: ibus error handler -------
|
when s_errib => -- s_errib: ibus error handler -------
|
ivm_stat.err := '1';
|
ivm_stat.err := '1';
|
ivm_stat.err_iobto := '1';
|
ivm_stat.err_iobto := '1';
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
if r.bytop='1' and r.paddr(0)='1' then
|
if r.bytop='1' and r.paddr(0)='1' then
|
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
|
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
|
end if;
|
end if;
|
|
|
if ato_go = '0' then -- handle access timeout counter
|
if ato_go = '0' then -- handle access timeout counter
|
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
|
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
|
else
|
else
|
n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down
|
n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down
|
end if;
|
end if;
|
|
|
ipaddr := (others=>'0');
|
ipaddr := (others=>'0');
|
if paddr_mmu = '1' then
|
if paddr_mmu = '1' then
|
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
|
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
|
ipaddr(21 downto 6) := PADDRH;
|
ipaddr(21 downto 6) := PADDRH;
|
if MMU_STAT.ena_22bit = '0' then
|
if MMU_STAT.ena_22bit = '0' then
|
ipaddr(21 downto 18) := (others=>'0');
|
ipaddr(21 downto 18) := (others=>'0');
|
end if;
|
end if;
|
else
|
else
|
case paddr_sel is
|
case paddr_sel is
|
when c_paddr_sel_vmaddr =>
|
when c_paddr_sel_vmaddr =>
|
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
|
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
|
when c_paddr_sel_rpaddr =>
|
when c_paddr_sel_rpaddr =>
|
ipaddr := r.paddr;
|
ipaddr := r.paddr;
|
when c_paddr_sel_cacc =>
|
when c_paddr_sel_cacc =>
|
ipaddr := CP_ADDR.addr & '0';
|
ipaddr := CP_ADDR.addr & '0';
|
if CP_ADDR.ena_22bit = '0' then
|
if CP_ADDR.ena_22bit = '0' then
|
ipaddr(21 downto 16) := (others=>'0');
|
ipaddr(21 downto 16) := (others=>'0');
|
end if;
|
end if;
|
when c_paddr_sel_ubmap =>
|
when c_paddr_sel_ubmap =>
|
ipaddr := UBMAP_ADDR_PM & '0';
|
ipaddr := UBMAP_ADDR_PM & '0';
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
if r.state = s_idle then
|
if r.state = s_idle then
|
n.paddr := ipaddr;
|
n.paddr := ipaddr;
|
end if;
|
end if;
|
|
|
iem_mreq.addr := ipaddr(21 downto 1);
|
iem_mreq.addr := ipaddr(21 downto 1);
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
UBMAP_MREQ <= iubmap_mreq;
|
UBMAP_MREQ <= iubmap_mreq;
|
|
|
IB_MREQ.req <= r.ibreq;
|
IB_MREQ.req <= r.ibreq;
|
IB_MREQ.we <= r.ibwe;
|
IB_MREQ.we <= r.ibwe;
|
IB_MREQ.be0 <= r.ibbe(0);
|
IB_MREQ.be0 <= r.ibbe(0);
|
IB_MREQ.be1 <= r.ibbe(1);
|
IB_MREQ.be1 <= r.ibbe(1);
|
IB_MREQ.dip <= r.ibdip;
|
IB_MREQ.dip <= r.ibdip;
|
IB_MREQ.cacc <= r.ibcacc;
|
IB_MREQ.cacc <= r.ibcacc;
|
IB_MREQ.racc <= r.ibracc;
|
IB_MREQ.racc <= r.ibracc;
|
IB_MREQ.addr <= r.ibaddr;
|
IB_MREQ.addr <= r.ibaddr;
|
IB_MREQ.din <= r.mdin;
|
IB_MREQ.din <= r.mdin;
|
|
|
VM_DOUT <= ivm_dout;
|
VM_DOUT <= ivm_dout;
|
VM_STAT <= ivm_stat;
|
VM_STAT <= ivm_stat;
|
MMU_CNTL <= immu_cntl;
|
MMU_CNTL <= immu_cntl;
|
|
|
EM_MREQ <= iem_mreq;
|
EM_MREQ <= iem_mreq;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
IB_MREQ_M <= IB_MREQ; -- external drive master port
|
IB_MREQ_M <= IB_MREQ; -- external drive master port
|
|
|
DM_STAT_VM.ibmreq <= IB_MREQ;
|
DM_STAT_VM.ibmreq <= IB_MREQ;
|
DM_STAT_VM.ibsres <= IB_SRES;
|
DM_STAT_VM.ibsres <= IB_SRES;
|
|
|
end syn;
|
end syn;
|
|
|