# $Id: w11a_tb_guide.txt 547 2013-12-29 13:10:07Z mueller $
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# $Id: w11a_tb_guide.txt 547 2013-12-29 13:10:07Z mueller $
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Guide to running w11a test benches
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Guide to running w11a test benches
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Table of content:
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Table of content:
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1. Unit tests benches
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1. Unit tests benches
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2. Available unit tests benches
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2. Available unit tests benches
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3. System tests benches
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3. System tests benches
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4. Available system tests benches
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4. Available system tests benches
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1. Unit tests benches -----------------------------------------------------
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1. Unit tests benches -----------------------------------------------------
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All unit test benches have the same simple structure:
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All unit test benches have the same simple structure:
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- a stimulus process reads test patterns as well as the expected
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- a stimulus process reads test patterns as well as the expected
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responses from a stimulus file
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responses from a stimulus file
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- the responses are checked in very simple cases by the stimulus process,
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- the responses are checked in very simple cases by the stimulus process,
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in general by a monitoring process
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in general by a monitoring process
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- the test bench produces a comprehensive log file. For each checked
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- the test bench produces a comprehensive log file. For each checked
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response the line contains the word "CHECK" and either an "OK" or a
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response the line contains the word "CHECK" and either an "OK" or a
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"FAIL", in the later case in general with an indication of whats wrong.
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"FAIL", in the later case in general with an indication of whats wrong.
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Other unexpected behaviour, like timeouts, will also result in a line
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Other unexpected behaviour, like timeouts, will also result in a line
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containing the word "FAIL".
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containing the word "FAIL".
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- at the end a line with the word "DONE" is printed.
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- at the end a line with the word "DONE" is printed.
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- the test bench is run like
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- the test bench is run like
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tbw [stimfile] | tee | egrep "(FAIL|DONE)"
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tbw [stimfile] | tee | egrep "(FAIL|DONE)"
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where
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where
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- 'tbw' is a small perl script setting up a symbolic link to the
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- 'tbw' is a small perl script setting up a symbolic link to the
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stimulus file, the default extracted from the file tbw.dat, if
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stimulus file, the default extracted from the file tbw.dat, if
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an optional file name is give this one will be used instead.
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an optional file name is give this one will be used instead.
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- 'tee' ensures that the full log is saved
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- 'tee' ensures that the full log is saved
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- 'egrep' filters FAIL and DONE lines, a successful run will
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- 'egrep' filters FAIL and DONE lines, a successful run will
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produce a single DONE line
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produce a single DONE line
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- Most tests can be run against
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- Most tests can be run against
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- the functional model
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- the functional model
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- gate level models at three stages
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- gate level models at three stages
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- the post-xst model (produced by netgen from ngc xst output)
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- the post-xst model (produced by netgen from ngc xst output)
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- the post-map model (produced by netgen from ncd ngdbuild output)
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- the post-map model (produced by netgen from ncd ngdbuild output)
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- the post-par model (produced by netgen from ncd par output)
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- the post-par model (produced by netgen from ncd par output)
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This is simply done using
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This is simply done using
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make _ssim for post-xst
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make _ssim for post-xst
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make _fsim for post-map
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make _fsim for post-map
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make _tsim for post-par
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make _tsim for post-par
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all the rest is handled by the build environment.
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all the rest is handled by the build environment.
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An example of a post-synthesis model is given for the w11a core test.
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An example of a post-synthesis model is given for the w11a core test.
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2. Available unit tests benches -------------------------------------------
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2. Available unit tests benches -------------------------------------------
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In the following the available tests are listed with
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In the following the available tests are listed with
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- the 'make' command to build them
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- the 'make' command to build them
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- the pipe setup to run them
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- the pipe setup to run them
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- the expected output (the run time measured on a 3 GHz system)
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- the expected output (the run time measured on a 3 GHz system)
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- serport receiver test
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- serport receiver test
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cd $RETROBASE/rtl/vlib/serport/tb
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cd $RETROBASE/rtl/vlib/serport/tb
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make tb_serport_uart_rx
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make tb_serport_uart_rx
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time tbw tb_serport_uart_rx |\
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time tbw tb_serport_uart_rx |\
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tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
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tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
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-> 1269955.0 ns 63488: DONE
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-> 1269955.0 ns 63488: DONE
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-> real 0m01.178s user 0m01.172s sys 0m00.020s
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-> real 0m01.178s user 0m01.172s sys 0m00.020s
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- serport receiver/transmitter test
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- serport receiver/transmitter test
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make tb_serport_uart_rxtx
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make tb_serport_uart_rxtx
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time tbw tb_serport_uart_rxtx |\
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time tbw tb_serport_uart_rxtx |\
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tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
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tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
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-> 52335.0 ns 2607: DONE
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-> 52335.0 ns 2607: DONE
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-> real 0m00.094s user 0m00.092s sys 0m00.008s
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-> real 0m00.094s user 0m00.092s sys 0m00.008s
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- serport autobauder test
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- serport autobauder test
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make tb_serport_autobaud
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make tb_serport_autobaud
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time tbw tb_serport_autobaud |\
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time tbw tb_serport_autobaud |\
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tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)"
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tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)"
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-> 367475.0 ns 18364: DONE
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-> 367475.0 ns 18364: DONE
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-> real 0m00.610s user 0m00.612s sys 0m00.004s
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-> real 0m00.610s user 0m00.612s sys 0m00.004s
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- rlink core test
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- rlink core test
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cd $RETROBASE/rtl/vlib/rlink/tb
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cd $RETROBASE/rtl/vlib/rlink/tb
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make tb_rlink_direct
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make tb_rlink_direct
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time tbw tb_rlink_direct |\
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time tbw tb_rlink_direct |\
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tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
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tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
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-> 147755.0 ns 7378: DONE
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-> 147755.0 ns 7378: DONE
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-> real 0m00.317s user 0m00.324s sys 0m00.028s
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-> real 0m00.317s user 0m00.324s sys 0m00.028s
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- rlink core test via serial port interface
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- rlink core test via serial port interface
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cd $RETROBASE/rtl/vlib/rlink/tb
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cd $RETROBASE/rtl/vlib/rlink/tb
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make tb_rlink_sp1c
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make tb_rlink_sp1c
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time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat |\
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time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat |\
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tee tb_rlink_sp1c_stim2_dsim.log | egrep "(FAIL|DONE)"
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tee tb_rlink_sp1c_stim2_dsim.log | egrep "(FAIL|DONE)"
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-> 24695.0 ns 1225: DONE
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-> 24695.0 ns 1225: DONE
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-> real 0m0.133s user 0m0.104s sys 0m0.008s
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-> real 0m0.133s user 0m0.104s sys 0m0.008s
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time tbw tb_rlink_sp1c tb_rlink_stim.dat |\
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time tbw tb_rlink_sp1c tb_rlink_stim.dat |\
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tee tb_rlink_sp1c_dsim.log | egrep "(FAIL|DONE)"
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tee tb_rlink_sp1c_dsim.log | egrep "(FAIL|DONE)"
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-> 551935.0 ns 27587: DONE
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-> 551935.0 ns 27587: DONE
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-> real 0m01.714s user 0m01.704s sys 0m00.044s
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-> real 0m01.714s user 0m01.704s sys 0m00.044s
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- w11a core test (using behavioural model)
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- w11a core test (using behavioural model)
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cd $RETROBASE/rtl/w11a/tb
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cd $RETROBASE/rtl/w11a/tb
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make tb_pdp11core
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make tb_pdp11core
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time tbw tb_pdp11core |\
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time tbw tb_pdp11core |\
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tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
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tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
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-> 1220255.0 ns 61003: DONE
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-> 1220255.0 ns 61003: DONE
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-> real 0m10.736s user 0m10.713s sys 0m00.060s
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-> real 0m10.736s user 0m10.713s sys 0m00.060s
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- w11a core test (using post-synthesis model)
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- w11a core test (using post-synthesis model)
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make ghdl_tmp_clean tb_pdp11core_ssim
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make ghdl_tmp_clean tb_pdp11core_ssim
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time tbw tb_pdp11core_ssim |\
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time tbw tb_pdp11core_ssim |\
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tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
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tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
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-> 1220255.0 ns 61003: DONE
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-> 1220255.0 ns 61003: DONE
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-> real 1m09.738s user 1m09.588s sys 0m00.096s
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-> real 1m09.738s user 1m09.588s sys 0m00.096s
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- s3board sram controller test
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- s3board sram controller test
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cd $RETROBASE/rtl/bplib/s3board/tb
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cd $RETROBASE/rtl/bplib/s3board/tb
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make tb_s3_sram_memctl
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make tb_s3_sram_memctl
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time tbw tb_s3_sram_memctl |\
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time tbw tb_s3_sram_memctl |\
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tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
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tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
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-> 5015.0 ns 241: DONE
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-> 5015.0 ns 241: DONE
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-> real 0m00.113s user 0m00.068s sys 0m00.016s
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-> real 0m00.113s user 0m00.068s sys 0m00.016s
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- nexys2/nexys3 cram controller test
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- nexys2/nexys3 cram controller test
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cd $RETROBASE/rtl/bplib/nxcramlib/tb
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cd $RETROBASE/rtl/bplib/nxcramlib/tb
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make tb_nx_cram_memctl_as
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make tb_nx_cram_memctl_as
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time tbw tb_nx_cram_memctl_as |\
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time tbw tb_nx_cram_memctl_as |\
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tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
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tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
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-> 24272.5 ns 1204: DONE
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-> 24272.5 ns 1204: DONE
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-> real 0m00.343s user 0m00.248s sys 0m00.100s
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-> real 0m00.343s user 0m00.248s sys 0m00.100s
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3. System tests benches ---------------------------------------------------
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3. System tests benches ---------------------------------------------------
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The system tests allow to verify to verify a full system design.
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The system tests allow to verify to verify a full system design.
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In this case vhdl test bench code contains
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In this case vhdl test bench code contains
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- (simple) models of the memories used on the FPGA boards
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- (simple) models of the memories used on the FPGA boards
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- drivers for the rlink connection (currently just serialport)
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- drivers for the rlink connection (currently just serialport)
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- code to interface the rlink data stream to a UNIX 'named pipe',
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- code to interface the rlink data stream to a UNIX 'named pipe',
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implemented with a C routine which is called via VHPI from VHDL.
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implemented with a C routine which is called via VHPI from VHDL.
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This way the whole ghdl simulation can be controlled via a di-directional
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This way the whole ghdl simulation can be controlled via a di-directional
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byte stream.
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byte stream.
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The rlink backend process can connect either via a named pipe to a ghdl
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The rlink backend process can connect either via a named pipe to a ghdl
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simulation, or via a serial port to a FPGA board. This way the same tests
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simulation, or via a serial port to a FPGA board. This way the same tests
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can be executed in simulation and on real hardware.
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can be executed in simulation and on real hardware.
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4. Available system tests benches -----------------------------------------
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4. Available system tests benches -----------------------------------------
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4a. serport tester ---------------------------------------------------
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4a. serport tester ---------------------------------------------------
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The sys_tst_serloop design is a test target for validating the serial
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The sys_tst_serloop design is a test target for validating the serial
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link UART stack. Send and receive throughput as well as loop-back tests
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link UART stack. Send and receive throughput as well as loop-back tests
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are supported
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are supported
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- sys_tst_serloop_s3 test bench
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- sys_tst_serloop_s3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
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cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
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make tb_tst_serloop_s3
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make tb_tst_serloop_s3
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time tbw tb_tst_serloop_s3 |\
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time tbw tb_tst_serloop_s3 |\
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tee tb_tst_serloop_s3_dsim.log | egrep "(FAIL|DONE)"
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tee tb_tst_serloop_s3_dsim.log | egrep "(FAIL|DONE)"
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-> 301353.3 ns 18068: DONE
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-> 301353.3 ns 18068: DONE
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-> real 0m1.422s user 0m1.372s sys 0m0.024s
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-> real 0m1.422s user 0m1.372s sys 0m0.024s
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- sys_tst_serloop_n2 test bench
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- sys_tst_serloop_n2 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
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make tb_tst_serloop1_n2
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make tb_tst_serloop1_n2
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time tbw tb_tst_serloop1_n2 |\
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time tbw tb_tst_serloop1_n2 |\
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tee tb_tst_serloop1_n2_dsim.log | egrep "(FAIL|DONE)"
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tee tb_tst_serloop1_n2_dsim.log | egrep "(FAIL|DONE)"
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-> 361560.0 ns 18068: DONE
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-> 361560.0 ns 18068: DONE
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-> real 0m1.341s user 0m1.340s sys 0m0.016s
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-> real 0m1.341s user 0m1.340s sys 0m0.016s
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make tb_tst_serloop2_n2
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make tb_tst_serloop2_n2
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time tbw tb_tst_serloop2_n2 |\
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time tbw tb_tst_serloop2_n2 |\
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tee tb_tst_serloop2_n2_dsim.log | egrep "(FAIL|DONE)"
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tee tb_tst_serloop2_n2_dsim.log | egrep "(FAIL|DONE)"
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-> 304353.3 ns 18248: DONE
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-> 304353.3 ns 18248: DONE
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-> real 0m1.933s user 0m1.924s sys 0m0.024s
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-> real 0m1.933s user 0m1.924s sys 0m0.024s
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- sys_tst_serloop_n3 test bench
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- sys_tst_serloop_n3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
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make tb_tst_serloop1_n3
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make tb_tst_serloop1_n3
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time tbw tb_tst_serloop1_n3 |\
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time tbw tb_tst_serloop1_n3 |\
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tee tb_tst_serloop1_n3_dsim.log | egrep "(FAIL|DONE)"
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tee tb_tst_serloop1_n3_dsim.log | egrep "(FAIL|DONE)"
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-> 361560.0 ns 18068: DONE
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-> 361560.0 ns 18068: DONE
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-> real 0m1.371s user 0m1.372s sys 0m0.016s
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-> real 0m1.371s user 0m1.372s sys 0m0.016s
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4b. rlink tester -----------------------------------------------------
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4b. rlink tester -----------------------------------------------------
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The sys_tst_rlink design is a test target for validating the rlink
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The sys_tst_rlink design is a test target for validating the rlink
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and rbus functionality at all levels.
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and rbus functionality at all levels.
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- sys_tst_rlink_s3 test bench
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- sys_tst_rlink_s3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
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make tb_tst_rlink_s3
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make tb_tst_rlink_s3
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time ti_rri --run="tbw tb_tst_rlink_s3" --fifo --logl=3 -- \
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time ti_rri --run="tbw tb_tst_rlink_s3" --fifo --logl=3 -- \
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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tee tb_tst_rlink_s3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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tee tb_tst_rlink_s3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 960540.0 ns 48017: DONE
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-> 960540.0 ns 48017: DONE
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-> real 0m4.470s
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-> real 0m4.470s
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- sys_tst_rlink_n2 test bench
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- sys_tst_rlink_n2 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
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make tb_tst_rlink_n2
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make tb_tst_rlink_n2
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time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
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time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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tee tb_tst_rlink_n2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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tee tb_tst_rlink_n2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 960560.0 ns 48017: DONE
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-> 960560.0 ns 48017: DONE
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-> real 0m4.717s
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-> real 0m4.717s
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- sys_tst_rlink_n3 test bench
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- sys_tst_rlink_n3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
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make tb_tst_rlink_n3
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make tb_tst_rlink_n3
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time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \
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time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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tee tb_tst_rlink_n3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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tee tb_tst_rlink_n3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 480380.0 ns 48017: DONE
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-> 480380.0 ns 48017: DONE
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-> real 0m4.860s
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-> real 0m4.860s
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4c. w11a systems -----------------------------------------------------
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4c. w11a systems -----------------------------------------------------
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The stimulus file used in the w11a core test can be executed in the
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The stimulus file used in the w11a core test can be executed in the
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full system context (both s3board and nexys2 versions) with the
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full system context (both s3board and nexys2 versions) with the
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following commands. Note that the cycle number printed in the DONE
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following commands. Note that the cycle number printed in the DONE
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line can now vary slightly because the response time of the rlink
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line can now vary slightly because the response time of the rlink
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backend process and thus scheduling of backend vs. ghdl process
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backend process and thus scheduling of backend vs. ghdl process
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can affect the result.
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can affect the result.
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- sys_w11a_s3 test bench
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- sys_w11a_s3 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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make tb_w11a_s3
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make tb_w11a_s3
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time ti_rri --pack=rw11 --run="tbw tb_w11a_s3" --fifo --logl=3 -- \
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time ti_rri --pack=rw11 --run="tbw tb_w11a_s3" --fifo --logl=3 -- \
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"rw11::setup_cpu" \
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"rw11::setup_cpu" \
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
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tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 10225140.0 ns 511247: DONE
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-> 10225140.0 ns 511247: DONE
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-> real 0m52.105s user 0m51.871s sys 0m0.376s
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-> real 0m52.105s user 0m51.871s sys 0m0.376s
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- sys_w11a_n2 test bench
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- sys_w11a_n2 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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make tb_w11a_n2
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make tb_w11a_n2
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time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
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time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
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"rw11::setup_cpu" \
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"rw11::setup_cpu" \
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
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tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 10278380.0 ns 513908: DONE
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-> 10278380.0 ns 513908: DONE
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-> real 1m2.951s user 1m2.628s sys 0m0.532s
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-> real 1m2.951s user 1m2.628s sys 0m0.532s
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|
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- sys_w11a_n3 test bench
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- sys_w11a_n3 test bench
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|
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
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make tb_w11a_n3
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make tb_w11a_n3
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time ti_rri --pack=rw11 --run="tbw tb_w11a_n3" --fifo --logl=3 -- \
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time ti_rri --pack=rw11 --run="tbw tb_w11a_n3" --fifo --logl=3 -- \
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"rw11::setup_cpu" \
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"rw11::setup_cpu" \
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
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tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 5167410.0 ns 516720: DONE
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-> 5167410.0 ns 516720: DONE
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-> real 1m5.322s user 1m5.072s sys 0m0.500s
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-> real 1m5.322s user 1m5.072s sys 0m0.500s
|
|
|
A new, modular w11a test bench is under construction. So far it is very
|
A new, modular w11a test bench is under construction. So far it is very
|
incomplete. This very preliminary version can be executed with
|
incomplete. This very preliminary version can be executed with
|
|
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- sys_w11a_n2 test bench
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- sys_w11a_n2 test bench
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|
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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make tb_w11a_n2
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make tb_w11a_n2
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time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
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time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
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"rw11::setup_cpu" "rw11::tbench @w11a_all.dat" | \
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"rw11::setup_cpu" "rw11::tbench @w11a_all.dat" | \
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tee w11a_tbench_dsim.log | egrep "(-[EFW]:|FAIL|PASS|DONE)"
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tee w11a_tbench_dsim.log | egrep "(-[EFW]:|FAIL|PASS|DONE)"
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-> 904180.0 ns 45198: DONE
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-> 904180.0 ns 45198: DONE
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-> real 0m5.539s user 0m5.748s sys 0m0.204s
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-> real 0m5.539s user 0m5.748s sys 0m0.204s
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