-- $Id: nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
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-- $Id: nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: nx_cram_memctl_as - syn
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-- Module Name: nx_cram_memctl_as - syn
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-- Description: nexys2/3: CRAM driver - async and page mode
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-- Description: nexys2/3: CRAM driver - async and page mode
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--
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--
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-- Dependencies: vlib/xlib/iob_reg_o
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-- Dependencies: vlib/xlib/iob_reg_o
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-- vlib/xlib/iob_reg_o_gen
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-- vlib/xlib/iob_reg_o_gen
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-- vlib/xlib/iob_reg_io_gen
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-- vlib/xlib/iob_reg_io_gen
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-- Test bench: tb/tb_nx_cram_memctl_as
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-- Test bench: tb/tb_nx_cram_memctl_as
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-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
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-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4, 13.1; ghdl 0.26
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-- Tool versions: xst 11.4, 13.1; ghdl 0.26
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
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-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
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-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
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-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
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-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
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-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
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-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
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-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
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-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
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-- 2011-11-19 427 1.0.5 now numeric_std clean
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-- 2011-11-19 427 1.0.5 now numeric_std clean
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-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
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-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
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-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
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-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
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-- cycle;
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-- cycle;
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-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
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-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
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-- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1
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-- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1
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-- 2010-05-23 293 1.0 Initial version
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-- 2010-05-23 293 1.0 Initial version
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--
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--
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-- Notes:
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-- Notes:
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-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
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-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
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-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
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-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
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-- short READ1 delay works in sim, but not on fpga where the data od the
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-- short READ1 delay works in sim, but not on fpga where the data od the
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-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
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-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
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-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
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-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
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-- 40ns or 50 ns, only T_apa 60 ns fails !
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-- 40ns or 50 ns, only T_apa 60 ns fails !
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-- Unclear what is wrong here, the timing of the memory model seems ok.
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-- Unclear what is wrong here, the timing of the memory model seems ok.
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-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
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-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
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-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
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-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
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-- transition simultaneously. The FPGA will go high-Z quickly, the memory
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-- transition simultaneously. The FPGA will go high-Z quickly, the memory
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-- low-Z delay by the IOB and internal memory delays. No clash.
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-- low-Z delay by the IOB and internal memory delays. No clash.
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-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
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-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
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-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
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-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
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-- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
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-- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
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-- Again no clash due to the 1 cycle delay.
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-- Again no clash due to the 1 cycle delay.
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--
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--
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-- Nominal timings:
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-- Nominal timings:
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-- READ0/1 = N_rd_cycle - 2
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-- READ0/1 = N_rd_cycle - 2
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-- WRITE = N_wr_cycle - 1
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-- WRITE = N_wr_cycle - 1
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--
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--
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-- from notes_nexys2.txt (Rev 339):
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-- from notes_nexys2.txt (Rev 339):
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-- clksys RD WR < use for > Test case
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-- clksys RD WR < use for > Test case
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-- MHz div mul
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-- MHz div mul
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-- <51.20 2 3 <-- 50 50 1 1
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-- <51.20 2 3 <-- 50 50 1 1
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-- 51.20- 54.80 3 3 <-- 52,54 54 25 27
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-- 51.20- 54.80 3 3 <-- 52,54 54 25 27
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-- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32
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-- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32
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-- 64.10- 68.50 4 4 <-- 65 65 10 13
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-- 64.10- 68.50 4 4 <-- 65 65 10 13
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-- 68.50- 76.92 4 5 <-- 70,75 75 2 3
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-- 68.50- 76.92 4 5 <-- 70,75 75 2 3
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-- 76.92- 82.19 5 5 <-- 80 80 5 8
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-- 76.92- 82.19 5 5 <-- 80 80 5 8
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-- 82.19- 89.74 5 6 <-- 85 85 10 17
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-- 82.19- 89.74 5 6 <-- 85 85 10 17
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-- 89.74- 95.89 6 6 <-- 90,95 95 10 19
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-- 89.74- 95.89 6 6 <-- 90,95 95 10 19
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-- 95.89-102.56 6 7 <-- 100 100 1 2
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-- 95.89-102.56 6 7 <-- 100 100 1 2
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--
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--
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-- Timing of some signals:
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-- Timing of some signals:
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--
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--
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-- single read request:
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-- single read request:
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--
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--
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-- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1|
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-- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1|
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-- 0 20 40 60 80 100 120
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-- 0 20 40 60 80 100 120
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-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
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-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
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--
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--
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-- REQ _______|^^^^^|_____________________________________________
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-- REQ _______|^^^^^|_____________________________________________
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-- WE ___________________________________________________________
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-- WE ___________________________________________________________
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--
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--
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-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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-- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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-- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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--
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--
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-- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h
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-- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h
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-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________
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-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________
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-- ACK_R ___________________________________________________________|^^^^^^^|_
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-- ACK_R ___________________________________________________________|^^^^^^^|_
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--
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--
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-- single write request:
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-- single write request:
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--
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--
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-- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle |
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-- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle |
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-- 0 20 40 60 80 100 120
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-- 0 20 40 60 80 100 120
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-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
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-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
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--
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--
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-- REQ _______|^^^^^|______________________________________
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-- REQ _______|^^^^^|______________________________________
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-- WE _______|^^^^^|______________________________________
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-- WE _______|^^^^^|______________________________________
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--
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--
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-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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-- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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-- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
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-- IOB_OE ____________________________________________________
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-- IOB_OE ____________________________________________________
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-- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____
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-- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____
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--
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--
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-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
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-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
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-- ACK_W __________________________________________|^^^^^^^|_
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-- ACK_W __________________________________________|^^^^^^^|_
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.xlib.all;
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|
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entity nx_cram_memctl_as is -- CRAM driver (async+page mode)
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entity nx_cram_memctl_as is -- CRAM driver (async+page mode)
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generic (
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generic (
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READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
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READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
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READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
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READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
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WRITEDELAY : positive := 3); -- write delay in clock cycles
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WRITEDELAY : positive := 3); -- write delay in clock cycles
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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REQ : in slbit; -- request
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REQ : in slbit; -- request
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WE : in slbit; -- write enable
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WE : in slbit; -- write enable
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BUSY : out slbit; -- controller busy
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BUSY : out slbit; -- controller busy
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ACK_R : out slbit; -- acknowledge read
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ACK_R : out slbit; -- acknowledge read
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ACK_W : out slbit; -- acknowledge write
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ACK_W : out slbit; -- acknowledge write
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ACT_R : out slbit; -- signal active read
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ACT_R : out slbit; -- signal active read
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ACT_W : out slbit; -- signal active write
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ACT_W : out slbit; -- signal active write
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ADDR : in slv22; -- address (32 bit word address)
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ADDR : in slv22; -- address (32 bit word address)
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BE : in slv4; -- byte enable
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BE : in slv4; -- byte enable
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DI : in slv32; -- data in (memory view)
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DI : in slv32; -- data in (memory view)
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DO : out slv32; -- data out (memory view)
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DO : out slv32; -- data out (memory view)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_MEM_ADDR : out slv23; -- cram: address lines
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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);
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);
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end nx_cram_memctl_as;
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end nx_cram_memctl_as;
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architecture syn of nx_cram_memctl_as is
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architecture syn of nx_cram_memctl_as is
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|
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: wait for req
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s_idle, -- s_idle: wait for req
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s_rdinit, -- s_rdinit: read init cycle
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s_rdinit, -- s_rdinit: read init cycle
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s_rdwait0, -- s_rdwait0: read wait low word
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s_rdwait0, -- s_rdwait0: read wait low word
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s_rdget0, -- s_rdget0: read get low word
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s_rdget0, -- s_rdget0: read get low word
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s_rdwait1, -- s_rdwait1: read wait high word
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s_rdwait1, -- s_rdwait1: read wait high word
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s_rdget1, -- s_rdget1: read get high word
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s_rdget1, -- s_rdget1: read get high word
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s_wrinit, -- s_wrinit: write init cycle
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s_wrinit, -- s_wrinit: write init cycle
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s_wrwait0, -- s_rdwait0: write wait 1st word
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s_wrwait0, -- s_rdwait0: write wait 1st word
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s_wrput0, -- s_rdput0: write put 1st word
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s_wrput0, -- s_rdput0: write put 1st word
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s_wrini1, -- s_wrini1: write init 2nd word
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s_wrini1, -- s_wrini1: write init 2nd word
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s_wrwait1, -- s_wrwait1: write wait 2nd word
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s_wrwait1, -- s_wrwait1: write wait 2nd word
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s_wrput1 -- s_wrput1: write put 2nd word
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s_wrput1 -- s_wrput1: write put 2nd word
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);
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);
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|
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type regs_type is record
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type regs_type is record
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state : state_type; -- state
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state : state_type; -- state
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ackr : slbit; -- signal ack_r
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ackr : slbit; -- signal ack_r
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addr0 : slbit; -- current addr0
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addr0 : slbit; -- current addr0
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be2nd : slv2; -- be's of 2nd write cycle
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be2nd : slv2; -- be's of 2nd write cycle
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cntdly : slv3; -- wait delay counter
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cntdly : slv3; -- wait delay counter
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cntce : slv7; -- ce counter
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cntce : slv7; -- ce counter
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fidle : slbit; -- force idle flag
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fidle : slbit; -- force idle flag
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memdo0 : slv16; -- mem data out, low word
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memdo0 : slv16; -- mem data out, low word
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memdi : slv32; -- mem data in
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memdi : slv32; -- mem data in
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end record regs_type;
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end record regs_type;
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|
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle, --
|
s_idle, --
|
'0', -- ackr
|
'0', -- ackr
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'0', -- addr0
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'0', -- addr0
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"00", -- be2nd
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"00", -- be2nd
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(others=>'0'), -- cntdly
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(others=>'0'), -- cntdly
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(others=>'0'), -- cntce
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(others=>'0'), -- cntce
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'0', -- fidle
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'0', -- fidle
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(others=>'0'), -- memdo0
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(others=>'0'), -- memdo0
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(others=>'0') -- memdi
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(others=>'0') -- memdi
|
);
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);
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|
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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|
|
signal CLK_180 : slbit := '0';
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signal CLK_180 : slbit := '0';
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signal MEM_CE_N : slbit := '1';
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signal MEM_CE_N : slbit := '1';
|
signal MEM_BE_N : slv2 := "11";
|
signal MEM_BE_N : slv2 := "11";
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signal MEM_WE_N : slbit := '1';
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signal MEM_WE_N : slbit := '1';
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signal MEM_OE_N : slbit := '1';
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signal MEM_OE_N : slbit := '1';
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signal BE_CE : slbit := '0';
|
signal BE_CE : slbit := '0';
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signal ADDRH_CE : slbit := '0';
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signal ADDRH_CE : slbit := '0';
|
signal ADDR0_CE : slbit := '0';
|
signal ADDR0_CE : slbit := '0';
|
signal ADDR0 : slbit := '0';
|
signal ADDR0 : slbit := '0';
|
signal DATA_CEI : slbit := '0';
|
signal DATA_CEI : slbit := '0';
|
signal DATA_CEO : slbit := '0';
|
signal DATA_CEO : slbit := '0';
|
signal DATA_OE : slbit := '0';
|
signal DATA_OE : slbit := '0';
|
signal MEM_DO : slv16 := (others=>'0');
|
signal MEM_DO : slv16 := (others=>'0');
|
signal MEM_DI : slv16 := (others=>'0');
|
signal MEM_DI : slv16 := (others=>'0');
|
|
|
-- these attributes aren't accepted by ghdl 0.26
|
-- these attributes aren't accepted by ghdl 0.26
|
-- attribute s : string;
|
-- attribute s : string;
|
-- attribute s of I_MEM_WAIT : signal is "true";
|
-- attribute s of I_MEM_WAIT : signal is "true";
|
|
|
begin
|
begin
|
|
|
assert READ0DELAY<=2**R_REGS.cntdly'length and
|
assert READ0DELAY<=2**R_REGS.cntdly'length and
|
READ1DELAY<=2**R_REGS.cntdly'length and
|
READ1DELAY<=2**R_REGS.cntdly'length and
|
WRITEDELAY<=2**R_REGS.cntdly'length
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WRITEDELAY<=2**R_REGS.cntdly'length
|
report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)"
|
report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)"
|
severity failure;
|
severity failure;
|
|
|
CLK_180 <= not CLK;
|
CLK_180 <= not CLK;
|
|
|
IOB_MEM_CE : iob_reg_o
|
IOB_MEM_CE : iob_reg_o
|
generic map (
|
generic map (
|
INIT => '1')
|
INIT => '1')
|
port map (
|
port map (
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CLK => CLK,
|
CLK => CLK,
|
CE => '1',
|
CE => '1',
|
DO => MEM_CE_N,
|
DO => MEM_CE_N,
|
PAD => O_MEM_CE_N
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PAD => O_MEM_CE_N
|
);
|
);
|
|
|
IOB_MEM_BE : iob_reg_o_gen
|
IOB_MEM_BE : iob_reg_o_gen
|
generic map (
|
generic map (
|
DWIDTH => 2,
|
DWIDTH => 2,
|
INIT => '1')
|
INIT => '1')
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CE => BE_CE,
|
CE => BE_CE,
|
DO => MEM_BE_N,
|
DO => MEM_BE_N,
|
PAD => O_MEM_BE_N
|
PAD => O_MEM_BE_N
|
);
|
);
|
|
|
IOB_MEM_WE : iob_reg_o
|
IOB_MEM_WE : iob_reg_o
|
generic map (
|
generic map (
|
INIT => '1')
|
INIT => '1')
|
port map (
|
port map (
|
CLK => CLK_180,
|
CLK => CLK_180,
|
CE => '1',
|
CE => '1',
|
DO => MEM_WE_N,
|
DO => MEM_WE_N,
|
PAD => O_MEM_WE_N
|
PAD => O_MEM_WE_N
|
);
|
);
|
|
|
IOB_MEM_OE : iob_reg_o
|
IOB_MEM_OE : iob_reg_o
|
generic map (
|
generic map (
|
INIT => '1')
|
INIT => '1')
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CE => '1',
|
CE => '1',
|
DO => MEM_OE_N,
|
DO => MEM_OE_N,
|
PAD => O_MEM_OE_N
|
PAD => O_MEM_OE_N
|
);
|
);
|
|
|
IOB_MEM_ADDRH : iob_reg_o_gen
|
IOB_MEM_ADDRH : iob_reg_o_gen
|
generic map (
|
generic map (
|
DWIDTH => 22)
|
DWIDTH => 22)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CE => ADDRH_CE,
|
CE => ADDRH_CE,
|
DO => ADDR,
|
DO => ADDR,
|
PAD => O_MEM_ADDR(22 downto 1)
|
PAD => O_MEM_ADDR(22 downto 1)
|
);
|
);
|
|
|
IOB_MEM_ADDR0 : iob_reg_o
|
IOB_MEM_ADDR0 : iob_reg_o
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CE => ADDR0_CE,
|
CE => ADDR0_CE,
|
DO => ADDR0,
|
DO => ADDR0,
|
PAD => O_MEM_ADDR(0)
|
PAD => O_MEM_ADDR(0)
|
);
|
);
|
|
|
IOB_MEM_DATA : iob_reg_io_gen
|
IOB_MEM_DATA : iob_reg_io_gen
|
generic map (
|
generic map (
|
DWIDTH => 16,
|
DWIDTH => 16,
|
PULL => "KEEP")
|
PULL => "KEEP")
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CEI => DATA_CEI,
|
CEI => DATA_CEI,
|
CEO => DATA_CEO,
|
CEO => DATA_CEO,
|
OE => DATA_OE,
|
OE => DATA_OE,
|
DI => MEM_DO,
|
DI => MEM_DO,
|
DO => MEM_DI,
|
DO => MEM_DI,
|
PAD => IO_MEM_DATA
|
PAD => IO_MEM_DATA
|
);
|
);
|
|
|
O_MEM_ADV_N <= '0';
|
O_MEM_ADV_N <= '0';
|
O_MEM_CLK <= '0';
|
O_MEM_CLK <= '0';
|
O_MEM_CRE <= '0';
|
O_MEM_CRE <= '0';
|
|
|
proc_regs: process (CLK)
|
proc_regs: process (CLK)
|
begin
|
begin
|
|
|
if rising_edge(CLK) then
|
if rising_edge(CLK) then
|
if RESET = '1' then
|
if RESET = '1' then
|
R_REGS <= regs_init;
|
R_REGS <= regs_init;
|
else
|
else
|
R_REGS <= N_REGS;
|
R_REGS <= N_REGS;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end process proc_regs;
|
end process proc_regs;
|
|
|
proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO)
|
proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO)
|
|
|
variable r : regs_type := regs_init;
|
variable r : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
variable ibusy : slbit := '0';
|
variable ibusy : slbit := '0';
|
variable iackw : slbit := '0';
|
variable iackw : slbit := '0';
|
variable iactr : slbit := '0';
|
variable iactr : slbit := '0';
|
variable iactw : slbit := '0';
|
variable iactw : slbit := '0';
|
variable imem_ce : slbit := '0';
|
variable imem_ce : slbit := '0';
|
variable imem_be : slv2 := "00";
|
variable imem_be : slv2 := "00";
|
variable imem_we : slbit := '0';
|
variable imem_we : slbit := '0';
|
variable imem_oe : slbit := '0';
|
variable imem_oe : slbit := '0';
|
variable ibe_ce : slbit := '0';
|
variable ibe_ce : slbit := '0';
|
variable iaddrh_ce : slbit := '0';
|
variable iaddrh_ce : slbit := '0';
|
variable iaddr0_ce : slbit := '0';
|
variable iaddr0_ce : slbit := '0';
|
variable iaddr0 : slbit := '0';
|
variable iaddr0 : slbit := '0';
|
variable idata_cei : slbit := '0';
|
variable idata_cei : slbit := '0';
|
variable idata_ceo : slbit := '0';
|
variable idata_ceo : slbit := '0';
|
variable idata_oe : slbit := '0';
|
variable idata_oe : slbit := '0';
|
|
|
procedure do_dispatch(nstate : out state_type;
|
procedure do_dispatch(nstate : out state_type;
|
iaddrh_ce : out slbit;
|
iaddrh_ce : out slbit;
|
iaddr0_ce : out slbit;
|
iaddr0_ce : out slbit;
|
iaddr0 : out slbit;
|
iaddr0 : out slbit;
|
ibe_ce : out slbit;
|
ibe_ce : out slbit;
|
imem_be : out slv2;
|
imem_be : out slv2;
|
imem_ce : out slbit;
|
imem_ce : out slbit;
|
imem_oe : out slbit;
|
imem_oe : out slbit;
|
nbe2nd : out slv2) is
|
nbe2nd : out slv2) is
|
begin
|
begin
|
iaddrh_ce := '1'; -- latch address (high part)
|
iaddrh_ce := '1'; -- latch address (high part)
|
iaddr0_ce := '1'; -- latch address 0 bit
|
iaddr0_ce := '1'; -- latch address 0 bit
|
ibe_ce := '1'; -- latch be's
|
ibe_ce := '1'; -- latch be's
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
nbe2nd := "00"; -- assume no 2nd write cycle
|
nbe2nd := "00"; -- assume no 2nd write cycle
|
if WE = '0' then -- if READ requested
|
if WE = '0' then -- if READ requested
|
iaddr0 := '0'; -- go first for low word
|
iaddr0 := '0'; -- go first for low word
|
imem_be := "11"; -- on read always on
|
imem_be := "11"; -- on read always on
|
imem_oe := '1'; -- oe CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
nstate := s_rdinit; -- next: read init part
|
nstate := s_rdinit; -- next: read init part
|
else -- if WRITE requested
|
else -- if WRITE requested
|
if BE(1 downto 0) /= "00" then -- low word write
|
if BE(1 downto 0) /= "00" then -- low word write
|
iaddr0 := '0'; -- access word 0
|
iaddr0 := '0'; -- access word 0
|
imem_be := BE(1 downto 0); -- set be's for 1st cycle
|
imem_be := BE(1 downto 0); -- set be's for 1st cycle
|
nbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle
|
nbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle
|
else -- high word write
|
else -- high word write
|
iaddr0 := '1'; -- access word 1
|
iaddr0 := '1'; -- access word 1
|
imem_be := BE(3 downto 2); -- set be's for 1st cycle
|
imem_be := BE(3 downto 2); -- set be's for 1st cycle
|
end if;
|
end if;
|
nstate := s_wrinit; -- next: write init part
|
nstate := s_wrinit; -- next: write init part
|
end if;
|
end if;
|
end procedure do_dispatch;
|
end procedure do_dispatch;
|
|
|
begin
|
begin
|
|
|
r := R_REGS;
|
r := R_REGS;
|
n := R_REGS;
|
n := R_REGS;
|
n.ackr := '0';
|
n.ackr := '0';
|
|
|
ibusy := '0';
|
ibusy := '0';
|
iackw := '0';
|
iackw := '0';
|
iactr := '0';
|
iactr := '0';
|
iactw := '0';
|
iactw := '0';
|
|
|
imem_ce := '0';
|
imem_ce := '0';
|
imem_be := "11";
|
imem_be := "11";
|
imem_we := '0';
|
imem_we := '0';
|
imem_oe := '0';
|
imem_oe := '0';
|
ibe_ce := '0';
|
ibe_ce := '0';
|
iaddrh_ce := '0';
|
iaddrh_ce := '0';
|
iaddr0_ce := '0';
|
iaddr0_ce := '0';
|
iaddr0 := '0';
|
iaddr0 := '0';
|
idata_cei := '0';
|
idata_cei := '0';
|
idata_ceo := '0';
|
idata_ceo := '0';
|
idata_oe := '0';
|
idata_oe := '0';
|
|
|
if unsigned(r.cntdly) /= 0 then
|
if unsigned(r.cntdly) /= 0 then
|
n.cntdly := slv(unsigned(r.cntdly) - 1);
|
n.cntdly := slv(unsigned(r.cntdly) - 1);
|
end if;
|
end if;
|
|
|
case r.state is
|
case r.state is
|
when s_idle => -- s_idle: wait for req
|
when s_idle => -- s_idle: wait for req
|
if REQ = '1' then -- if IO requested
|
if REQ = '1' then -- if IO requested
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
end if;
|
end if;
|
|
|
when s_rdinit => -- s_rdinit: read init cycle
|
when s_rdinit => -- s_rdinit: read init cycle
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactr := '1'; -- signal mem read
|
iactr := '1'; -- signal mem read
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
|
n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
|
n.state := s_rdwait0; -- next: wait
|
n.state := s_rdwait0; -- next: wait
|
|
|
when s_rdwait0 => -- s_rdwait0: read wait low word
|
when s_rdwait0 => -- s_rdwait0: read wait low word
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactr := '1'; -- signal mem read
|
iactr := '1'; -- signal mem read
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
n.state := s_rdget0; -- next: get low word
|
n.state := s_rdget0; -- next: get low word
|
end if;
|
end if;
|
|
|
when s_rdget0 => -- s_rdget0: read get low word
|
when s_rdget0 => -- s_rdget0: read get low word
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactr := '1'; -- signal mem read
|
iactr := '1'; -- signal mem read
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
idata_cei := '1'; -- latch input data
|
idata_cei := '1'; -- latch input data
|
iaddr0_ce := '1'; -- latch address 0 bit
|
iaddr0_ce := '1'; -- latch address 0 bit
|
iaddr0 := '1'; -- now go for high word
|
iaddr0 := '1'; -- now go for high word
|
n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
|
n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
|
n.state := s_rdwait1; -- next: wait high word
|
n.state := s_rdwait1; -- next: wait high word
|
|
|
when s_rdwait1 => -- s_rdwait1: read wait high word
|
when s_rdwait1 => -- s_rdwait1: read wait high word
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactr := '1'; -- signal mem read
|
iactr := '1'; -- signal mem read
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
imem_oe := '1'; -- oe CRAM next cycle
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
n.state := s_rdget1; -- next: get low word
|
n.state := s_rdget1; -- next: get low word
|
end if; --
|
end if; --
|
|
|
when s_rdget1 => -- s_rdget1: read get high word
|
when s_rdget1 => -- s_rdget1: read get high word
|
iactr := '1'; -- signal mem read
|
iactr := '1'; -- signal mem read
|
n.memdo0:= MEM_DO; -- save low word data
|
n.memdo0:= MEM_DO; -- save low word data
|
idata_cei := '1'; -- latch input data
|
idata_cei := '1'; -- latch input data
|
n.ackr := '1'; -- ACK_R next cycle
|
n.ackr := '1'; -- ACK_R next cycle
|
n.state := s_idle; -- next: wait next request
|
n.state := s_idle; -- next: wait next request
|
if r.fidle = '1' then -- forced idle cycle
|
if r.fidle = '1' then -- forced idle cycle
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
else
|
else
|
if REQ = '1' then -- if IO requested
|
if REQ = '1' then -- if IO requested
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_wrinit => -- s_wrinit: write init cycle
|
when s_wrinit => -- s_wrinit: write init cycle
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
iackw := '1'; -- signal write done (all latched)
|
iackw := '1'; -- signal write done (all latched)
|
idata_ceo:= '1'; -- latch output data
|
idata_ceo:= '1'; -- latch output data
|
idata_oe := '1'; -- oe FPGA next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_we := '1'; -- we CRAM in half cycle
|
imem_we := '1'; -- we CRAM in half cycle
|
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
|
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
|
n.state := s_wrwait0; -- next: wait
|
n.state := s_wrwait0; -- next: wait
|
|
|
when s_wrwait0 => -- s_rdput0: write wait 1st word
|
when s_wrwait0 => -- s_rdput0: write wait 1st word
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
idata_oe := '1'; -- oe FPGA next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_we := '1'; -- we CRAM next cycle
|
imem_we := '1'; -- we CRAM next cycle
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
n.state := s_wrput0; -- next: put 1st word
|
n.state := s_wrput0; -- next: put 1st word
|
end if;
|
end if;
|
|
|
when s_wrput0 => -- s_rdput0: write put 1st word
|
when s_wrput0 => -- s_rdput0: write put 1st word
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
imem_we := '0'; -- deassert we CRAM in half cycle
|
imem_we := '0'; -- deassert we CRAM in half cycle
|
if r.be2nd /= "00" then
|
if r.be2nd /= "00" then
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
iaddr0_ce := '1'; -- latch address 0 bit
|
iaddr0_ce := '1'; -- latch address 0 bit
|
iaddr0 := '1'; -- now go for high word
|
iaddr0 := '1'; -- now go for high word
|
ibe_ce := '1'; -- latch be's
|
ibe_ce := '1'; -- latch be's
|
imem_be := r.be2nd; -- now be's of high word
|
imem_be := r.be2nd; -- now be's of high word
|
n.state := s_wrini1; -- next: start 2nd write
|
n.state := s_wrini1; -- next: start 2nd write
|
else
|
else
|
n.state := s_idle; -- next: wait next request
|
n.state := s_idle; -- next: wait next request
|
if r.fidle = '1' then -- forced idle cycle
|
if r.fidle = '1' then -- forced idle cycle
|
ibusy := '1'; -- signal busy
|
ibusy := '1'; -- signal busy
|
else
|
else
|
if REQ = '1' then -- if IO requested
|
if REQ = '1' then -- if IO requested
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_wrini1 => -- s_wrini1: write init 2nd word
|
when s_wrini1 => -- s_wrini1: write init 2nd word
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
idata_ceo:= '1'; -- latch output data
|
idata_ceo:= '1'; -- latch output data
|
idata_oe := '1'; -- oe FPGA next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_we := '1'; -- we CRAM in half cycle
|
imem_we := '1'; -- we CRAM in half cycle
|
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
|
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
|
n.state := s_wrwait1; -- next: wait
|
n.state := s_wrwait1; -- next: wait
|
|
|
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
|
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
idata_oe := '1'; -- oe FPGA next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_ce := '1'; -- ce CRAM next cycle
|
imem_we := '1'; -- we CRAM next cycle
|
imem_we := '1'; -- we CRAM next cycle
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
if unsigned(r.cntdly) = 0 then -- wait expired ?
|
n.state := s_wrput1; -- next: put 2nd word
|
n.state := s_wrput1; -- next: put 2nd word
|
end if;
|
end if;
|
|
|
when s_wrput1 => -- s_wrput1: write put 2nd word
|
when s_wrput1 => -- s_wrput1: write put 2nd word
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
imem_we := '0'; -- deassert we CRAM in half cycle
|
imem_we := '0'; -- deassert we CRAM in half cycle
|
n.state := s_idle; -- next: wait next request
|
n.state := s_idle; -- next: wait next request
|
if r.fidle = '1' then -- forced idle cycle
|
if r.fidle = '1' then -- forced idle cycle
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
else
|
else
|
if REQ = '1' then -- if IO requested
|
if REQ = '1' then -- if IO requested
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
if imem_ce = '0' then -- if cmem not active
|
if imem_ce = '0' then -- if cmem not active
|
n.cntce := (others=>'0'); -- clear counter
|
n.cntce := (others=>'0'); -- clear counter
|
n.fidle := '0'; -- clear force idle flag
|
n.fidle := '0'; -- clear force idle flag
|
else -- if cmem active
|
else -- if cmem active
|
if unsigned(r.cntce) >= 127 then -- if max ce count expired
|
if unsigned(r.cntce) >= 127 then -- if max ce count expired
|
n.fidle := '1'; -- set forced idle flag
|
n.fidle := '1'; -- set forced idle flag
|
else -- if max ce count not yet reached
|
else -- if max ce count not yet reached
|
n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
|
n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if iaddrh_ce = '1' then -- if addresses are latched
|
if iaddrh_ce = '1' then -- if addresses are latched
|
n.memdi := DI; -- latch data too...
|
n.memdi := DI; -- latch data too...
|
end if;
|
end if;
|
|
|
if iaddr0_ce = '1' then -- if address bit 0 changed
|
if iaddr0_ce = '1' then -- if address bit 0 changed
|
n.addr0 := iaddr0; -- mirror it in state regs
|
n.addr0 := iaddr0; -- mirror it in state regs
|
end if;
|
end if;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
MEM_CE_N <= not imem_ce;
|
MEM_CE_N <= not imem_ce;
|
MEM_WE_N <= not imem_we;
|
MEM_WE_N <= not imem_we;
|
MEM_BE_N <= not imem_be;
|
MEM_BE_N <= not imem_be;
|
MEM_OE_N <= not imem_oe;
|
MEM_OE_N <= not imem_oe;
|
|
|
if r.addr0 = '0' then
|
if r.addr0 = '0' then
|
MEM_DI <= r.memdi(15 downto 0);
|
MEM_DI <= r.memdi(15 downto 0);
|
else
|
else
|
MEM_DI <= r.memdi(31 downto 16);
|
MEM_DI <= r.memdi(31 downto 16);
|
end if;
|
end if;
|
|
|
BE_CE <= ibe_ce;
|
BE_CE <= ibe_ce;
|
ADDRH_CE <= iaddrh_ce;
|
ADDRH_CE <= iaddrh_ce;
|
ADDR0_CE <= iaddr0_ce;
|
ADDR0_CE <= iaddr0_ce;
|
ADDR0 <= iaddr0;
|
ADDR0 <= iaddr0;
|
DATA_CEI <= idata_cei;
|
DATA_CEI <= idata_cei;
|
DATA_CEO <= idata_ceo;
|
DATA_CEO <= idata_ceo;
|
DATA_OE <= idata_oe;
|
DATA_OE <= idata_oe;
|
|
|
BUSY <= ibusy;
|
BUSY <= ibusy;
|
ACK_R <= r.ackr;
|
ACK_R <= r.ackr;
|
ACK_W <= iackw;
|
ACK_W <= iackw;
|
ACT_R <= iactr;
|
ACT_R <= iactr;
|
ACT_W <= iactw;
|
ACT_W <= iactw;
|
|
|
DO <= MEM_DO & r.memdo0;
|
DO <= MEM_DO & r.memdo0;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
end syn;
|
end syn;
|
|
|