-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: s3_sram_memctl - syn
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-- Module Name: s3_sram_memctl - syn
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-- Description: s3board: SRAM driver
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-- Description: s3board: SRAM driver
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--
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--
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-- Dependencies: vlib/xlib/iob_reg_o
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-- Dependencies: vlib/xlib/iob_reg_o
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-- vlib/xlib/iob_reg_o_gen
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-- vlib/xlib/iob_reg_o_gen
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-- vlib/xlib/iob_reg_io_gen
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-- vlib/xlib/iob_reg_io_gen
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-- Test bench: tb/tb_s3_sram_memctl
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-- Test bench: tb/tb_s3_sram_memctl
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-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
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-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-05-23 293 11.4 L68 xc3s1000-4 7 22 0 14 s 8.5
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-- 2010-05-23 293 11.4 L68 xc3s1000-4 7 22 0 14 s 8.5
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-- 2008-02-16 116 8.2.03 I34 xc3s1000-4 5 30 0 17 s 7.0
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-- 2008-02-16 116 8.2.03 I34 xc3s1000-4 5 30 0 17 s 7.0
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 1.0.6 now numeric_std clean
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-- 2011-11-19 427 1.0.6 now numeric_std clean
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-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
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-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
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-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
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-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
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-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface
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-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface
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-- 2008-01-20 113 1.0.2 rename memdrv -> memctl_s3sram
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-- 2008-01-20 113 1.0.2 rename memdrv -> memctl_s3sram
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-- 2007-12-15 101 1.0.1 use _N for active low; get ce/we clocking right
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-- 2007-12-15 101 1.0.1 use _N for active low; get ce/we clocking right
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-- 2007-12-08 100 1.0 Initial version
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-- 2007-12-08 100 1.0 Initial version
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--
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--
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-- Timing of some signals:
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-- Timing of some signals:
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--
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--
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-- single read request:
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-- single read request:
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--
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--
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-- state |_idle |_read |_idle |
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-- state |_idle |_read |_idle |
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--
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--
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-- CLK __|^^^|___|^^^|___|^^^|___|^
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-- CLK __|^^^|___|^^^|___|^^^|___|^
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--
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--
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-- REQ _______|^^^^^|______________
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-- REQ _______|^^^^^|______________
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-- WE ____________________________
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-- WE ____________________________
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--
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--
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-- IOB_CE __________|^^^^^^^|_________
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-- IOB_CE __________|^^^^^^^|_________
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-- IOB_OE __________|^^^^^^^|_________
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-- IOB_OE __________|^^^^^^^|_________
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--
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--
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-- DO oooooooooooooooooo|ddddddd|d
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-- DO oooooooooooooooooo|ddddddd|d
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-- BUSY ____________________________
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-- BUSY ____________________________
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-- ACK_R __________________|^^^^^^^|_
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-- ACK_R __________________|^^^^^^^|_
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--
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--
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-- single write request:
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-- single write request:
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--
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--
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-- state |_idle |_write1|_write2|_idle |
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-- state |_idle |_write1|_write2|_idle |
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--
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--
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-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^
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-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^
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--
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--
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-- REQ _______|^^^^^|______________
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-- REQ _______|^^^^^|______________
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-- WE _______|^^^^^|______________
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-- WE _______|^^^^^|______________
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--
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--
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-- IOB_CE __________|^^^^^^^^^^^^^^^|_________
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-- IOB_CE __________|^^^^^^^^^^^^^^^|_________
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-- IOB_BE __________|^^^^^^^^^^^^^^^|_________
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-- IOB_BE __________|^^^^^^^^^^^^^^^|_________
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-- IOB_OE ____________________________________
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-- IOB_OE ____________________________________
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-- IOB_WE ______________|^^^^^^^|_____________
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-- IOB_WE ______________|^^^^^^^|_____________
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--
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--
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-- BUSY __________|^^^^^^^|_________________
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-- BUSY __________|^^^^^^^|_________________
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-- ACK_W __________________|^^^^^^^|_________
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-- ACK_W __________________|^^^^^^^|_________
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.xlib.all;
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entity s3_sram_memctl is -- SRAM driver for S3BOARD
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entity s3_sram_memctl is -- SRAM driver for S3BOARD
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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REQ : in slbit; -- request
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REQ : in slbit; -- request
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WE : in slbit; -- write enable
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WE : in slbit; -- write enable
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BUSY : out slbit; -- controller busy
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BUSY : out slbit; -- controller busy
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ACK_R : out slbit; -- acknowledge read
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ACK_R : out slbit; -- acknowledge read
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ACK_W : out slbit; -- acknowledge write
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ACK_W : out slbit; -- acknowledge write
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ACT_R : out slbit; -- signal active read
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ACT_R : out slbit; -- signal active read
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ACT_W : out slbit; -- signal active write
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ACT_W : out slbit; -- signal active write
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ADDR : in slv18; -- address
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ADDR : in slv18; -- address
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BE : in slv4; -- byte enable
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BE : in slv4; -- byte enable
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DI : in slv32; -- data in (memory view)
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DI : in slv32; -- data in (memory view)
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DO : out slv32; -- data out (memory view)
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DO : out slv32; -- data out (memory view)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv18; -- sram: address lines
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O_MEM_ADDR : out slv18; -- sram: address lines
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IO_MEM_DATA : inout slv32 -- sram: data lines
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IO_MEM_DATA : inout slv32 -- sram: data lines
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);
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);
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end s3_sram_memctl;
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end s3_sram_memctl;
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architecture syn of s3_sram_memctl is
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architecture syn of s3_sram_memctl is
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: wait for req
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s_idle, -- s_idle: wait for req
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s_read, -- s_read: read cycle
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s_read, -- s_read: read cycle
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s_write1, -- s_write1: write cycle, 1st half
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s_write1, -- s_write1: write cycle, 1st half
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s_write2, -- s_write2: write cycle, 2nd half
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s_write2, -- s_write2: write cycle, 2nd half
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s_bta_r2w, -- s_bta_r2w: bus turn around: r->w
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s_bta_r2w, -- s_bta_r2w: bus turn around: r->w
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s_bta_w2r -- s_bta_w2r: bus turn around: w->r
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s_bta_w2r -- s_bta_w2r: bus turn around: w->r
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);
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);
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type regs_type is record
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type regs_type is record
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state : state_type; -- state
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state : state_type; -- state
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ackr : slbit; -- signal ack_r
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ackr : slbit; -- signal ack_r
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle,
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s_idle,
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'0' -- ackr
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'0' -- ackr
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);
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal CLK_180 : slbit := '0';
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signal CLK_180 : slbit := '0';
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signal MEM_CE_N : slv2 := "00";
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signal MEM_CE_N : slv2 := "00";
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signal MEM_BE_N : slv4 := "0000";
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signal MEM_BE_N : slv4 := "0000";
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signal MEM_WE_N : slbit := '0';
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signal MEM_WE_N : slbit := '0';
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signal MEM_OE_N : slbit := '0';
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signal MEM_OE_N : slbit := '0';
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signal ADDR_CE : slbit := '0';
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signal ADDR_CE : slbit := '0';
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signal DATA_CEI : slbit := '0';
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signal DATA_CEI : slbit := '0';
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signal DATA_CEO : slbit := '0';
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signal DATA_CEO : slbit := '0';
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signal DATA_OE : slbit := '0';
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signal DATA_OE : slbit := '0';
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begin
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begin
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CLK_180 <= not CLK;
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CLK_180 <= not CLK;
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IOB_MEM_CE : iob_reg_o_gen
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IOB_MEM_CE : iob_reg_o_gen
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generic map (
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generic map (
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DWIDTH => 2,
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DWIDTH => 2,
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INIT => '1')
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INIT => '1')
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE => '1',
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CE => '1',
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DO => MEM_CE_N,
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DO => MEM_CE_N,
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PAD => O_MEM_CE_N
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PAD => O_MEM_CE_N
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);
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);
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IOB_MEM_BE : iob_reg_o_gen
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IOB_MEM_BE : iob_reg_o_gen
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generic map (
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generic map (
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DWIDTH => 4,
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DWIDTH => 4,
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INIT => '1')
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INIT => '1')
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE => ADDR_CE,
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CE => ADDR_CE,
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DO => MEM_BE_N,
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DO => MEM_BE_N,
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PAD => O_MEM_BE_N
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PAD => O_MEM_BE_N
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);
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);
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IOB_MEM_WE : iob_reg_o
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IOB_MEM_WE : iob_reg_o
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generic map (
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generic map (
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INIT => '1')
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INIT => '1')
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port map (
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port map (
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CLK => CLK_180,
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CLK => CLK_180,
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CE => '1',
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CE => '1',
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DO => MEM_WE_N,
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DO => MEM_WE_N,
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PAD => O_MEM_WE_N
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PAD => O_MEM_WE_N
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);
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);
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IOB_MEM_OE : iob_reg_o
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IOB_MEM_OE : iob_reg_o
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generic map (
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generic map (
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INIT => '1')
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INIT => '1')
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE => '1',
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CE => '1',
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DO => MEM_OE_N,
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DO => MEM_OE_N,
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PAD => O_MEM_OE_N
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PAD => O_MEM_OE_N
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);
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);
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IOB_MEM_ADDR : iob_reg_o_gen
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IOB_MEM_ADDR : iob_reg_o_gen
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generic map (
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generic map (
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DWIDTH => 18)
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DWIDTH => 18)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE => ADDR_CE,
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CE => ADDR_CE,
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DO => ADDR,
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DO => ADDR,
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PAD => O_MEM_ADDR
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PAD => O_MEM_ADDR
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);
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);
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IOB_MEM_DATA : iob_reg_io_gen
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IOB_MEM_DATA : iob_reg_io_gen
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generic map (
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generic map (
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DWIDTH => 32,
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DWIDTH => 32,
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PULL => "KEEP")
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PULL => "KEEP")
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CEI => DATA_CEI,
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CEI => DATA_CEI,
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CEO => DATA_CEO,
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CEO => DATA_CEO,
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OE => DATA_OE,
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OE => DATA_OE,
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DI => DO,
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DI => DO,
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DO => DI,
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DO => DI,
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PAD => IO_MEM_DATA
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PAD => IO_MEM_DATA
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next: process (R_REGS, REQ, WE, BE)
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proc_next: process (R_REGS, REQ, WE, BE)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibusy : slbit := '0';
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variable ibusy : slbit := '0';
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variable iackw : slbit := '0';
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variable iackw : slbit := '0';
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variable iactr : slbit := '0';
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variable iactr : slbit := '0';
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variable iactw : slbit := '0';
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variable iactw : slbit := '0';
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variable imem_ce : slv2 := "00";
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variable imem_ce : slv2 := "00";
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variable imem_be : slv4 := "0000";
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variable imem_be : slv4 := "0000";
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variable imem_we : slbit := '0';
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variable imem_we : slbit := '0';
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variable imem_oe : slbit := '0';
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variable imem_oe : slbit := '0';
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variable iaddr_ce : slbit := '0';
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variable iaddr_ce : slbit := '0';
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variable idata_cei : slbit := '0';
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variable idata_cei : slbit := '0';
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variable idata_ceo : slbit := '0';
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variable idata_ceo : slbit := '0';
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variable idata_oe : slbit := '0';
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variable idata_oe : slbit := '0';
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begin
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begin
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|
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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n.ackr := '0';
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n.ackr := '0';
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ibusy := '0';
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ibusy := '0';
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iackw := '0';
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iackw := '0';
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iactr := '0';
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iactr := '0';
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iactw := '0';
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iactw := '0';
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|
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imem_ce := "00";
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imem_ce := "00";
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imem_be := "1111";
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imem_be := "1111";
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imem_we := '0';
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imem_we := '0';
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imem_oe := '0';
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imem_oe := '0';
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iaddr_ce := '0';
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iaddr_ce := '0';
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idata_cei := '0';
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idata_cei := '0';
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idata_ceo := '0';
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idata_ceo := '0';
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idata_oe := '0';
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idata_oe := '0';
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case r.state is
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case r.state is
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when s_idle => -- s_idle: wait for req
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when s_idle => -- s_idle: wait for req
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if REQ = '1' then -- if IO requested
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if REQ = '1' then -- if IO requested
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if WE = '0' then -- if READ requested
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if WE = '0' then -- if READ requested
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iaddr_ce := '1'; -- latch address and be's
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iaddr_ce := '1'; -- latch address and be's
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imem_ce := "11"; -- ce SRAM next cycle
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imem_ce := "11"; -- ce SRAM next cycle
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imem_oe := '1'; -- oe SRAM next cycle
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imem_oe := '1'; -- oe SRAM next cycle
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n.state := s_read; -- next: read
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n.state := s_read; -- next: read
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else -- if WRITE requested
|
else -- if WRITE requested
|
iaddr_ce := '1'; -- latch address and be's
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iaddr_ce := '1'; -- latch address and be's
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idata_ceo := '1'; -- latch output data
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idata_ceo := '1'; -- latch output data
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idata_oe := '1'; -- oe FPGA next cycle
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idata_oe := '1'; -- oe FPGA next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
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imem_be := BE; -- use request BE's
|
imem_be := BE; -- use request BE's
|
n.state := s_write1; -- next: write 1st part
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n.state := s_write1; -- next: write 1st part
|
end if;
|
end if;
|
end if;
|
end if;
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|
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when s_read => -- s_read: read cycle
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when s_read => -- s_read: read cycle
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idata_cei := '1'; -- latch input data
|
idata_cei := '1'; -- latch input data
|
iactr := '1'; -- signal mem read
|
iactr := '1'; -- signal mem read
|
n.ackr := '1'; -- ACK_R next cycle
|
n.ackr := '1'; -- ACK_R next cycle
|
if REQ = '1' then -- if IO requested
|
if REQ = '1' then -- if IO requested
|
if WE = '0' then -- if READ requested
|
if WE = '0' then -- if READ requested
|
iaddr_ce := '1'; -- latch address and be's
|
iaddr_ce := '1'; -- latch address and be's
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_oe := '1'; -- oe SRAM next cycle
|
imem_oe := '1'; -- oe SRAM next cycle
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n.state := s_read; -- next: continue read
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n.state := s_read; -- next: continue read
|
else -- if WRITE requested
|
else -- if WRITE requested
|
iaddr_ce := '1'; -- latch address and be's
|
iaddr_ce := '1'; -- latch address and be's
|
idata_ceo := '1'; -- latch output data
|
idata_ceo := '1'; -- latch output data
|
imem_be := BE; -- use request BE's
|
imem_be := BE; -- use request BE's
|
n.state := s_bta_r2w; -- next: bus turn around cycle
|
n.state := s_bta_r2w; -- next: bus turn around cycle
|
end if;
|
end if;
|
else
|
else
|
n.state := s_idle; -- next: idle if nothing to do
|
n.state := s_idle; -- next: idle if nothing to do
|
end if;
|
end if;
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|
|
when s_write1 => -- s_write1: write cycle, 1st half
|
when s_write1 => -- s_write1: write cycle, 1st half
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
idata_oe := '1'; -- oe FPGA next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_we := '1'; -- we SRAM next shifted cycle
|
imem_we := '1'; -- we SRAM next shifted cycle
|
n.state := s_write2; -- next: write cycle, 2nd half
|
n.state := s_write2; -- next: write cycle, 2nd half
|
|
|
when s_write2 => -- s_write2: write cycle, 2nd half
|
when s_write2 => -- s_write2: write cycle, 2nd half
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
iackw := '1'; -- signal write acknowledge
|
iackw := '1'; -- signal write acknowledge
|
idata_cei := '1'; -- latch input data (from SRAM)
|
idata_cei := '1'; -- latch input data (from SRAM)
|
if REQ = '1' then -- if IO requested
|
if REQ = '1' then -- if IO requested
|
if WE = '1' then -- if WRITE requested
|
if WE = '1' then -- if WRITE requested
|
iaddr_ce := '1'; -- latch address and be's
|
iaddr_ce := '1'; -- latch address and be's
|
idata_ceo := '1'; -- latch output data
|
idata_ceo := '1'; -- latch output data
|
idata_oe := '1'; -- oe FPGA next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_be := BE; -- use request BE's
|
imem_be := BE; -- use request BE's
|
n.state := s_write1; -- next: continue read
|
n.state := s_write1; -- next: continue read
|
else -- if READ requested
|
else -- if READ requested
|
iaddr_ce := '1'; -- latch address and be's
|
iaddr_ce := '1'; -- latch address and be's
|
n.state := s_bta_w2r; -- next: bus turn around cycle
|
n.state := s_bta_w2r; -- next: bus turn around cycle
|
end if;
|
end if;
|
else
|
else
|
n.state := s_idle; -- next: idle if nothing to do
|
n.state := s_idle; -- next: idle if nothing to do
|
end if;
|
end if;
|
|
|
when s_bta_r2w => -- s_bta_r2w: bus turn around: r->w
|
when s_bta_r2w => -- s_bta_r2w: bus turn around: r->w
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactw := '1'; -- signal mem write
|
iactw := '1'; -- signal mem write
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
idata_oe := '1'; -- oe FPGA next cycle
|
n.state := s_write1; -- next: start write
|
n.state := s_write1; -- next: start write
|
|
|
when s_bta_w2r => -- s_bta_w2r: bus turn around: w->r
|
when s_bta_w2r => -- s_bta_w2r: bus turn around: w->r
|
ibusy := '1'; -- signal busy, unable to handle req
|
ibusy := '1'; -- signal busy, unable to handle req
|
iactr := '1'; -- signal mem read
|
iactr := '1'; -- signal mem read
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_ce := "11"; -- ce SRAM next cycle
|
imem_oe := '1'; -- oe SRAM next cycle
|
imem_oe := '1'; -- oe SRAM next cycle
|
n.state := s_read; -- next: start read
|
n.state := s_read; -- next: start read
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
MEM_CE_N <= not imem_ce;
|
MEM_CE_N <= not imem_ce;
|
MEM_WE_N <= not imem_we;
|
MEM_WE_N <= not imem_we;
|
MEM_BE_N <= not imem_be;
|
MEM_BE_N <= not imem_be;
|
MEM_OE_N <= not imem_oe;
|
MEM_OE_N <= not imem_oe;
|
ADDR_CE <= iaddr_ce;
|
ADDR_CE <= iaddr_ce;
|
DATA_CEI <= idata_cei;
|
DATA_CEI <= idata_cei;
|
DATA_CEO <= idata_ceo;
|
DATA_CEO <= idata_ceo;
|
DATA_OE <= idata_oe;
|
DATA_OE <= idata_oe;
|
|
|
BUSY <= ibusy;
|
BUSY <= ibusy;
|
ACK_R <= r.ackr;
|
ACK_R <= r.ackr;
|
ACK_W <= iackw;
|
ACK_W <= iackw;
|
ACT_R <= iactr;
|
ACT_R <= iactr;
|
ACT_W <= iactw;
|
ACT_W <= iactw;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
end syn;
|
end syn;
|
|
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