-- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: ibdr_dl11 - syn
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-- Module Name: ibdr_dl11 - syn
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-- Description: ibus dev(rem): DL11-A/B
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-- Description: ibus dev(rem): DL11-A/B
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
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-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
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-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
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-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
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-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
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-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
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-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK
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-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK
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-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change)
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-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change)
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-- 2008-01-27 115 1.0.3 bugfix: set ilam when rbuf read by cpu;
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-- 2008-01-27 115 1.0.3 bugfix: set ilam when rbuf read by cpu;
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-- add xdone and rrdy bits to rri xbuf read
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-- add xdone and rrdy bits to rri xbuf read
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-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now)
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-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now)
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-- 2008-01-20 112 1.0.1 use BRESET
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-- 2008-01-20 112 1.0.1 use BRESET
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-- 2008-01-05 108 1.0 Initial version
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-- 2008-01-05 108 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
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entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
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generic (
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generic (
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IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
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IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_USEC : in slbit; -- usec pulse
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RESET : in slbit; -- system reset
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ_RX : out slbit; -- interrupt request, receiver
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EI_REQ_RX : out slbit; -- interrupt request, receiver
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EI_REQ_TX : out slbit; -- interrupt request, transmitter
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EI_REQ_TX : out slbit; -- interrupt request, transmitter
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EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
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EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
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EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
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EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
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);
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);
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end ibdr_dl11;
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end ibdr_dl11;
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architecture syn of ibdr_dl11 is
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architecture syn of ibdr_dl11 is
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constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
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constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
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constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
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constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
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constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
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constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
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constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
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constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
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subtype rcsr_ibf_rrlim is integer range 14 downto 12;
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subtype rcsr_ibf_rrlim is integer range 14 downto 12;
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constant rcsr_ibf_rdone : integer := 7;
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constant rcsr_ibf_rdone : integer := 7;
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constant rcsr_ibf_rie : integer := 6;
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constant rcsr_ibf_rie : integer := 6;
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constant xcsr_ibf_xrdy : integer := 7;
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constant xcsr_ibf_xrdy : integer := 7;
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constant xcsr_ibf_xie : integer := 6;
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constant xcsr_ibf_xie : integer := 6;
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constant xcsr_ibf_xmaint: integer := 2;
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constant xcsr_ibf_xmaint: integer := 2;
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constant xbuf_ibf_xval : integer := 8;
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constant xbuf_ibf_xval : integer := 8;
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constant xbuf_ibf_rrdy : integer := 9;
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constant xbuf_ibf_rrdy : integer := 9;
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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ibsel : slbit; -- ibus select
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rrlim : slv3; -- rcsr: receiver rate limit
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rrlim : slv3; -- rcsr: receiver rate limit
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rdone : slbit; -- rcsr: receiver done
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rdone : slbit; -- rcsr: receiver done
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rie : slbit; -- rcsr: receiver interrupt enable
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rie : slbit; -- rcsr: receiver interrupt enable
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rbuf : slv8; -- rbuf:
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rbuf : slv8; -- rbuf:
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rval : slbit; -- rx rbuf valid
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rval : slbit; -- rx rbuf valid
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rintreq : slbit; -- rx interrupt request
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rintreq : slbit; -- rx interrupt request
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rdlybsy : slbit; -- rx delay busy
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rdlybsy : slbit; -- rx delay busy
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rdlycnt : slv10; -- rx delay counter
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rdlycnt : slv10; -- rx delay counter
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xrdy : slbit; -- xcsr: transmitter ready
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xrdy : slbit; -- xcsr: transmitter ready
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xie : slbit; -- xcsr: transmitter interrupt enable
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xie : slbit; -- xcsr: transmitter interrupt enable
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xmaint : slbit; -- xcsr: maintenance mode
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xmaint : slbit; -- xcsr: maintenance mode
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xbuf : slv8; -- xbuf:
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xbuf : slv8; -- xbuf:
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xintreq : slbit; -- tx interrupt request
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xintreq : slbit; -- tx interrupt request
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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'0', -- ibsel
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'0', -- ibsel
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(others=>'0'), -- rrlim
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(others=>'0'), -- rrlim
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'0','0', -- rdone, rie
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'0','0', -- rdone, rie
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(others=>'0'), -- rbuf
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(others=>'0'), -- rbuf
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'0','0','0', -- rval,rintreq,rdlybsy
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'0','0','0', -- rval,rintreq,rdlybsy
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(others=>'0'), -- rdlycnt
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(others=>'0'), -- rdlycnt
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'1', -- xrdy !! is set !!
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'1', -- xrdy !! is set !!
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'0','0', -- xie,xmaint
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'0','0', -- xie,xmaint
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(others=>'0'), -- xbuf
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(others=>'0'), -- xbuf
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'0' -- xintreq
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'0' -- xintreq
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);
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);
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signal R_REGS : regs_type := regs_init;
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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begin
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if BRESET = '1' then
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if BRESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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if RESET = '0' then -- if RESET=0 we do just an ibus reset
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if RESET = '0' then -- if RESET=0 we do just an ibus reset
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R_REGS.rrlim <= N_REGS.rrlim; -- don't reset rx rate limit
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R_REGS.rrlim <= N_REGS.rrlim; -- don't reset rx rate limit
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R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
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R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
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R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter
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R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter
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end if;
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end if;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX)
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proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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variable ibreq : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ilam : slbit := '0';
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variable ilam : slbit := '0';
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variable rdlystart : slbit := '0';
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variable rdlystart : slbit := '0';
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variable rdlyinit : slv10 := (others=>'0');
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variable rdlyinit : slv10 := (others=>'0');
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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idout := (others=>'0');
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idout := (others=>'0');
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibrd := IB_MREQ.re;
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ibrd := IB_MREQ.re;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ilam := '0';
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ilam := '0';
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rdlystart := '0';
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rdlystart := '0';
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-- ibus address decoder
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-- ibus address decoder
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n.ibsel := '0';
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n.ibsel := '0';
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if IB_MREQ.aval='1' and
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if IB_MREQ.aval='1' and
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IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
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IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
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n.ibsel := '1';
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n.ibsel := '1';
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end if;
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end if;
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-- ibus transactions
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-- ibus transactions
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if r.ibsel = '1' then
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if r.ibsel = '1' then
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case IB_MREQ.addr(2 downto 1) is
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case IB_MREQ.addr(2 downto 1) is
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when ibaddr_rcsr => -- RCSR -- receive control status ----
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when ibaddr_rcsr => -- RCSR -- receive control status ----
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idout(rcsr_ibf_rdone) := r.rdone;
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idout(rcsr_ibf_rdone) := r.rdone;
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idout(rcsr_ibf_rie) := r.rie;
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idout(rcsr_ibf_rie) := r.rie;
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if ibw0 = '1' then
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if ibw0 = '1' then
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n.rie := IB_MREQ.din(rcsr_ibf_rie);
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n.rie := IB_MREQ.din(rcsr_ibf_rie);
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if IB_MREQ.din(rcsr_ibf_rie) = '1' then
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if IB_MREQ.din(rcsr_ibf_rie) = '1' then
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if r.rdone='1' and r.rie='0' then -- ie set while done=1
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if r.rdone='1' and r.rie='0' then -- ie set while done=1
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n.rintreq := '1'; -- request interrupt
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n.rintreq := '1'; -- request interrupt
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end if;
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end if;
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else
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else
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n.rintreq := '0';
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n.rintreq := '0';
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end if;
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end if;
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end if;
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end if;
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else -- rri ---------------------
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else -- rri ---------------------
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idout(rcsr_ibf_rrlim) := r.rrlim;
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idout(rcsr_ibf_rrlim) := r.rrlim;
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if ibw1 = '1' then
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if ibw1 = '1' then
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n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
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n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
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end if;
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end if;
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end if;
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end if;
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when ibaddr_rbuf => -- RBUF -- receive data buffer -------
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when ibaddr_rbuf => -- RBUF -- receive data buffer -------
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idout(r.rbuf'range) := r.rbuf;
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idout(r.rbuf'range) := r.rbuf;
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if ibrd = '1' then
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if ibrd = '1' then
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n.rdone := '0'; -- clear DONE
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n.rdone := '0'; -- clear DONE
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n.rval := '0'; -- clear rbuf valid
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n.rval := '0'; -- clear rbuf valid
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n.rintreq := '0'; -- clear pending interrupts
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n.rintreq := '0'; -- clear pending interrupts
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rdlystart := '1'; -- start rx delay counter
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rdlystart := '1'; -- start rx delay counter
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if r.xmaint = '0' then -- if not in loop-back
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if r.xmaint = '0' then -- if not in loop-back
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ilam := '1'; -- request rb attention
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ilam := '1'; -- request rb attention
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end if;
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end if;
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end if;
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end if;
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else -- rri ---------------------
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else -- rri ---------------------
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if ibw0 = '1' then
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if ibw0 = '1' then
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n.rbuf := IB_MREQ.din(n.rbuf'range);
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n.rbuf := IB_MREQ.din(n.rbuf'range);
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n.rval := '1'; -- set rbuf valid
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n.rval := '1'; -- set rbuf valid
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if r.rdlybsy = '0' then -- if rdly timer not running
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if r.rdlybsy = '0' then -- if rdly timer not running
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n.rdone := '1'; -- set DONE
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n.rdone := '1'; -- set DONE
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if r.rie = '1' then -- if rx interrupt enabled
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if r.rie = '1' then -- if rx interrupt enabled
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n.rintreq := '1'; -- request interrupt
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n.rintreq := '1'; -- request interrupt
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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when ibaddr_xcsr => -- XCSR -- transmit control status ---
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when ibaddr_xcsr => -- XCSR -- transmit control status ---
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idout(xcsr_ibf_xrdy) := r.xrdy;
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idout(xcsr_ibf_xrdy) := r.xrdy;
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idout(xcsr_ibf_xie) := r.xie;
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idout(xcsr_ibf_xie) := r.xie;
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idout(xcsr_ibf_xmaint):= r.xmaint;
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idout(xcsr_ibf_xmaint):= r.xmaint;
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if ibw0 = '1' then
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if ibw0 = '1' then
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n.xie := IB_MREQ.din(xcsr_ibf_xie);
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n.xie := IB_MREQ.din(xcsr_ibf_xie);
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if IB_MREQ.din(xcsr_ibf_xie) = '1' then
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if IB_MREQ.din(xcsr_ibf_xie) = '1' then
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if r.xrdy='1' and r.xie='0' then -- ie set while ready=1
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if r.xrdy='1' and r.xie='0' then -- ie set while ready=1
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n.xintreq := '1'; -- request interrupt
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n.xintreq := '1'; -- request interrupt
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end if;
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end if;
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else
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else
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n.xintreq := '0';
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n.xintreq := '0';
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end if;
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end if;
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n.xmaint := IB_MREQ.din(xcsr_ibf_xmaint);
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n.xmaint := IB_MREQ.din(xcsr_ibf_xmaint);
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end if;
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end if;
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end if;
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end if;
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when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
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when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if ibw0 = '1' then
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if ibw0 = '1' then
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n.xbuf := IB_MREQ.din(n.xbuf'range);
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n.xbuf := IB_MREQ.din(n.xbuf'range);
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n.xrdy := '0';
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n.xrdy := '0';
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n.xintreq := '0';
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n.xintreq := '0';
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if r.xmaint = '0' then
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if r.xmaint = '0' then
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ilam := '1';
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ilam := '1';
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end if;
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end if;
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end if;
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end if;
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else -- rri ---------------------
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else -- rri ---------------------
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idout(r.xbuf'range) := r.xbuf;
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idout(r.xbuf'range) := r.xbuf;
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if r.xmaint = '0' then -- if not in maintenace mode
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if r.xmaint = '0' then -- if not in maintenace mode
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idout(xbuf_ibf_xval) := not r.xrdy;
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idout(xbuf_ibf_xval) := not r.xrdy;
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idout(xbuf_ibf_rrdy) := not r.rval;
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idout(xbuf_ibf_rrdy) := not r.rval;
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end if;
|
end if;
|
if ibrd = '1' then
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if ibrd = '1' then
|
n.xrdy := '1';
|
n.xrdy := '1';
|
if r.xie = '1' then
|
if r.xie = '1' then
|
n.xintreq := '1';
|
n.xintreq := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
else -- if unselected handle loop-back
|
else -- if unselected handle loop-back
|
if r.xmaint = '1' and -- if in maintenace mode
|
if r.xmaint = '1' and -- if in maintenace mode
|
r.xrdy='0' and -- and transmit pending
|
r.xrdy='0' and -- and transmit pending
|
r.rdone='0' and -- and receive buffer empty
|
r.rdone='0' and -- and receive buffer empty
|
r.rdlybsy='0' then -- and rdly timer not running
|
r.rdlybsy='0' then -- and rdly timer not running
|
n.rbuf := r.xbuf; -- copy transmit to receive buffer
|
n.rbuf := r.xbuf; -- copy transmit to receive buffer
|
n.xrdy := '1'; -- mark transmit done
|
n.xrdy := '1'; -- mark transmit done
|
n.rdone := '1'; -- make receive done
|
n.rdone := '1'; -- make receive done
|
if r.rie = '1' then -- if rx interrupt enabled
|
if r.rie = '1' then -- if rx interrupt enabled
|
n.rintreq := '1'; -- request it
|
n.rintreq := '1'; -- request it
|
end if;
|
end if;
|
if r.xie = '1' then -- if tx interrupt enabled
|
if r.xie = '1' then -- if tx interrupt enabled
|
n.xintreq := '1'; -- request it
|
n.xintreq := '1'; -- request it
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
-- other state changes
|
-- other state changes
|
|
|
rdlyinit := (others=>'0');
|
rdlyinit := (others=>'0');
|
case r.rrlim is
|
case r.rrlim is
|
when "000" => rdlyinit := "0000000000"; -- rlim=0 -> disabled
|
when "000" => rdlyinit := "0000000000"; -- rlim=0 -> disabled
|
when "001" => rdlyinit := "0000000011"; -- rlim=1 -> delay by 3+ usec
|
when "001" => rdlyinit := "0000000011"; -- rlim=1 -> delay by 3+ usec
|
when "010" => rdlyinit := "0000001111"; -- rlim=2 -> delay by 15+ usec
|
when "010" => rdlyinit := "0000001111"; -- rlim=2 -> delay by 15+ usec
|
when "011" => rdlyinit := "0000111111"; -- rlim=3 -> delay by 63+ usec
|
when "011" => rdlyinit := "0000111111"; -- rlim=3 -> delay by 63+ usec
|
when "100" => rdlyinit := "0001111111"; -- rlim=4 -> delay by 127+ usec
|
when "100" => rdlyinit := "0001111111"; -- rlim=4 -> delay by 127+ usec
|
when "101" => rdlyinit := "0011111111"; -- rlim=5 -> delay by 255+ usec
|
when "101" => rdlyinit := "0011111111"; -- rlim=5 -> delay by 255+ usec
|
when "110" => rdlyinit := "0111111111"; -- rlim=6 -> delay by 511+ usec
|
when "110" => rdlyinit := "0111111111"; -- rlim=6 -> delay by 511+ usec
|
when "111" => rdlyinit := "1111111111"; -- rlim=7 -> delay by 1023+ usec
|
when "111" => rdlyinit := "1111111111"; -- rlim=7 -> delay by 1023+ usec
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
if rdlystart = '1' then -- if rdly timer start requested
|
if rdlystart = '1' then -- if rdly timer start requested
|
n.rdlycnt := rdlyinit; -- init counter
|
n.rdlycnt := rdlyinit; -- init counter
|
if r.rrlim /= "000" then -- rate limiter enabled ?
|
if r.rrlim /= "000" then -- rate limiter enabled ?
|
n.rdlybsy := '1'; -- set busy
|
n.rdlybsy := '1'; -- set busy
|
end if;
|
end if;
|
elsif CE_USEC = '1' then -- if end-of-usec
|
elsif CE_USEC = '1' then -- if end-of-usec
|
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement
|
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement
|
if r.rdlybsy='1' and -- if delay busy
|
if r.rdlybsy='1' and -- if delay busy
|
unsigned(r.rdlycnt) = 0 then -- and counter at zero
|
unsigned(r.rdlycnt) = 0 then -- and counter at zero
|
n.rdlybsy := '0'; -- clear busy
|
n.rdlybsy := '0'; -- clear busy
|
if n.rval = '1' then -- if rbuf is valid or is set
|
if n.rval = '1' then -- if rbuf is valid or is set
|
-- valid this cycle (use n.!!)
|
-- valid this cycle (use n.!!)
|
n.rdone := '1'; -- set DONE
|
n.rdone := '1'; -- set DONE
|
if r.rie = '1' then -- if rx interrupt enabled
|
if r.rie = '1' then -- if rx interrupt enabled
|
n.rintreq := '1'; -- request interrupt
|
n.rintreq := '1'; -- request interrupt
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if EI_ACK_RX = '1' then
|
if EI_ACK_RX = '1' then
|
n.rintreq := '0';
|
n.rintreq := '0';
|
end if;
|
end if;
|
if EI_ACK_TX = '1' then
|
if EI_ACK_TX = '1' then
|
n.xintreq := '0';
|
n.xintreq := '0';
|
end if;
|
end if;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
IB_SRES.dout <= idout;
|
IB_SRES.dout <= idout;
|
IB_SRES.ack <= r.ibsel and ibreq;
|
IB_SRES.ack <= r.ibsel and ibreq;
|
IB_SRES.busy <= '0';
|
IB_SRES.busy <= '0';
|
|
|
RB_LAM <= ilam;
|
RB_LAM <= ilam;
|
EI_REQ_RX <= r.rintreq;
|
EI_REQ_RX <= r.rintreq;
|
EI_REQ_TX <= r.xintreq;
|
EI_REQ_TX <= r.xintreq;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
|
|
end syn;
|
end syn;
|
|
|