-- $Id: rbd_tst_rlink.vhd 438 2011-12-11 23:40:52Z mueller $
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-- $Id: rbd_tst_rlink.vhd 438 2011-12-11 23:40:52Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rbd_tst_rlink - syn
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-- Module Name: rbd_tst_rlink - syn
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-- Description: rbus device for tst_rlink
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-- Description: rbus device for tst_rlink
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--
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--
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-- Dependencies: rbus/rbd_tester
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-- Dependencies: rbus/rbd_tester
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-- rbus/rbd_bram
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-- rbus/rbd_bram
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-- rbus/rbd_rbmon
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-- rbus/rbd_rbmon
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-- rbus/rbd_eyemon
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-- rbus/rbd_eyemon
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-- rbus/rbd_timer
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-- rbus/rbd_timer
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-- rbus/rb_sres_or_3
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-- rbus/rb_sres_or_3
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-- rbus/rb_sres_or_4
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-- rbus/rb_sres_or_4
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--
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--
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-- Test bench: nexys3/tb/tb_tst_rlink_n3
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-- Test bench: nexys3/tb/tb_tst_rlink_n3
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Tool versions: xst 13.1; ghdl 0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-11 351 1.0 Initial version (derived from tst_rlink)
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-- 2011-11-11 351 1.0 Initial version (derived from tst_rlink)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Usage of STAT signal:
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-- Usage of STAT signal:
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-- STAT(0): timer 0 busy
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-- STAT(0): timer 0 busy
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-- STAT(1): timer 1 busy
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-- STAT(1): timer 1 busy
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-- STAT(2:7): unused
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-- STAT(2:7): unused
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.rbdlib.all;
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use work.rbdlib.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity rbd_tst_rlink is -- rbus device for tst_rlink
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entity rbd_tst_rlink is -- rbus device for tst_rlink
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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CE_USEC : in slbit; -- usec pulse
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CE_USEC : in slbit; -- usec pulse
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_LAM : out slv16; -- rbus: look at me
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RB_LAM : out slv16; -- rbus: look at me
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RB_STAT : out slv3; -- rbus: status flags
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RB_STAT : out slv3; -- rbus: status flags
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RB_SRES_TOP : in rb_sres_type; -- top-level rb_sres, for rbd_mon
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RB_SRES_TOP : in rb_sres_type; -- top-level rb_sres, for rbd_mon
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RXSD : in slbit; -- serport rxsd, for rbd_emon
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RXSD : in slbit; -- serport rxsd, for rbd_emon
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RXACT : in slbit; -- serport rxact, for rbd_emon
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RXACT : in slbit; -- serport rxact, for rbd_emon
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STAT : out slv8 -- status flags
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STAT : out slv8 -- status flags
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);
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);
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end rbd_tst_rlink;
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end rbd_tst_rlink;
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architecture syn of rbd_tst_rlink is
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architecture syn of rbd_tst_rlink is
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signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
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signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
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signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
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signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
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signal RB_SRES_MON : rb_sres_type := rb_sres_init;
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signal RB_SRES_MON : rb_sres_type := rb_sres_init;
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signal RB_SRES_EMON : rb_sres_type := rb_sres_init;
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signal RB_SRES_EMON : rb_sres_type := rb_sres_init;
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signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init;
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signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init;
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signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init;
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signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init;
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signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init;
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signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init;
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signal RB_LAM_TEST : slv16 := (others=>'0');
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signal RB_LAM_TEST : slv16 := (others=>'0');
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signal TIM0_DONE : slbit := '0';
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signal TIM0_DONE : slbit := '0';
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signal TIM0_BUSY : slbit := '0';
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signal TIM0_BUSY : slbit := '0';
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signal TIM1_DONE : slbit := '0';
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signal TIM1_DONE : slbit := '0';
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signal TIM1_BUSY : slbit := '0';
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signal TIM1_BUSY : slbit := '0';
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constant rbaddr_mon : slv8 := "11111100"; -- 111111xx
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constant rbaddr_mon : slv8 := "11111100"; -- 111111xx
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constant rbaddr_emon : slv8 := "11111000"; -- 111110xx
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constant rbaddr_emon : slv8 := "11111000"; -- 111110xx
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constant rbaddr_bram : slv8 := "11110100"; -- 111101xx
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constant rbaddr_bram : slv8 := "11110100"; -- 111101xx
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constant rbaddr_test : slv8 := "11110000"; -- 111100xx
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constant rbaddr_test : slv8 := "11110000"; -- 111100xx
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constant rbaddr_tim1 : slv8 := "11100001"; -- 11100001
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constant rbaddr_tim1 : slv8 := "11100001"; -- 11100001
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constant rbaddr_tim0 : slv8 := "11100000"; -- 11100000
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constant rbaddr_tim0 : slv8 := "11100000"; -- 11100000
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begin
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begin
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TEST : rbd_tester
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TEST : rbd_tester
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generic map (
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generic map (
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RB_ADDR => rbaddr_test)
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RB_ADDR => rbaddr_test)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_TEST,
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RB_SRES => RB_SRES_TEST,
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RB_LAM => RB_LAM_TEST,
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RB_LAM => RB_LAM_TEST,
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RB_STAT => RB_STAT
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RB_STAT => RB_STAT
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);
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);
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BRAM : rbd_bram
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BRAM : rbd_bram
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generic map (
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generic map (
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RB_ADDR => rbaddr_bram)
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RB_ADDR => rbaddr_bram)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_BRAM
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RB_SRES => RB_SRES_BRAM
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);
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);
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MON : rbd_rbmon
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MON : rbd_rbmon
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generic map (
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generic map (
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RB_ADDR => rbaddr_mon,
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RB_ADDR => rbaddr_mon,
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AWIDTH => 9)
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AWIDTH => 9)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_MON,
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RB_SRES => RB_SRES_MON,
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RB_SRES_SUM => RB_SRES_TOP
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RB_SRES_SUM => RB_SRES_TOP
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);
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);
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EMON : rbd_eyemon
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EMON : rbd_eyemon
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generic map (
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generic map (
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RB_ADDR => rbaddr_emon,
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RB_ADDR => rbaddr_emon,
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RDIV => slv(to_unsigned(0,8)))
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RDIV => slv(to_unsigned(0,8)))
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_EMON,
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RB_SRES => RB_SRES_EMON,
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RXSD => RXSD,
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RXSD => RXSD,
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RXACT => RXACT
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RXACT => RXACT
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);
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);
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TIM0 : rbd_timer
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TIM0 : rbd_timer
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generic map (
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generic map (
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RB_ADDR => rbaddr_tim0)
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RB_ADDR => rbaddr_tim0)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RESET => RESET,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_TIM0,
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RB_SRES => RB_SRES_TIM0,
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DONE => TIM0_DONE,
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DONE => TIM0_DONE,
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BUSY => TIM0_BUSY
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BUSY => TIM0_BUSY
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);
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);
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TIM1 : rbd_timer
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TIM1 : rbd_timer
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generic map (
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generic map (
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RB_ADDR => rbaddr_tim1)
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RB_ADDR => rbaddr_tim1)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RESET => RESET,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_TIM1,
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RB_SRES => RB_SRES_TIM1,
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DONE => TIM1_DONE,
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DONE => TIM1_DONE,
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BUSY => TIM1_BUSY
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BUSY => TIM1_BUSY
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);
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);
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RB_SRES_OR1 : rb_sres_or_3
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RB_SRES_OR1 : rb_sres_or_3
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port map (
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port map (
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RB_SRES_1 => RB_SRES_TEST,
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RB_SRES_1 => RB_SRES_TEST,
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RB_SRES_2 => RB_SRES_BRAM,
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RB_SRES_2 => RB_SRES_BRAM,
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RB_SRES_3 => RB_SRES_MON,
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RB_SRES_3 => RB_SRES_MON,
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RB_SRES_OR => RB_SRES_SUM1
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RB_SRES_OR => RB_SRES_SUM1
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);
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);
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RB_SRES_OR : rb_sres_or_4
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RB_SRES_OR : rb_sres_or_4
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port map (
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port map (
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RB_SRES_1 => RB_SRES_SUM1,
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RB_SRES_1 => RB_SRES_SUM1,
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RB_SRES_2 => RB_SRES_EMON,
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RB_SRES_2 => RB_SRES_EMON,
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RB_SRES_3 => RB_SRES_TIM0,
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RB_SRES_3 => RB_SRES_TIM0,
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RB_SRES_4 => RB_SRES_TIM1,
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RB_SRES_4 => RB_SRES_TIM1,
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RB_SRES_OR => RB_SRES
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RB_SRES_OR => RB_SRES
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);
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);
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RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2);
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RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2);
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RB_LAM(1) <= TIM1_DONE;
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RB_LAM(1) <= TIM1_DONE;
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RB_LAM(0) <= TIM0_DONE;
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RB_LAM(0) <= TIM0_DONE;
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STAT(0) <= TIM0_BUSY;
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STAT(0) <= TIM0_BUSY;
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STAT(1) <= TIM1_BUSY;
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STAT(1) <= TIM1_BUSY;
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STAT(7 downto 2) <= (others=>'0');
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STAT(7 downto 2) <= (others=>'0');
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end syn;
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end syn;
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