-- $Id: sys_tst_rlink_s3.vhd 476 2013-01-26 22:23:53Z mueller $
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-- $Id: sys_tst_rlink_s3.vhd 476 2013-01-26 22:23:53Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: sys_tst_rlink_s3 - syn
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-- Module Name: sys_tst_rlink_s3 - syn
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-- Description: rlink tester design for s3board
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-- Description: rlink tester design for s3board
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--
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--
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-- Dependencies: vlib/genlib/clkdivce
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-- Dependencies: vlib/genlib/clkdivce
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/sn_humanio_rbus
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-- bplib/bpgen/sn_humanio_rbus
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-- vlib/rlink/rlink_sp1c
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-- vlib/rlink/rlink_sp1c
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-- rbd_tst_rlink
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-- rbd_tst_rlink
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-- vlib/rbus/rb_sres_or_2
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-- vlib/rbus/rb_sres_or_2
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-- bplib/s3board/s3_sram_dummy
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-- bplib/s3board/s3_sram_dummy
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--
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--
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-- Test bench: tb/tb_tst_rlink_s3
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-- Test bench: tb/tb_tst_rlink_s3
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Tool versions: xst 13.1; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6
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-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2)
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-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Usage of S3board switches, Buttons, LEDs:
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-- Usage of S3board switches, Buttons, LEDs:
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--
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--
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-- SWI(7:2): no function (only connected to sn_humanio_rbus)
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-- SWI(7:2): no function (only connected to sn_humanio_rbus)
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-- SWI(1): 1 enable XON
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-- SWI(1): 1 enable XON
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-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
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-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
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-- 1 -> Pmod B/top RS232 port /
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-- 1 -> Pmod B/top RS232 port /
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--
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--
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-- LED(7): SER_MONI.abact
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-- LED(7): SER_MONI.abact
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-- LED(6:2): no function (only connected to sn_humanio_rbus)
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-- LED(6:2): no function (only connected to sn_humanio_rbus)
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-- LED(0): timer 0 busy
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-- LED(0): timer 0 busy
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-- LED(1): timer 1 busy
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-- LED(1): timer 1 busy
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--
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--
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-- DSP: SER_MONI.clkdiv (from auto bauder)
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-- DSP: SER_MONI.clkdiv (from auto bauder)
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-- DP(3): not SER_MONI.txok (shows tx back preasure)
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-- DP(3): not SER_MONI.txok (shows tx back preasure)
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-- DP(2): SER_MONI.txact (shows tx activity)
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-- DP(2): SER_MONI.txact (shows tx activity)
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-- DP(1): not SER_MONI.rxok (shows rx back preasure)
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-- DP(1): not SER_MONI.rxok (shows rx back preasure)
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-- DP(0): SER_MONI.rxact (shows rx activity)
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-- DP(0): SER_MONI.rxact (shows rx activity)
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.genlib.all;
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use work.genlib.all;
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use work.serportlib.all;
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use work.serportlib.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.rlinklib.all;
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use work.bpgenlib.all;
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use work.bpgenlib.all;
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use work.bpgenrbuslib.all;
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use work.bpgenrbuslib.all;
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use work.s3boardlib.all;
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use work.s3boardlib.all;
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use work.sys_conf.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity sys_tst_rlink_s3 is -- top level
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entity sys_tst_rlink_s3 is -- top level
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-- implements s3board_fusp_aif
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-- implements s3board_fusp_aif
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port (
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port (
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I_CLK50 : in slbit; -- 50 MHz board clock
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I_CLK50 : in slbit; -- 50 MHz board clock
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I_RXD : in slbit; -- receive data (board view)
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- s3 switches
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I_SWI : in slv8; -- s3 switches
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I_BTN : in slv4; -- s3 buttons
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I_BTN : in slv4; -- s3 buttons
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O_LED : out slv8; -- s3 leds
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O_LED : out slv8; -- s3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv18; -- sram: address lines
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O_MEM_ADDR : out slv18; -- sram: address lines
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IO_MEM_DATA : inout slv32; -- sram: data lines
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IO_MEM_DATA : inout slv32; -- sram: data lines
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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);
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);
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end sys_tst_rlink_s3;
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end sys_tst_rlink_s3;
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architecture syn of sys_tst_rlink_s3 is
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architecture syn of sys_tst_rlink_s3 is
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signal CLK : slbit := '0';
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signal CLK : slbit := '0';
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signal RXD : slbit := '1';
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signal RXD : slbit := '1';
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signal TXD : slbit := '0';
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signal TXD : slbit := '0';
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signal RTS_N : slbit := '0';
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signal RTS_N : slbit := '0';
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signal CTS_N : slbit := '0';
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signal CTS_N : slbit := '0';
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signal SWI : slv8 := (others=>'0');
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signal SWI : slv8 := (others=>'0');
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signal BTN : slv4 := (others=>'0');
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signal BTN : slv4 := (others=>'0');
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signal LED : slv8 := (others=>'0');
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signal LED : slv8 := (others=>'0');
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signal DSP_DAT : slv16 := (others=>'0');
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signal DSP_DAT : slv16 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal RESET : slbit := '0';
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signal RESET : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal CE_MSEC : slbit := '0';
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signal CE_MSEC : slbit := '0';
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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signal RB_SRES_TST : rb_sres_type := rb_sres_init;
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signal RB_SRES_TST : rb_sres_type := rb_sres_init;
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_STAT : slv3 := (others=>'0');
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signal RB_STAT : slv3 := (others=>'0');
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal STAT : slv8 := (others=>'0');
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signal STAT : slv8 := (others=>'0');
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constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
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constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
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begin
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begin
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assert (sys_conf_clksys mod 1000000) = 0
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assert (sys_conf_clksys mod 1000000) = 0
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report "assert sys_conf_clksys on MHz grid"
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report "assert sys_conf_clksys on MHz grid"
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severity failure;
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severity failure;
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RESET <= '0'; -- so far not used
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RESET <= '0'; -- so far not used
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CLK <= I_CLK50;
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CLK <= I_CLK50;
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CLKDIV : clkdivce
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CLKDIV : clkdivce
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generic map (
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generic map (
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CDUWIDTH => 7,
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CDUWIDTH => 7,
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USECDIV => sys_conf_clksys_mhz,
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USECDIV => sys_conf_clksys_mhz,
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MSECDIV => 1000)
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MSECDIV => 1000)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC
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CE_MSEC => CE_MSEC
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);
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);
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IOB_RS232 : bp_rs232_2l4l_iob
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IOB_RS232 : bp_rs232_2l4l_iob
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => '0',
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RESET => '0',
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SEL => SWI(0),
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SEL => SWI(0),
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RXD => RXD,
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RXD => RXD,
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TXD => TXD,
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TXD => TXD,
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CTS_N => CTS_N,
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CTS_N => CTS_N,
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RTS_N => RTS_N,
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RTS_N => RTS_N,
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I_RXD0 => I_RXD,
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I_RXD0 => I_RXD,
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O_TXD0 => O_TXD,
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O_TXD0 => O_TXD,
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I_RXD1 => I_FUSP_RXD,
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I_RXD1 => I_FUSP_RXD,
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O_TXD1 => O_FUSP_TXD,
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O_TXD1 => O_FUSP_TXD,
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I_CTS1_N => I_FUSP_CTS_N,
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I_CTS1_N => I_FUSP_CTS_N,
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O_RTS1_N => O_FUSP_RTS_N
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O_RTS1_N => O_FUSP_RTS_N
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);
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);
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HIO : sn_humanio_rbus
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HIO : sn_humanio_rbus
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generic map (
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generic map (
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DEBOUNCE => sys_conf_hio_debounce,
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DEBOUNCE => sys_conf_hio_debounce,
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RB_ADDR => rbaddr_hio)
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RB_ADDR => rbaddr_hio)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_HIO,
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RB_SRES => RB_SRES_HIO,
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SWI => SWI,
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SWI => SWI,
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BTN => BTN,
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BTN => BTN,
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LED => LED,
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LED => LED,
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DSP_DAT => DSP_DAT,
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DSP_DAT => DSP_DAT,
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DSP_DP => DSP_DP,
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DSP_DP => DSP_DP,
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I_SWI => I_SWI,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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I_BTN => I_BTN,
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O_LED => O_LED,
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O_LED => O_LED,
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O_ANO_N => O_ANO_N,
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O_ANO_N => O_ANO_N,
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O_SEG_N => O_SEG_N
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O_SEG_N => O_SEG_N
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);
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);
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RLINK : rlink_sp1c
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RLINK : rlink_sp1c
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generic map (
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generic map (
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ATOWIDTH => 6,
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ATOWIDTH => 6,
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ITOWIDTH => 6,
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ITOWIDTH => 6,
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CPREF => c_rlink_cpref,
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CPREF => c_rlink_cpref,
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IFAWIDTH => 5,
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IFAWIDTH => 5,
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OFAWIDTH => 5,
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OFAWIDTH => 5,
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ENAPIN_RLMON => sbcntl_sbf_rlmon,
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ENAPIN_RLMON => sbcntl_sbf_rlmon,
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ENAPIN_RBMON => sbcntl_sbf_rbmon,
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ENAPIN_RBMON => sbcntl_sbf_rbmon,
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CDWIDTH => 15,
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CDWIDTH => 15,
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CDINIT => sys_conf_ser2rri_cdinit)
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CDINIT => sys_conf_ser2rri_cdinit)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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CE_INT => CE_MSEC,
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CE_INT => CE_MSEC,
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RESET => RESET,
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RESET => RESET,
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ENAXON => SWI(1),
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ENAXON => SWI(1),
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ENAESC => SWI(1),
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ENAESC => SWI(1),
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RXSD => RXD,
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RXSD => RXD,
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TXSD => TXD,
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TXSD => TXD,
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CTS_N => CTS_N,
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CTS_N => CTS_N,
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RTS_N => RTS_N,
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RTS_N => RTS_N,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT,
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RB_STAT => RB_STAT,
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RL_MONI => open,
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RL_MONI => open,
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SER_MONI => SER_MONI
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SER_MONI => SER_MONI
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);
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);
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RBDTST : entity work.rbd_tst_rlink
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RBDTST : entity work.rbd_tst_rlink
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_TST,
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RB_SRES => RB_SRES_TST,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT,
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RB_STAT => RB_STAT,
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RB_SRES_TOP => RB_SRES,
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RB_SRES_TOP => RB_SRES,
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RXSD => RXD,
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RXSD => RXD,
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RXACT => SER_MONI.rxact,
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RXACT => SER_MONI.rxact,
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STAT => STAT
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STAT => STAT
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);
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);
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RB_SRES_OR1 : rb_sres_or_2
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RB_SRES_OR1 : rb_sres_or_2
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port map (
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port map (
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RB_SRES_1 => RB_SRES_HIO,
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RB_SRES_1 => RB_SRES_HIO,
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RB_SRES_2 => RB_SRES_TST,
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RB_SRES_2 => RB_SRES_TST,
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RB_SRES_OR => RB_SRES
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RB_SRES_OR => RB_SRES
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);
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);
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|
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SRAM : s3_sram_dummy -- connect SRAM to protection dummy
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SRAM : s3_sram_dummy -- connect SRAM to protection dummy
|
port map (
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port map (
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_ADDR => O_MEM_ADDR,
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O_MEM_ADDR => O_MEM_ADDR,
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IO_MEM_DATA => IO_MEM_DATA
|
IO_MEM_DATA => IO_MEM_DATA
|
);
|
);
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|
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DSP_DAT <= SER_MONI.abclkdiv;
|
DSP_DAT <= SER_MONI.abclkdiv;
|
|
|
DSP_DP(3) <= not SER_MONI.txok;
|
DSP_DP(3) <= not SER_MONI.txok;
|
DSP_DP(2) <= SER_MONI.txact;
|
DSP_DP(2) <= SER_MONI.txact;
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DSP_DP(1) <= not SER_MONI.rxok;
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DSP_DP(1) <= not SER_MONI.rxok;
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DSP_DP(0) <= SER_MONI.rxact;
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DSP_DP(0) <= SER_MONI.rxact;
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|
|
LED(7) <= SER_MONI.abact;
|
LED(7) <= SER_MONI.abact;
|
LED(6 downto 2) <= (others=>'0');
|
LED(6 downto 2) <= (others=>'0');
|
LED(1) <= STAT(1);
|
LED(1) <= STAT(1);
|
LED(0) <= STAT(0);
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LED(0) <= STAT(0);
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|
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end syn;
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end syn;
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|
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