-- $Id: sys_w11a_n3.vhd 538 2013-10-06 17:21:25Z mueller $
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-- $Id: sys_w11a_n3.vhd 538 2013-10-06 17:21:25Z mueller $
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--
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--
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-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: sys_w11a_n3 - syn
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-- Module Name: sys_w11a_n3 - syn
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-- Description: w11a test design for nexys3
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-- Description: w11a test design for nexys3
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--
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--
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-- Dependencies: vlib/xlib/s6_cmt_sfs
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-- Dependencies: vlib/xlib/s6_cmt_sfs
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-- vlib/genlib/clkdivce
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-- vlib/genlib/clkdivce
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/sn_humanio_rbus
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-- bplib/bpgen/sn_humanio_rbus
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-- bplib/fx2rlink/rlink_sp1c_fx2
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-- bplib/fx2rlink/rlink_sp1c_fx2
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-- bplib/fx2rlink/ioleds_sp1c_fx2
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-- bplib/fx2rlink/ioleds_sp1c_fx2
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-- vlib/rri/rb_sres_or_3
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-- vlib/rri/rb_sres_or_3
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-- w11a/pdp11_core_rbus
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-- w11a/pdp11_core_rbus
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-- w11a/pdp11_core
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-- w11a/pdp11_core
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-- w11a/pdp11_bram
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-- w11a/pdp11_bram
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-- vlib/nxcramlib/nx_cram_dummy
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-- vlib/nxcramlib/nx_cram_dummy
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-- w11a/pdp11_cache
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-- w11a/pdp11_cache
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-- w11a/pdp11_mem70
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-- w11a/pdp11_mem70
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-- bplib/nxcramlib/nx_cram_memctl_as
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-- bplib/nxcramlib/nx_cram_memctl_as
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-- ibus/ib_sres_or_2
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-- ibus/ib_sres_or_2
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-- ibus/ibdr_minisys
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-- ibus/ibdr_minisys
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-- ibus/ibdr_maxisys
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-- ibus/ibdr_maxisys
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-- w11a/pdp11_tmu_sb [sim only]
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-- w11a/pdp11_tmu_sb [sim only]
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--
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--
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-- Test bench: tb/tb_sys_w11a_n3
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-- Test bench: tb/tb_sys_w11a_n3
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1, 14.6; ghdl 0.29
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-- Tool versions: xst 13.1, 14.6; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
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-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
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-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
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-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
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-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
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-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
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-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
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-- 2013-04-21 509 1.4 added fx2 (cuff) support
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-- 2013-04-21 509 1.4 added fx2 (cuff) support
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-- 2011-12-18 440 1.0.4 use rlink_sp1c
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-- 2011-12-18 440 1.0.4 use rlink_sp1c
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-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
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-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
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-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
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-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
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-- 2011-11-23 432 1.0.1 fixup PPCM handling
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-- 2011-11-23 432 1.0.1 fixup PPCM handling
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-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
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-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- w11a test design for nexys3
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-- w11a test design for nexys3
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-- w11a + rlink + serport
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-- w11a + rlink + serport
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--
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--
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-- Usage of Nexys 3 Switches, Buttons, LEDs:
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-- Usage of Nexys 3 Switches, Buttons, LEDs:
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--
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--
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-- SWI(7:3): no function (only connected to sn_humanio_rbus)
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-- SWI(7:3): no function (only connected to sn_humanio_rbus)
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-- (2) 0 -> int/ext RS242 port for rlink
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-- (2) 0 -> int/ext RS242 port for rlink
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-- 1 -> use USB interface for rlink
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-- 1 -> use USB interface for rlink
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-- SWI(1): 1 enable XON
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-- SWI(1): 1 enable XON
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-- SWI(0): 0 -> main board RS232 port
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-- SWI(0): 0 -> main board RS232 port
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-- 1 -> Pmod B/top RS232 port
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-- 1 -> Pmod B/top RS232 port
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--
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--
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-- LED(7) MEM_ACT_W
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-- LED(7) MEM_ACT_W
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-- (6) MEM_ACT_R
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-- (6) MEM_ACT_R
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-- (5) cmdbusy (all rlink access, mostly rdma)
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-- (5) cmdbusy (all rlink access, mostly rdma)
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-- (4:0): if cpugo=1 show cpu mode activity
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-- (4:0): if cpugo=1 show cpu mode activity
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-- (4) kernel mode, pri>0
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-- (4) kernel mode, pri>0
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-- (3) kernel mode, pri=0
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-- (3) kernel mode, pri=0
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-- (2) kernel mode, wait
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-- (2) kernel mode, wait
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-- (1) supervisor mode
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-- (1) supervisor mode
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-- (0) user mode
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-- (0) user mode
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-- if cpugo=0 shows cpurust
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-- if cpugo=0 shows cpurust
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-- (3:0) cpurust code
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-- (3:0) cpurust code
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-- (4) '1'
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-- (4) '1'
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--
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--
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-- DP(3:0) shows IO activity
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-- DP(3:0) shows IO activity
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-- if SWI(2)=0 (serport)
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-- if SWI(2)=0 (serport)
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-- (3): not SER_MONI.txok (shows tx back preasure)
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-- (3): not SER_MONI.txok (shows tx back preasure)
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-- (2): SER_MONI.txact (shows tx activity)
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-- (2): SER_MONI.txact (shows tx activity)
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-- (1): not SER_MONI.rxok (shows rx back preasure)
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-- (1): not SER_MONI.rxok (shows rx back preasure)
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-- (0): SER_MONI.rxact (shows rx activity)
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-- (0): SER_MONI.rxact (shows rx activity)
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-- if SWI(2)=1 (fx2-usb)
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-- if SWI(2)=1 (fx2-usb)
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-- (3): RB_SRES.busy (shows rbus back preasure)
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-- (3): RB_SRES.busy (shows rbus back preasure)
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-- (2): RLB_TXBUSY (shows tx back preasure)
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-- (2): RLB_TXBUSY (shows tx back preasure)
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-- (1): RLB_TXENA (shows tx activity)
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-- (1): RLB_TXENA (shows tx activity)
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-- (0): RLB_RXVAL (shows rx activity)
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-- (0): RLB_RXVAL (shows rx activity)
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.xlib.all;
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use work.genlib.all;
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use work.genlib.all;
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use work.serportlib.all;
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use work.serportlib.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.rlinklib.all;
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use work.fx2lib.all;
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use work.fx2lib.all;
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use work.fx2rlinklib.all;
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use work.fx2rlinklib.all;
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use work.bpgenlib.all;
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use work.bpgenlib.all;
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use work.bpgenrbuslib.all;
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use work.bpgenrbuslib.all;
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use work.nxcramlib.all;
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use work.nxcramlib.all;
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use work.iblib.all;
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use work.iblib.all;
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use work.ibdlib.all;
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use work.ibdlib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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use work.sys_conf.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity sys_w11a_n3 is -- top level
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entity sys_w11a_n3 is -- top level
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-- implements nexys3_fusp_cuff_aif
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-- implements nexys3_fusp_cuff_aif
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port (
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port (
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I_CLK100 : in slbit; -- 100 MHz clock
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I_CLK100 : in slbit; -- 100 MHz clock
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I_RXD : in slbit; -- receive data (board view)
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- n3 switches
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I_SWI : in slv8; -- n3 switches
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I_BTN : in slv5; -- n3 buttons
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I_BTN : in slv5; -- n3 buttons
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O_LED : out slv8; -- n3 leds
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O_LED : out slv8; -- n3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_MEM_ADDR : out slv23; -- cram: address lines
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16; -- cram: data lines
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IO_MEM_DATA : inout slv16; -- cram: data lines
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O_PPCM_CE_N : out slbit; -- ppcm: ...
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O_PPCM_CE_N : out slbit; -- ppcm: ...
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O_PPCM_RST_N : out slbit; -- ppcm: ...
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O_PPCM_RST_N : out slbit; -- ppcm: ...
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit; -- fusp: rs232 tx
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O_FUSP_TXD : out slbit; -- fusp: rs232 tx
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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);
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end sys_w11a_n3;
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end sys_w11a_n3;
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architecture syn of sys_w11a_n3 is
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architecture syn of sys_w11a_n3 is
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signal CLK : slbit := '0';
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signal CLK : slbit := '0';
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signal RXD : slbit := '1';
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signal RXD : slbit := '1';
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signal TXD : slbit := '0';
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signal TXD : slbit := '0';
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signal RTS_N : slbit := '0';
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signal RTS_N : slbit := '0';
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signal CTS_N : slbit := '0';
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signal CTS_N : slbit := '0';
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signal SWI : slv8 := (others=>'0');
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signal SWI : slv8 := (others=>'0');
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signal BTN : slv5 := (others=>'0');
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signal BTN : slv5 := (others=>'0');
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signal LED : slv8 := (others=>'0');
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signal LED : slv8 := (others=>'0');
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signal DSP_DAT : slv16 := (others=>'0');
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signal DSP_DAT : slv16 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_STAT : slv3 := (others=>'0');
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signal RB_STAT : slv3 := (others=>'0');
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signal RLB_MONI : rlb_moni_type := rlb_moni_init;
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signal RLB_MONI : rlb_moni_type := rlb_moni_init;
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
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signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
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signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
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signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
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signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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signal RESET : slbit := '0';
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signal RESET : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal CE_MSEC : slbit := '0';
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signal CE_MSEC : slbit := '0';
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signal CPU_RESET : slbit := '0';
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signal CPU_RESET : slbit := '0';
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signal CP_CNTL : cp_cntl_type := cp_cntl_init;
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signal CP_CNTL : cp_cntl_type := cp_cntl_init;
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signal CP_ADDR : cp_addr_type := cp_addr_init;
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signal CP_ADDR : cp_addr_type := cp_addr_init;
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signal CP_DIN : slv16 := (others=>'0');
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signal CP_DIN : slv16 := (others=>'0');
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signal CP_STAT : cp_stat_type := cp_stat_init;
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signal CP_STAT : cp_stat_type := cp_stat_init;
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signal CP_DOUT : slv16 := (others=>'0');
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signal CP_DOUT : slv16 := (others=>'0');
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signal EI_PRI : slv3 := (others=>'0');
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signal EI_PRI : slv3 := (others=>'0');
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signal EI_VECT : slv9_2 := (others=>'0');
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signal EI_VECT : slv9_2 := (others=>'0');
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signal EI_ACKM : slbit := '0';
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signal EI_ACKM : slbit := '0';
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signal EM_MREQ : em_mreq_type := em_mreq_init;
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signal EM_MREQ : em_mreq_type := em_mreq_init;
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signal EM_SRES : em_sres_type := em_sres_init;
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signal EM_SRES : em_sres_type := em_sres_init;
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signal HM_ENA : slbit := '0';
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signal HM_ENA : slbit := '0';
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signal MEM70_FMISS : slbit := '0';
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signal MEM70_FMISS : slbit := '0';
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signal CACHE_FMISS : slbit := '0';
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signal CACHE_FMISS : slbit := '0';
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signal CACHE_CHIT : slbit := '0';
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signal CACHE_CHIT : slbit := '0';
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signal MEM_REQ : slbit := '0';
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signal MEM_REQ : slbit := '0';
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signal MEM_WE : slbit := '0';
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signal MEM_WE : slbit := '0';
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signal MEM_BUSY : slbit := '0';
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signal MEM_BUSY : slbit := '0';
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signal MEM_ACK_R : slbit := '0';
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signal MEM_ACK_R : slbit := '0';
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signal MEM_ACT_R : slbit := '0';
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signal MEM_ACT_R : slbit := '0';
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signal MEM_ACT_W : slbit := '0';
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signal MEM_ACT_W : slbit := '0';
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signal MEM_ADDR : slv20 := (others=>'0');
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signal MEM_ADDR : slv20 := (others=>'0');
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signal MEM_BE : slv4 := (others=>'0');
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signal MEM_BE : slv4 := (others=>'0');
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signal MEM_DI : slv32 := (others=>'0');
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signal MEM_DI : slv32 := (others=>'0');
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signal MEM_DO : slv32 := (others=>'0');
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signal MEM_DO : slv32 := (others=>'0');
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signal MEM_ADDR_EXT : slv22 := (others=>'0');
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signal MEM_ADDR_EXT : slv22 := (others=>'0');
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signal BRESET : slbit := '0';
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signal BRESET : slbit := '0';
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signal IB_MREQ : ib_mreq_type := ib_mreq_init;
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signal IB_MREQ : ib_mreq_type := ib_mreq_init;
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signal IB_SRES : ib_sres_type := ib_sres_init;
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signal IB_SRES : ib_sres_type := ib_sres_init;
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signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
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signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
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signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
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signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
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signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
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signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
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signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
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signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
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signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
|
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
|
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
|
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
|
|
|
signal DISPREG : slv16 := (others=>'0');
|
signal DISPREG : slv16 := (others=>'0');
|
|
|
constant rbaddr_core0 : slv8 := "00000000";
|
constant rbaddr_core0 : slv8 := "00000000";
|
constant rbaddr_ibus : slv8 := "10000000";
|
constant rbaddr_ibus : slv8 := "10000000";
|
constant rbaddr_hio : slv8 := "11000000";
|
constant rbaddr_hio : slv8 := "11000000";
|
|
|
begin
|
begin
|
|
|
assert (sys_conf_clksys mod 1000000) = 0
|
assert (sys_conf_clksys mod 1000000) = 0
|
report "assert sys_conf_clksys on MHz grid"
|
report "assert sys_conf_clksys on MHz grid"
|
severity failure;
|
severity failure;
|
|
|
GEN_CLKSYS : s6_cmt_sfs
|
GEN_CLKSYS : s6_cmt_sfs
|
generic map (
|
generic map (
|
VCO_DIVIDE => sys_conf_clksys_vcodivide,
|
VCO_DIVIDE => sys_conf_clksys_vcodivide,
|
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
|
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
|
OUT_DIVIDE => sys_conf_clksys_outdivide,
|
OUT_DIVIDE => sys_conf_clksys_outdivide,
|
CLKIN_PERIOD => 10.0,
|
CLKIN_PERIOD => 10.0,
|
CLKIN_JITTER => 0.01,
|
CLKIN_JITTER => 0.01,
|
STARTUP_WAIT => false,
|
STARTUP_WAIT => false,
|
GEN_TYPE => sys_conf_clksys_gentype)
|
GEN_TYPE => sys_conf_clksys_gentype)
|
port map (
|
port map (
|
CLKIN => I_CLK100,
|
CLKIN => I_CLK100,
|
CLKFX => CLK,
|
CLKFX => CLK,
|
LOCKED => open
|
LOCKED => open
|
);
|
);
|
|
|
CLKDIV : clkdivce
|
CLKDIV : clkdivce
|
generic map (
|
generic map (
|
CDUWIDTH => 7,
|
CDUWIDTH => 7,
|
USECDIV => sys_conf_clksys_mhz,
|
USECDIV => sys_conf_clksys_mhz,
|
MSECDIV => 1000)
|
MSECDIV => 1000)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CE_USEC => CE_USEC,
|
CE_USEC => CE_USEC,
|
CE_MSEC => CE_MSEC
|
CE_MSEC => CE_MSEC
|
);
|
);
|
|
|
IOB_RS232 : bp_rs232_2l4l_iob
|
IOB_RS232 : bp_rs232_2l4l_iob
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
RESET => '0',
|
RESET => '0',
|
SEL => SWI(0),
|
SEL => SWI(0),
|
RXD => RXD,
|
RXD => RXD,
|
TXD => TXD,
|
TXD => TXD,
|
CTS_N => CTS_N,
|
CTS_N => CTS_N,
|
RTS_N => RTS_N,
|
RTS_N => RTS_N,
|
I_RXD0 => I_RXD,
|
I_RXD0 => I_RXD,
|
O_TXD0 => O_TXD,
|
O_TXD0 => O_TXD,
|
I_RXD1 => I_FUSP_RXD,
|
I_RXD1 => I_FUSP_RXD,
|
O_TXD1 => O_FUSP_TXD,
|
O_TXD1 => O_FUSP_TXD,
|
I_CTS1_N => I_FUSP_CTS_N,
|
I_CTS1_N => I_FUSP_CTS_N,
|
O_RTS1_N => O_FUSP_RTS_N
|
O_RTS1_N => O_FUSP_RTS_N
|
);
|
);
|
|
|
HIO : sn_humanio_rbus
|
HIO : sn_humanio_rbus
|
generic map (
|
generic map (
|
BWIDTH => 5,
|
BWIDTH => 5,
|
DEBOUNCE => sys_conf_hio_debounce,
|
DEBOUNCE => sys_conf_hio_debounce,
|
RB_ADDR => rbaddr_hio)
|
RB_ADDR => rbaddr_hio)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
RESET => RESET,
|
RESET => RESET,
|
CE_MSEC => CE_MSEC,
|
CE_MSEC => CE_MSEC,
|
RB_MREQ => RB_MREQ,
|
RB_MREQ => RB_MREQ,
|
RB_SRES => RB_SRES_HIO,
|
RB_SRES => RB_SRES_HIO,
|
SWI => SWI,
|
SWI => SWI,
|
BTN => BTN,
|
BTN => BTN,
|
LED => LED,
|
LED => LED,
|
DSP_DAT => DSP_DAT,
|
DSP_DAT => DSP_DAT,
|
DSP_DP => DSP_DP,
|
DSP_DP => DSP_DP,
|
I_SWI => I_SWI,
|
I_SWI => I_SWI,
|
I_BTN => I_BTN,
|
I_BTN => I_BTN,
|
O_LED => O_LED,
|
O_LED => O_LED,
|
O_ANO_N => O_ANO_N,
|
O_ANO_N => O_ANO_N,
|
O_SEG_N => O_SEG_N
|
O_SEG_N => O_SEG_N
|
);
|
);
|
|
|
RLINK : rlink_sp1c_fx2
|
RLINK : rlink_sp1c_fx2
|
generic map (
|
generic map (
|
ATOWIDTH => 7, -- 128 cycles access timeout
|
ATOWIDTH => 7, -- 128 cycles access timeout
|
ITOWIDTH => 6, -- 64 periods max idle timeout
|
ITOWIDTH => 6, -- 64 periods max idle timeout
|
CPREF => c_rlink_cpref,
|
CPREF => c_rlink_cpref,
|
IFAWIDTH => 5, -- 32 word input fifo
|
IFAWIDTH => 5, -- 32 word input fifo
|
OFAWIDTH => 5, -- 32 word output fifo
|
OFAWIDTH => 5, -- 32 word output fifo
|
PETOWIDTH => sys_conf_fx2_petowidth,
|
PETOWIDTH => sys_conf_fx2_petowidth,
|
CCWIDTH => sys_conf_fx2_ccwidth,
|
CCWIDTH => sys_conf_fx2_ccwidth,
|
ENAPIN_RLMON => sbcntl_sbf_rlmon,
|
ENAPIN_RLMON => sbcntl_sbf_rlmon,
|
ENAPIN_RBMON => sbcntl_sbf_rbmon,
|
ENAPIN_RBMON => sbcntl_sbf_rbmon,
|
CDWIDTH => 13,
|
CDWIDTH => 13,
|
CDINIT => sys_conf_ser2rri_cdinit)
|
CDINIT => sys_conf_ser2rri_cdinit)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CE_USEC => CE_USEC,
|
CE_USEC => CE_USEC,
|
CE_MSEC => CE_MSEC,
|
CE_MSEC => CE_MSEC,
|
CE_INT => CE_MSEC,
|
CE_INT => CE_MSEC,
|
RESET => RESET,
|
RESET => RESET,
|
ENAXON => SWI(1),
|
ENAXON => SWI(1),
|
ENAESC => SWI(1),
|
ENAESC => SWI(1),
|
ENAFX2 => SWI(2),
|
ENAFX2 => SWI(2),
|
RXSD => RXD,
|
RXSD => RXD,
|
TXSD => TXD,
|
TXSD => TXD,
|
CTS_N => CTS_N,
|
CTS_N => CTS_N,
|
RTS_N => RTS_N,
|
RTS_N => RTS_N,
|
RB_MREQ => RB_MREQ,
|
RB_MREQ => RB_MREQ,
|
RB_SRES => RB_SRES,
|
RB_SRES => RB_SRES,
|
RB_LAM => RB_LAM,
|
RB_LAM => RB_LAM,
|
RB_STAT => RB_STAT,
|
RB_STAT => RB_STAT,
|
RL_MONI => open,
|
RL_MONI => open,
|
RLB_MONI => RLB_MONI,
|
RLB_MONI => RLB_MONI,
|
SER_MONI => SER_MONI,
|
SER_MONI => SER_MONI,
|
FX2_MONI => FX2_MONI,
|
FX2_MONI => FX2_MONI,
|
I_FX2_IFCLK => I_FX2_IFCLK,
|
I_FX2_IFCLK => I_FX2_IFCLK,
|
O_FX2_FIFO => O_FX2_FIFO,
|
O_FX2_FIFO => O_FX2_FIFO,
|
I_FX2_FLAG => I_FX2_FLAG,
|
I_FX2_FLAG => I_FX2_FLAG,
|
O_FX2_SLRD_N => O_FX2_SLRD_N,
|
O_FX2_SLRD_N => O_FX2_SLRD_N,
|
O_FX2_SLWR_N => O_FX2_SLWR_N,
|
O_FX2_SLWR_N => O_FX2_SLWR_N,
|
O_FX2_SLOE_N => O_FX2_SLOE_N,
|
O_FX2_SLOE_N => O_FX2_SLOE_N,
|
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
|
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
|
IO_FX2_DATA => IO_FX2_DATA
|
IO_FX2_DATA => IO_FX2_DATA
|
);
|
);
|
|
|
RB_SRES_OR : rb_sres_or_3
|
RB_SRES_OR : rb_sres_or_3
|
port map (
|
port map (
|
RB_SRES_1 => RB_SRES_CPU,
|
RB_SRES_1 => RB_SRES_CPU,
|
RB_SRES_2 => RB_SRES_IBD,
|
RB_SRES_2 => RB_SRES_IBD,
|
RB_SRES_3 => RB_SRES_HIO,
|
RB_SRES_3 => RB_SRES_HIO,
|
RB_SRES_OR => RB_SRES
|
RB_SRES_OR => RB_SRES
|
);
|
);
|
|
|
RB2CP : pdp11_core_rbus
|
RB2CP : pdp11_core_rbus
|
generic map (
|
generic map (
|
RB_ADDR_CORE => rbaddr_core0,
|
RB_ADDR_CORE => rbaddr_core0,
|
RB_ADDR_IBUS => rbaddr_ibus)
|
RB_ADDR_IBUS => rbaddr_ibus)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
RESET => RESET,
|
RESET => RESET,
|
RB_MREQ => RB_MREQ,
|
RB_MREQ => RB_MREQ,
|
RB_SRES => RB_SRES_CPU,
|
RB_SRES => RB_SRES_CPU,
|
RB_STAT => RB_STAT,
|
RB_STAT => RB_STAT,
|
RB_LAM => RB_LAM(0),
|
RB_LAM => RB_LAM(0),
|
CPU_RESET => CPU_RESET,
|
CPU_RESET => CPU_RESET,
|
CP_CNTL => CP_CNTL,
|
CP_CNTL => CP_CNTL,
|
CP_ADDR => CP_ADDR,
|
CP_ADDR => CP_ADDR,
|
CP_DIN => CP_DIN,
|
CP_DIN => CP_DIN,
|
CP_STAT => CP_STAT,
|
CP_STAT => CP_STAT,
|
CP_DOUT => CP_DOUT
|
CP_DOUT => CP_DOUT
|
);
|
);
|
|
|
CORE : pdp11_core
|
CORE : pdp11_core
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
RESET => CPU_RESET,
|
RESET => CPU_RESET,
|
CP_CNTL => CP_CNTL,
|
CP_CNTL => CP_CNTL,
|
CP_ADDR => CP_ADDR,
|
CP_ADDR => CP_ADDR,
|
CP_DIN => CP_DIN,
|
CP_DIN => CP_DIN,
|
CP_STAT => CP_STAT,
|
CP_STAT => CP_STAT,
|
CP_DOUT => CP_DOUT,
|
CP_DOUT => CP_DOUT,
|
EI_PRI => EI_PRI,
|
EI_PRI => EI_PRI,
|
EI_VECT => EI_VECT,
|
EI_VECT => EI_VECT,
|
EI_ACKM => EI_ACKM,
|
EI_ACKM => EI_ACKM,
|
EM_MREQ => EM_MREQ,
|
EM_MREQ => EM_MREQ,
|
EM_SRES => EM_SRES,
|
EM_SRES => EM_SRES,
|
BRESET => BRESET,
|
BRESET => BRESET,
|
IB_MREQ_M => IB_MREQ,
|
IB_MREQ_M => IB_MREQ,
|
IB_SRES_M => IB_SRES,
|
IB_SRES_M => IB_SRES,
|
DM_STAT_DP => DM_STAT_DP,
|
DM_STAT_DP => DM_STAT_DP,
|
DM_STAT_VM => DM_STAT_VM,
|
DM_STAT_VM => DM_STAT_VM,
|
DM_STAT_CO => DM_STAT_CO
|
DM_STAT_CO => DM_STAT_CO
|
);
|
);
|
|
|
MEM_BRAM: if sys_conf_bram > 0 generate
|
MEM_BRAM: if sys_conf_bram > 0 generate
|
signal HM_VAL_BRAM : slbit := '0';
|
signal HM_VAL_BRAM : slbit := '0';
|
begin
|
begin
|
|
|
MEM : pdp11_bram
|
MEM : pdp11_bram
|
generic map (
|
generic map (
|
AWIDTH => sys_conf_bram_awidth)
|
AWIDTH => sys_conf_bram_awidth)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
GRESET => CPU_RESET,
|
GRESET => CPU_RESET,
|
EM_MREQ => EM_MREQ,
|
EM_MREQ => EM_MREQ,
|
EM_SRES => EM_SRES
|
EM_SRES => EM_SRES
|
);
|
);
|
|
|
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
|
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
|
|
|
MEM70: pdp11_mem70
|
MEM70: pdp11_mem70
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CRESET => BRESET,
|
CRESET => BRESET,
|
HM_ENA => EM_MREQ.req,
|
HM_ENA => EM_MREQ.req,
|
HM_VAL => HM_VAL_BRAM,
|
HM_VAL => HM_VAL_BRAM,
|
CACHE_FMISS => MEM70_FMISS,
|
CACHE_FMISS => MEM70_FMISS,
|
IB_MREQ => IB_MREQ,
|
IB_MREQ => IB_MREQ,
|
IB_SRES => IB_SRES_MEM70
|
IB_SRES => IB_SRES_MEM70
|
);
|
);
|
|
|
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
|
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
|
port map (
|
port map (
|
O_MEM_CE_N => O_MEM_CE_N,
|
O_MEM_CE_N => O_MEM_CE_N,
|
O_MEM_BE_N => O_MEM_BE_N,
|
O_MEM_BE_N => O_MEM_BE_N,
|
O_MEM_WE_N => O_MEM_WE_N,
|
O_MEM_WE_N => O_MEM_WE_N,
|
O_MEM_OE_N => O_MEM_OE_N,
|
O_MEM_OE_N => O_MEM_OE_N,
|
O_MEM_ADV_N => O_MEM_ADV_N,
|
O_MEM_ADV_N => O_MEM_ADV_N,
|
O_MEM_CLK => O_MEM_CLK,
|
O_MEM_CLK => O_MEM_CLK,
|
O_MEM_CRE => O_MEM_CRE,
|
O_MEM_CRE => O_MEM_CRE,
|
I_MEM_WAIT => I_MEM_WAIT,
|
I_MEM_WAIT => I_MEM_WAIT,
|
O_MEM_ADDR => O_MEM_ADDR,
|
O_MEM_ADDR => O_MEM_ADDR,
|
IO_MEM_DATA => IO_MEM_DATA
|
IO_MEM_DATA => IO_MEM_DATA
|
);
|
);
|
|
|
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
|
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
|
O_PPCM_RST_N <= '1'; --
|
O_PPCM_RST_N <= '1'; --
|
|
|
end generate MEM_BRAM;
|
end generate MEM_BRAM;
|
|
|
MEM_SRAM: if sys_conf_bram = 0 generate
|
MEM_SRAM: if sys_conf_bram = 0 generate
|
|
|
CACHE: pdp11_cache
|
CACHE: pdp11_cache
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
GRESET => CPU_RESET,
|
GRESET => CPU_RESET,
|
EM_MREQ => EM_MREQ,
|
EM_MREQ => EM_MREQ,
|
EM_SRES => EM_SRES,
|
EM_SRES => EM_SRES,
|
FMISS => CACHE_FMISS,
|
FMISS => CACHE_FMISS,
|
CHIT => CACHE_CHIT,
|
CHIT => CACHE_CHIT,
|
MEM_REQ => MEM_REQ,
|
MEM_REQ => MEM_REQ,
|
MEM_WE => MEM_WE,
|
MEM_WE => MEM_WE,
|
MEM_BUSY => MEM_BUSY,
|
MEM_BUSY => MEM_BUSY,
|
MEM_ACK_R => MEM_ACK_R,
|
MEM_ACK_R => MEM_ACK_R,
|
MEM_ADDR => MEM_ADDR,
|
MEM_ADDR => MEM_ADDR,
|
MEM_BE => MEM_BE,
|
MEM_BE => MEM_BE,
|
MEM_DI => MEM_DI,
|
MEM_DI => MEM_DI,
|
MEM_DO => MEM_DO
|
MEM_DO => MEM_DO
|
);
|
);
|
|
|
MEM70: pdp11_mem70
|
MEM70: pdp11_mem70
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CRESET => BRESET,
|
CRESET => BRESET,
|
HM_ENA => HM_ENA,
|
HM_ENA => HM_ENA,
|
HM_VAL => CACHE_CHIT,
|
HM_VAL => CACHE_CHIT,
|
CACHE_FMISS => MEM70_FMISS,
|
CACHE_FMISS => MEM70_FMISS,
|
IB_MREQ => IB_MREQ,
|
IB_MREQ => IB_MREQ,
|
IB_SRES => IB_SRES_MEM70
|
IB_SRES => IB_SRES_MEM70
|
);
|
);
|
|
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
|
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
|
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
|
|
|
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
|
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
|
|
|
SRAM_CTL: nx_cram_memctl_as
|
SRAM_CTL: nx_cram_memctl_as
|
generic map (
|
generic map (
|
READ0DELAY => sys_conf_memctl_read0delay,
|
READ0DELAY => sys_conf_memctl_read0delay,
|
READ1DELAY => sys_conf_memctl_read1delay,
|
READ1DELAY => sys_conf_memctl_read1delay,
|
WRITEDELAY => sys_conf_memctl_writedelay)
|
WRITEDELAY => sys_conf_memctl_writedelay)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
RESET => CPU_RESET,
|
RESET => CPU_RESET,
|
REQ => MEM_REQ,
|
REQ => MEM_REQ,
|
WE => MEM_WE,
|
WE => MEM_WE,
|
BUSY => MEM_BUSY,
|
BUSY => MEM_BUSY,
|
ACK_R => MEM_ACK_R,
|
ACK_R => MEM_ACK_R,
|
ACK_W => open,
|
ACK_W => open,
|
ACT_R => MEM_ACT_R,
|
ACT_R => MEM_ACT_R,
|
ACT_W => MEM_ACT_W,
|
ACT_W => MEM_ACT_W,
|
ADDR => MEM_ADDR_EXT,
|
ADDR => MEM_ADDR_EXT,
|
BE => MEM_BE,
|
BE => MEM_BE,
|
DI => MEM_DI,
|
DI => MEM_DI,
|
DO => MEM_DO,
|
DO => MEM_DO,
|
O_MEM_CE_N => O_MEM_CE_N,
|
O_MEM_CE_N => O_MEM_CE_N,
|
O_MEM_BE_N => O_MEM_BE_N,
|
O_MEM_BE_N => O_MEM_BE_N,
|
O_MEM_WE_N => O_MEM_WE_N,
|
O_MEM_WE_N => O_MEM_WE_N,
|
O_MEM_OE_N => O_MEM_OE_N,
|
O_MEM_OE_N => O_MEM_OE_N,
|
O_MEM_ADV_N => O_MEM_ADV_N,
|
O_MEM_ADV_N => O_MEM_ADV_N,
|
O_MEM_CLK => O_MEM_CLK,
|
O_MEM_CLK => O_MEM_CLK,
|
O_MEM_CRE => O_MEM_CRE,
|
O_MEM_CRE => O_MEM_CRE,
|
I_MEM_WAIT => I_MEM_WAIT,
|
I_MEM_WAIT => I_MEM_WAIT,
|
O_MEM_ADDR => O_MEM_ADDR,
|
O_MEM_ADDR => O_MEM_ADDR,
|
IO_MEM_DATA => IO_MEM_DATA
|
IO_MEM_DATA => IO_MEM_DATA
|
);
|
);
|
|
|
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
|
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
|
O_PPCM_RST_N <= '1'; --
|
O_PPCM_RST_N <= '1'; --
|
|
|
end generate MEM_SRAM;
|
end generate MEM_SRAM;
|
|
|
IB_SRES_OR : ib_sres_or_2
|
IB_SRES_OR : ib_sres_or_2
|
port map (
|
port map (
|
IB_SRES_1 => IB_SRES_MEM70,
|
IB_SRES_1 => IB_SRES_MEM70,
|
IB_SRES_2 => IB_SRES_IBDR,
|
IB_SRES_2 => IB_SRES_IBDR,
|
IB_SRES_OR => IB_SRES
|
IB_SRES_OR => IB_SRES
|
);
|
);
|
|
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IBD_MINI : if false generate
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IBD_MINI : if false generate
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begin
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begin
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IBDR_SYS : ibdr_minisys
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IBDR_SYS : ibdr_minisys
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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RESET => CPU_RESET,
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RESET => CPU_RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RB_LAM => RB_LAM(15 downto 1),
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RB_LAM => RB_LAM(15 downto 1),
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_IBDR,
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IB_SRES => IB_SRES_IBDR,
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EI_ACKM => EI_ACKM,
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EI_ACKM => EI_ACKM,
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EI_PRI => EI_PRI,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT,
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EI_VECT => EI_VECT,
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DISPREG => DISPREG
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DISPREG => DISPREG
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);
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);
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end generate IBD_MINI;
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end generate IBD_MINI;
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|
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IBD_MAXI : if true generate
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IBD_MAXI : if true generate
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begin
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begin
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IBDR_SYS : ibdr_maxisys
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IBDR_SYS : ibdr_maxisys
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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RESET => CPU_RESET,
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RESET => CPU_RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RB_LAM => RB_LAM(15 downto 1),
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RB_LAM => RB_LAM(15 downto 1),
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_IBDR,
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IB_SRES => IB_SRES_IBDR,
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EI_ACKM => EI_ACKM,
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EI_ACKM => EI_ACKM,
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EI_PRI => EI_PRI,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT,
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EI_VECT => EI_VECT,
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DISPREG => DISPREG
|
DISPREG => DISPREG
|
);
|
);
|
end generate IBD_MAXI;
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end generate IBD_MAXI;
|
|
|
IOLEDS : ioleds_sp1c_fx2
|
IOLEDS : ioleds_sp1c_fx2
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CE_USEC => CE_USEC,
|
CE_USEC => CE_USEC,
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RESET => CPU_RESET,
|
RESET => CPU_RESET,
|
ENAFX2 => SWI(2),
|
ENAFX2 => SWI(2),
|
RB_SRES => RB_SRES,
|
RB_SRES => RB_SRES,
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RLB_MONI => RLB_MONI,
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RLB_MONI => RLB_MONI,
|
SER_MONI => SER_MONI,
|
SER_MONI => SER_MONI,
|
IOLEDS => DSP_DP
|
IOLEDS => DSP_DP
|
);
|
);
|
|
|
DSP_DAT(15 downto 0) <= DISPREG;
|
DSP_DAT(15 downto 0) <= DISPREG;
|
|
|
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
|
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
|
variable iled : slv8 := (others=>'0');
|
variable iled : slv8 := (others=>'0');
|
begin
|
begin
|
iled := (others=>'0');
|
iled := (others=>'0');
|
iled(7) := MEM_ACT_W;
|
iled(7) := MEM_ACT_W;
|
iled(6) := MEM_ACT_R;
|
iled(6) := MEM_ACT_R;
|
iled(5) := CP_STAT.cmdbusy;
|
iled(5) := CP_STAT.cmdbusy;
|
if CP_STAT.cpugo = '1' then
|
if CP_STAT.cpugo = '1' then
|
case DM_STAT_DP.psw.cmode is
|
case DM_STAT_DP.psw.cmode is
|
when c_psw_kmode =>
|
when c_psw_kmode =>
|
if CP_STAT.cpuwait = '1' then
|
if CP_STAT.cpuwait = '1' then
|
iled(2) := '1';
|
iled(2) := '1';
|
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
|
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
|
iled(3) := '1';
|
iled(3) := '1';
|
else
|
else
|
iled(4) := '1';
|
iled(4) := '1';
|
end if;
|
end if;
|
when c_psw_smode =>
|
when c_psw_smode =>
|
iled(1) := '1';
|
iled(1) := '1';
|
when c_psw_umode =>
|
when c_psw_umode =>
|
iled(0) := '1';
|
iled(0) := '1';
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
else
|
else
|
iled(4) := '1';
|
iled(4) := '1';
|
iled(3 downto 0) := CP_STAT.cpurust;
|
iled(3 downto 0) := CP_STAT.cpurust;
|
end if;
|
end if;
|
LED <= iled;
|
LED <= iled;
|
end process;
|
end process;
|
|
|
-- synthesis translate_off
|
-- synthesis translate_off
|
DM_STAT_SY.emmreq <= EM_MREQ;
|
DM_STAT_SY.emmreq <= EM_MREQ;
|
DM_STAT_SY.emsres <= EM_SRES;
|
DM_STAT_SY.emsres <= EM_SRES;
|
DM_STAT_SY.chit <= CACHE_CHIT;
|
DM_STAT_SY.chit <= CACHE_CHIT;
|
|
|
TMU : pdp11_tmu_sb
|
TMU : pdp11_tmu_sb
|
generic map (
|
generic map (
|
ENAPIN => 13)
|
ENAPIN => 13)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
DM_STAT_DP => DM_STAT_DP,
|
DM_STAT_DP => DM_STAT_DP,
|
DM_STAT_VM => DM_STAT_VM,
|
DM_STAT_VM => DM_STAT_VM,
|
DM_STAT_CO => DM_STAT_CO,
|
DM_STAT_CO => DM_STAT_CO,
|
DM_STAT_SY => DM_STAT_SY
|
DM_STAT_SY => DM_STAT_SY
|
);
|
);
|
-- synthesis translate_on
|
-- synthesis translate_on
|
|
|
end syn;
|
end syn;
|
|
|