-- $Id: cdc_pulse.vhd 426 2011-11-18 18:14:08Z mueller $
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-- $Id: cdc_pulse.vhd 426 2011-11-18 18:14:08Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: cdc_pulse - syn
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-- Module Name: cdc_pulse - syn
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-- Description: clock domain cross for pulse
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-- Description: clock domain cross for pulse
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-09 422 1.0 Initial version
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-- 2011-11-09 422 1.0 Initial version
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity cdc_pulse is -- clock domain cross for pulse
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entity cdc_pulse is -- clock domain cross for pulse
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generic (
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generic (
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POUT_SINGLE : boolean := false; -- if true: single cycle pout
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POUT_SINGLE : boolean := false; -- if true: single cycle pout
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BUSY_WACK : boolean := false); -- if true: busy waits for ack
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BUSY_WACK : boolean := false); -- if true: busy waits for ack
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port (
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port (
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CLKM : in slbit; -- clock master
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CLKM : in slbit; -- clock master
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RESET : in slbit := '0'; -- M|reset
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RESET : in slbit := '0'; -- M|reset
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CLKS : in slbit; -- clock slave
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CLKS : in slbit; -- clock slave
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PIN : in slbit; -- M|pulse in
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PIN : in slbit; -- M|pulse in
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BUSY : out slbit; -- M|busy
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BUSY : out slbit; -- M|busy
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POUT : out slbit -- S|pulse out
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POUT : out slbit -- S|pulse out
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);
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);
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end entity cdc_pulse;
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end entity cdc_pulse;
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architecture syn of cdc_pulse is
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architecture syn of cdc_pulse is
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signal R_REQ : slbit := '0';
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signal R_REQ : slbit := '0';
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signal R_REQ_C : slbit := '0';
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signal R_REQ_C : slbit := '0';
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signal R_ACK : slbit := '0';
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signal R_ACK : slbit := '0';
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signal R_ACK_C : slbit := '0';
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signal R_ACK_C : slbit := '0';
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signal R_ACK_S : slbit := '0';
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signal R_ACK_S : slbit := '0';
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begin
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begin
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proc_master: process (CLKM)
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proc_master: process (CLKM)
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begin
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begin
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if rising_edge(CLKM) then
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if rising_edge(CLKM) then
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if RESET = '1' then
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if RESET = '1' then
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R_REQ <= '0';
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R_REQ <= '0';
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else
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else
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if PIN = '1' then
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if PIN = '1' then
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R_REQ <= '1';
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R_REQ <= '1';
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elsif R_ACK_S = '1' then
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elsif R_ACK_S = '1' then
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R_REQ <= '0';
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R_REQ <= '0';
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end if;
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end if;
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end if;
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end if;
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R_ACK_C <= R_ACK;
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R_ACK_C <= R_ACK;
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R_ACK_S <= R_ACK_C;
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R_ACK_S <= R_ACK_C;
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end if;
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end if;
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end process proc_master;
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end process proc_master;
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proc_slave: process (CLKS)
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proc_slave: process (CLKS)
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begin
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begin
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if rising_edge(CLKS) then
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if rising_edge(CLKS) then
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R_REQ_C <= R_REQ;
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R_REQ_C <= R_REQ;
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R_ACK <= R_REQ_C;
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R_ACK <= R_REQ_C;
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end if;
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end if;
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end process proc_slave;
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end process proc_slave;
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SINGLE1: if POUT_SINGLE = true generate
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SINGLE1: if POUT_SINGLE = true generate
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signal R_ACK_1 : slbit := '0';
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signal R_ACK_1 : slbit := '0';
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signal R_POUT : slbit := '0';
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signal R_POUT : slbit := '0';
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begin
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begin
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proc_pout: process (CLKS)
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proc_pout: process (CLKS)
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begin
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begin
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if rising_edge(CLKS) then
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if rising_edge(CLKS) then
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R_ACK_1 <= R_ACK;
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R_ACK_1 <= R_ACK;
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if R_ACK='1' and R_ACK_1='0' then
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if R_ACK='1' and R_ACK_1='0' then
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R_POUT <= '1';
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R_POUT <= '1';
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else
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else
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R_POUT <= '0';
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R_POUT <= '0';
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end if;
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end if;
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end if;
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end if;
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end process proc_pout;
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end process proc_pout;
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POUT <= R_POUT;
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POUT <= R_POUT;
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end generate SINGLE1;
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end generate SINGLE1;
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SINGLE0: if POUT_SINGLE = false generate
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SINGLE0: if POUT_SINGLE = false generate
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begin
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begin
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POUT <= R_ACK;
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POUT <= R_ACK;
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end generate SINGLE0;
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end generate SINGLE0;
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BUSY1: if BUSY_WACK = true generate
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BUSY1: if BUSY_WACK = true generate
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begin
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begin
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BUSY <= R_REQ or R_ACK_S;
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BUSY <= R_REQ or R_ACK_S;
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end generate BUSY1;
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end generate BUSY1;
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BUSY0: if BUSY_WACK = false generate
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BUSY0: if BUSY_WACK = false generate
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begin
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begin
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BUSY <= R_REQ;
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BUSY <= R_REQ;
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end generate BUSY0;
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end generate BUSY0;
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end syn;
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end syn;
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