-- $Id: fifo_1c_dram_raw.vhd 421 2011-11-07 21:23:50Z mueller $
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-- $Id: fifo_1c_dram_raw.vhd 421 2011-11-07 21:23:50Z mueller $
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--
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: fifo_1c_dram_raw - syn
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-- Module Name: fifo_1c_dram_raw - syn
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-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
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-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
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-- interface exposing dram signals.
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-- interface exposing dram signals.
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--
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--
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-- Dependencies: ram_1swar_1ar_gen
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-- Dependencies: ram_1swar_1ar_gen
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--
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--
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-- Test bench: tb/tb_fifo_1c_dram
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-- Test bench: tb/tb_fifo_1c_dram
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-- Target Devices: generic Spartan, Virtex
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-07 421 1.0.2 now numeric_std clean
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-- 2011-11-07 421 1.0.2 now numeric_std clean
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-03 47 1.0 Initial version
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-- 2007-06-03 47 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
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entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
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generic (
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generic (
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AWIDTH : positive := 4; -- address width (sets size)
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AWIDTH : positive := 4; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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DWIDTH : positive := 16); -- data width
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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WE : in slbit; -- write enable
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WE : in slbit; -- write enable
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RE : in slbit; -- read enable
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RE : in slbit; -- read enable
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DI : in slv(DWIDTH-1 downto 0); -- input data
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DI : in slv(DWIDTH-1 downto 0); -- input data
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DO : out slv(DWIDTH-1 downto 0); -- output data
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DO : out slv(DWIDTH-1 downto 0); -- output data
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SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
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SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
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EMPTY : out slbit; -- empty flag
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EMPTY : out slbit; -- empty flag
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FULL : out slbit -- full flag
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FULL : out slbit -- full flag
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);
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);
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end fifo_1c_dram_raw;
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end fifo_1c_dram_raw;
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architecture syn of fifo_1c_dram_raw is
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architecture syn of fifo_1c_dram_raw is
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type regs_type is record
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type regs_type is record
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waddr : slv(AWIDTH-1 downto 0); -- write address
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waddr : slv(AWIDTH-1 downto 0); -- write address
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raddr : slv(AWIDTH-1 downto 0); -- read address
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raddr : slv(AWIDTH-1 downto 0); -- read address
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empty : slbit; -- empty flag
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empty : slbit; -- empty flag
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full : slbit; -- full flag
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full : slbit; -- full flag
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end record regs_type;
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end record regs_type;
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constant memsize : positive := 2**AWIDTH;
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constant memsize : positive := 2**AWIDTH;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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slv(to_unsigned(0,AWIDTH)), -- waddr
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slv(to_unsigned(0,AWIDTH)), -- waddr
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slv(to_unsigned(0,AWIDTH)), -- raddr
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slv(to_unsigned(0,AWIDTH)), -- raddr
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'1','0' -- empty,full
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'1','0' -- empty,full
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);
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal RAM_WE : slbit := '0';
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signal RAM_WE : slbit := '0';
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begin
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begin
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RAM : ram_1swar_1ar_gen
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RAM : ram_1swar_1ar_gen
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generic map (
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generic map (
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AWIDTH => AWIDTH,
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AWIDTH => AWIDTH,
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DWIDTH => DWIDTH)
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DWIDTH => DWIDTH)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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WE => RAM_WE,
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WE => RAM_WE,
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ADDRA => R_REGS.waddr,
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ADDRA => R_REGS.waddr,
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ADDRB => R_REGS.raddr,
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ADDRB => R_REGS.raddr,
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DI => DI,
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DI => DI,
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DOA => open,
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DOA => open,
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DOB => DO
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DOB => DO
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next: process (R_REGS, RESET, WE, RE)
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proc_next: process (R_REGS, RESET, WE, RE)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
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variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
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variable we_val : slbit := '0';
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variable we_val : slbit := '0';
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variable re_val : slbit := '0';
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variable re_val : slbit := '0';
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variable iram_we : slbit := '0';
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variable iram_we : slbit := '0';
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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re_val := RE and not r.empty;
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re_val := RE and not r.empty;
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we_val := WE and ((not r.full) or RE);
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we_val := WE and ((not r.full) or RE);
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isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
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isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
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iram_we := '0';
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iram_we := '0';
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if RESET = '1' then
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if RESET = '1' then
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n := regs_init;
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n := regs_init;
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else
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else
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if we_val = '1' then
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if we_val = '1' then
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n.waddr := slv(unsigned(r.waddr) + 1);
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n.waddr := slv(unsigned(r.waddr) + 1);
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iram_we := '1';
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iram_we := '1';
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if re_val = '0' then
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if re_val = '0' then
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n.empty := '0';
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n.empty := '0';
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if unsigned(isize) = memsize-1 then
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if unsigned(isize) = memsize-1 then
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n.full := '1';
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n.full := '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if re_val = '1' then
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if re_val = '1' then
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n.raddr := slv(unsigned(r.raddr) + 1);
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n.raddr := slv(unsigned(r.raddr) + 1);
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if we_val = '0' then
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if we_val = '0' then
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n.full := '0';
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n.full := '0';
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if unsigned(isize) = 1 then
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if unsigned(isize) = 1 then
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n.empty := '1';
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n.empty := '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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RAM_WE <= iram_we;
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RAM_WE <= iram_we;
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SIZE <= isize;
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SIZE <= isize;
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EMPTY <= r.empty;
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EMPTY <= r.empty;
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FULL <= r.full;
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FULL <= r.full;
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end process proc_next;
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end process proc_next;
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end syn;
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end syn;
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