-- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: ram_1swar_1ar_gen - syn
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-- Module Name: ram_1swar_1ar_gen - syn
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-- Description: Dual-Port RAM with with one synchronous write and two
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-- Description: Dual-Port RAM with with one synchronous write and two
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-- asynchronius read ports (as distributed RAM).
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-- asynchronius read ports (as distributed RAM).
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-- Direct instantiation of Xilinx UNISIM primitives
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-- Direct instantiation of Xilinx UNISIM primitives
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's
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-- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's
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-- 2008-03-08 123 1.0.1 use shorter label names
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-- 2008-03-08 123 1.0.1 use shorter label names
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-- 2008-03-02 122 1.0 Initial version
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-- 2008-03-02 122 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.ALL;
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use unisim.vcomponents.ALL;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
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entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
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generic (
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generic (
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AWIDTH : positive := 4; -- address port width
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AWIDTH : positive := 4; -- address port width
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DWIDTH : positive := 16); -- data port width
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DWIDTH : positive := 16); -- data port width
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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WE : in slbit; -- write enable (port A)
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WE : in slbit; -- write enable (port A)
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
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DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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);
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end ram_1swar_1ar_gen;
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end ram_1swar_1ar_gen;
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architecture syn of ram_1swar_1ar_gen is
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architecture syn of ram_1swar_1ar_gen is
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begin
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begin
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assert AWIDTH>=4 and AWIDTH<=5
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assert AWIDTH>=4 and AWIDTH<=5
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report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported"
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report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported"
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severity failure;
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severity failure;
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AW_4: if AWIDTH = 4 generate
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AW_4: if AWIDTH = 4 generate
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GL: for i in DWIDTH-1 downto 0 generate
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GL: for i in DWIDTH-1 downto 0 generate
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MEM : RAM16X1D
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MEM : RAM16X1D
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generic map (
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generic map (
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INIT => X"0000")
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INIT => X"0000")
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port map (
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port map (
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DPO => DOB(i),
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DPO => DOB(i),
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SPO => DOA(i),
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SPO => DOA(i),
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A0 => ADDRA(0),
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A0 => ADDRA(0),
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A1 => ADDRA(1),
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A1 => ADDRA(1),
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A2 => ADDRA(2),
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A2 => ADDRA(2),
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A3 => ADDRA(3),
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A3 => ADDRA(3),
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D => DI(i),
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D => DI(i),
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DPRA0 => ADDRB(0),
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DPRA0 => ADDRB(0),
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DPRA1 => ADDRB(1),
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DPRA1 => ADDRB(1),
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DPRA2 => ADDRB(2),
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DPRA2 => ADDRB(2),
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DPRA3 => ADDRB(3),
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DPRA3 => ADDRB(3),
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WCLK => CLK,
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WCLK => CLK,
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WE => WE
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WE => WE
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);
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);
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end generate GL;
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end generate GL;
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end generate AW_4;
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end generate AW_4;
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-- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge..
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-- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge..
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AW_5: if AWIDTH = 5 generate
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AW_5: if AWIDTH = 5 generate
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signal WE0 : slbit := '0';
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signal WE0 : slbit := '0';
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signal WE1 : slbit := '0';
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signal WE1 : slbit := '0';
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signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0');
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begin
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begin
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WE0 <= WE and not ADDRA(4);
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WE0 <= WE and not ADDRA(4);
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WE1 <= WE and ADDRA(4);
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WE1 <= WE and ADDRA(4);
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GL: for i in DWIDTH-1 downto 0 generate
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GL: for i in DWIDTH-1 downto 0 generate
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MEM0 : RAM16X1D
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MEM0 : RAM16X1D
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generic map (
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generic map (
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INIT => X"0000")
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INIT => X"0000")
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port map (
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port map (
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DPO => DOB0(i),
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DPO => DOB0(i),
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SPO => DOA0(i),
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SPO => DOA0(i),
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A0 => ADDRA(0),
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A0 => ADDRA(0),
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A1 => ADDRA(1),
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A1 => ADDRA(1),
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A2 => ADDRA(2),
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A2 => ADDRA(2),
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A3 => ADDRA(3),
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A3 => ADDRA(3),
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D => DI(i),
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D => DI(i),
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DPRA0 => ADDRB(0),
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DPRA0 => ADDRB(0),
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DPRA1 => ADDRB(1),
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DPRA1 => ADDRB(1),
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DPRA2 => ADDRB(2),
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DPRA2 => ADDRB(2),
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DPRA3 => ADDRB(3),
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DPRA3 => ADDRB(3),
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WCLK => CLK,
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WCLK => CLK,
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WE => WE0
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WE => WE0
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);
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);
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MEM1 : RAM16X1D
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MEM1 : RAM16X1D
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generic map (
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generic map (
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INIT => X"0000")
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INIT => X"0000")
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port map (
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port map (
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DPO => DOB1(i),
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DPO => DOB1(i),
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SPO => DOA1(i),
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SPO => DOA1(i),
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A0 => ADDRA(0),
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A0 => ADDRA(0),
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A1 => ADDRA(1),
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A1 => ADDRA(1),
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A2 => ADDRA(2),
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A2 => ADDRA(2),
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A3 => ADDRA(3),
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A3 => ADDRA(3),
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D => DI(i),
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D => DI(i),
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DPRA0 => ADDRB(0),
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DPRA0 => ADDRB(0),
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DPRA1 => ADDRB(1),
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DPRA1 => ADDRB(1),
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DPRA2 => ADDRB(2),
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DPRA2 => ADDRB(2),
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DPRA3 => ADDRB(3),
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DPRA3 => ADDRB(3),
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WCLK => CLK,
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WCLK => CLK,
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WE => WE1
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WE => WE1
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);
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);
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DOA <= DOA0 when ADDRA(4)='0' else DOA1;
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DOA <= DOA0 when ADDRA(4)='0' else DOA1;
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DOB <= DOB0 when ADDRB(4)='0' else DOB1;
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DOB <= DOB0 when ADDRB(4)='0' else DOB1;
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end generate GL;
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end generate GL;
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end generate AW_5;
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end generate AW_5;
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-- AW_6: if AWIDTH = 6 generate
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-- AW_6: if AWIDTH = 6 generate
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-- GL: for i in DWIDTH-1 downto 0 generate
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-- GL: for i in DWIDTH-1 downto 0 generate
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-- MEM : RAM64X1D
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-- MEM : RAM64X1D
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-- generic map (
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-- generic map (
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-- INIT => X"0000000000000000")
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-- INIT => X"0000000000000000")
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-- port map (
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-- port map (
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-- DPO => DOB(i),
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-- DPO => DOB(i),
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-- SPO => DOA(i),
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-- SPO => DOA(i),
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-- A0 => ADDRA(0),
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-- A0 => ADDRA(0),
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-- A1 => ADDRA(1),
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-- A1 => ADDRA(1),
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-- A2 => ADDRA(2),
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-- A2 => ADDRA(2),
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-- A3 => ADDRA(3),
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-- A3 => ADDRA(3),
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-- A4 => ADDRA(4),
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-- A4 => ADDRA(4),
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-- A5 => ADDRA(5),
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-- A5 => ADDRA(5),
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-- D => DI(i),
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-- D => DI(i),
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-- DPRA0 => ADDRB(0),
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-- DPRA0 => ADDRB(0),
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-- DPRA1 => ADDRB(1),
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-- DPRA1 => ADDRB(1),
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-- DPRA2 => ADDRB(2),
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-- DPRA2 => ADDRB(2),
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-- DPRA3 => ADDRB(3),
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-- DPRA3 => ADDRB(3),
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-- DPRA4 => ADDRB(4),
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-- DPRA4 => ADDRB(4),
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-- DPRA5 => ADDRB(5),
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-- DPRA5 => ADDRB(5),
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-- WCLK => CLK,
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-- WCLK => CLK,
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-- WE => WE
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-- WE => WE
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-- );
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-- );
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-- end generate GL;
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-- end generate GL;
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-- end generate AW_6;
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-- end generate AW_6;
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end syn;
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end syn;
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-- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong.
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-- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong.
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-- The annotation states that DPO is the port A output and SPO is port B
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-- The annotation states that DPO is the port A output and SPO is port B
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-- output. The text before is correct, DPO is port B and SPO is port A.
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-- output. The text before is correct, DPO is port B and SPO is port A.
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