-- $Id: ram_1swar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ram_1swar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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--
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: ram_1swar_gen_unisim - syn
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-- Module Name: ram_1swar_gen_unisim - syn
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-- Description: Single-Port RAM with with one synchronous write and one
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-- Description: Single-Port RAM with with one synchronous write and one
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-- asynchronius read port (as distributed RAM).
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-- asynchronius read port (as distributed RAM).
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-- Direct instantiation of Xilinx UNISIM primitives
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-- Direct instantiation of Xilinx UNISIM primitives
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2008-03-08 123 1.0.1 use shorter label names
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-- 2008-03-08 123 1.0.1 use shorter label names
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-- 2008-03-02 122 1.0 Initial version
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-- 2008-03-02 122 1.0 Initial version
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.ALL;
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use unisim.vcomponents.ALL;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
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entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
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generic (
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generic (
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AWIDTH : positive := 4; -- address port width
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AWIDTH : positive := 4; -- address port width
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DWIDTH : positive := 16); -- data port width
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DWIDTH : positive := 16); -- data port width
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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WE : in slbit; -- write enable
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WE : in slbit; -- write enable
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ADDR : in slv(AWIDTH-1 downto 0); -- address port
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ADDR : in slv(AWIDTH-1 downto 0); -- address port
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DI : in slv(DWIDTH-1 downto 0); -- data in port
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DI : in slv(DWIDTH-1 downto 0); -- data in port
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DO : out slv(DWIDTH-1 downto 0) -- data out port
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DO : out slv(DWIDTH-1 downto 0) -- data out port
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);
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);
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end ram_1swar_gen;
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end ram_1swar_gen;
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architecture syn of ram_1swar_gen is
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architecture syn of ram_1swar_gen is
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begin
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begin
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assert AWIDTH>=4 and AWIDTH<=6
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assert AWIDTH>=4 and AWIDTH<=6
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report "assert(AWIDTH>=4 and AWIDTH<=6): only 4..6 bit AWIDTH supported"
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report "assert(AWIDTH>=4 and AWIDTH<=6): only 4..6 bit AWIDTH supported"
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severity failure;
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severity failure;
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AW_4: if AWIDTH = 4 generate
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AW_4: if AWIDTH = 4 generate
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GL: for i in DWIDTH-1 downto 0 generate
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GL: for i in DWIDTH-1 downto 0 generate
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MEM : RAM16X1S
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MEM : RAM16X1S
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generic map (
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generic map (
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INIT => X"0000")
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INIT => X"0000")
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port map (
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port map (
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O => DO(i),
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O => DO(i),
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A0 => ADDR(0),
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A0 => ADDR(0),
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A1 => ADDR(1),
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A1 => ADDR(1),
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A2 => ADDR(2),
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A2 => ADDR(2),
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A3 => ADDR(3),
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A3 => ADDR(3),
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D => DI(i),
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D => DI(i),
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WCLK => CLK,
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WCLK => CLK,
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WE => WE
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WE => WE
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);
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);
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end generate GL;
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end generate GL;
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end generate AW_4;
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end generate AW_4;
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AW_5: if AWIDTH = 5 generate
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AW_5: if AWIDTH = 5 generate
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GL: for i in DWIDTH-1 downto 0 generate
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GL: for i in DWIDTH-1 downto 0 generate
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MEM : RAM32X1S
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MEM : RAM32X1S
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generic map (
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generic map (
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INIT => X"00000000")
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INIT => X"00000000")
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port map (
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port map (
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O => DO(i),
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O => DO(i),
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A0 => ADDR(0),
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A0 => ADDR(0),
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A1 => ADDR(1),
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A1 => ADDR(1),
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A2 => ADDR(2),
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A2 => ADDR(2),
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A3 => ADDR(3),
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A3 => ADDR(3),
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A4 => ADDR(4),
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A4 => ADDR(4),
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D => DI(i),
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D => DI(i),
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WCLK => CLK,
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WCLK => CLK,
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WE => WE
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WE => WE
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);
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);
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end generate GL;
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end generate GL;
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end generate AW_5;
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end generate AW_5;
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AW_6: if AWIDTH = 6 generate
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AW_6: if AWIDTH = 6 generate
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GL: for i in DWIDTH-1 downto 0 generate
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GL: for i in DWIDTH-1 downto 0 generate
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MEM : RAM64X1S
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MEM : RAM64X1S
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generic map (
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generic map (
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INIT => X"0000000000000000")
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INIT => X"0000000000000000")
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port map (
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port map (
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O => DO(i),
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O => DO(i),
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A0 => ADDR(0),
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A0 => ADDR(0),
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A1 => ADDR(1),
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A1 => ADDR(1),
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A2 => ADDR(2),
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A2 => ADDR(2),
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A3 => ADDR(3),
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A3 => ADDR(3),
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A4 => ADDR(4),
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A4 => ADDR(4),
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A5 => ADDR(5),
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A5 => ADDR(5),
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D => DI(i),
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D => DI(i),
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WCLK => CLK,
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WCLK => CLK,
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WE => WE
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WE => WE
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);
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);
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end generate GL;
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end generate GL;
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end generate AW_6;
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end generate AW_6;
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end syn;
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end syn;
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