-- $Id: ram_2swsr_rfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ram_2swsr_rfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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--
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: ram_2swsr_rfirst_gen - syn
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-- Module Name: ram_2swsr_rfirst_gen - syn
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-- Description: Dual-Port RAM with with two synchronous read/write ports
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-- Description: Dual-Port RAM with with two synchronous read/write ports
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-- and 'read-before-write' semantics (as block RAM).
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-- and 'read-before-write' semantics (as block RAM).
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-- Direct instantiation of Xilinx UNISIM primitives
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-- Direct instantiation of Xilinx UNISIM primitives
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: Spartan-3, Virtex-2,-4
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-- Target Devices: Spartan-3, Virtex-2,-4
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
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-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
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-- 2008-03-02 122 1.0 Initial version
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-- 2008-03-02 122 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.ALL;
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use unisim.vcomponents.ALL;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
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entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
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generic (
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generic (
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AWIDTH : positive := 13; -- address port width 11/9 or 13/8
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AWIDTH : positive := 13; -- address port width 11/9 or 13/8
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DWIDTH : positive := 8); -- data port width
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DWIDTH : positive := 8); -- data port width
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port(
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port(
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CLKA : in slbit; -- clock port A
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CLKA : in slbit; -- clock port A
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CLKB : in slbit; -- clock port B
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CLKB : in slbit; -- clock port B
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ENA : in slbit; -- enable port A
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ENA : in slbit; -- enable port A
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ENB : in slbit; -- enable port B
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ENB : in slbit; -- enable port B
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WEA : in slbit; -- write enable port A
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WEA : in slbit; -- write enable port A
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WEB : in slbit; -- write enable port B
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WEB : in slbit; -- write enable port B
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DIA : in slv(DWIDTH-1 downto 0); -- data in port A
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DIA : in slv(DWIDTH-1 downto 0); -- data in port A
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DIB : in slv(DWIDTH-1 downto 0); -- data in port B
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DIB : in slv(DWIDTH-1 downto 0); -- data in port B
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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);
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end ram_2swsr_rfirst_gen;
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end ram_2swsr_rfirst_gen;
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architecture syn of ram_2swsr_rfirst_gen is
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architecture syn of ram_2swsr_rfirst_gen is
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begin
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begin
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UMEM: ram_2swsr_xfirst_gen_unisim
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UMEM: ram_2swsr_xfirst_gen_unisim
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generic map (
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generic map (
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AWIDTH => AWIDTH,
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AWIDTH => AWIDTH,
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DWIDTH => DWIDTH,
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DWIDTH => DWIDTH,
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WRITE_MODE => "READ_FIRST")
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WRITE_MODE => "READ_FIRST")
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port map (
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port map (
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CLKA => CLKA,
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CLKA => CLKA,
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CLKB => CLKB,
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CLKB => CLKB,
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ENA => ENA,
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ENA => ENA,
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ENB => ENB,
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ENB => ENB,
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WEA => WEA,
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WEA => WEA,
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WEB => WEB,
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WEB => WEB,
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ADDRA => ADDRA,
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ADDRA => ADDRA,
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ADDRB => ADDRB,
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ADDRB => ADDRB,
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DIA => DIA,
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DIA => DIA,
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DIB => DIB,
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DIB => DIB,
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DOA => DOA,
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DOA => DOA,
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DOB => DOB
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DOB => DOB
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);
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);
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end syn;
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end syn;
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