-- $Id: rlink_core8.vhd 440 2011-12-18 20:08:09Z mueller $
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-- $Id: rlink_core8.vhd 440 2011-12-18 20:08:09Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rlink_core8 - syn
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-- Module Name: rlink_core8 - syn
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-- Description: rlink core with 8bit interface (core+b2c/c2b+rlmon+rbmon)
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-- Description: rlink core with 8bit interface (core+b2c/c2b+rlmon+rbmon)
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--
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--
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-- Dependencies: rlink_core
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-- Dependencies: rlink_core
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-- comlib/byte2cdata
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-- comlib/byte2cdata
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-- comlib/cdata2byte
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-- comlib/cdata2byte
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-- rlink_mon_sb [sim only]
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-- rlink_mon_sb [sim only]
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-- rbus/rb_mon_sb [sim only]
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-- rbus/rb_mon_sb [sim only]
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--
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--
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-- Test bench: -
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-- Test bench: -
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Tool versions: xst 13.1; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-12-09 437 13.1 O40d xc3s1000-4 184 403 0 244 s 9.1
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-- 2011-12-09 437 13.1 O40d xc3s1000-4 184 403 0 244 s 9.1
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-09 437 1.0 Initial version
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-- 2011-12-09 437 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.comlib.all;
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use work.comlib.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.rlinklib.all;
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entity rlink_core8 is -- rlink core with 8bit interface
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entity rlink_core8 is -- rlink core with 8bit interface
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generic (
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generic (
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ATOWIDTH : positive := 5; -- access timeout counter width
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ATOWIDTH : positive := 5; -- access timeout counter width
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ITOWIDTH : positive := 6; -- idle timeout counter width
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ITOWIDTH : positive := 6; -- idle timeout counter width
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
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ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
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CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RLB_DI : in slv8; -- rlink 8b: data in
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RLB_DI : in slv8; -- rlink 8b: data in
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RLB_ENA : in slbit; -- rlink 8b: data enable
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RLB_ENA : in slbit; -- rlink 8b: data enable
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RLB_BUSY : out slbit; -- rlink 8b: data busy
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RLB_BUSY : out slbit; -- rlink 8b: data busy
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RLB_DO : out slv8; -- rlink 8b: data out
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RLB_DO : out slv8; -- rlink 8b: data out
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RLB_VAL : out slbit; -- rlink 8b: data valid
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RLB_VAL : out slbit; -- rlink 8b: data valid
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RLB_HOLD : in slbit; -- rlink 8b: data hold
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RLB_HOLD : in slbit; -- rlink 8b: data hold
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RL_MONI : out rl_moni_type; -- rlink: monitor port
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RL_MONI : out rl_moni_type; -- rlink: monitor port
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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RB_STAT : in slv3 -- rbus: status flags
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);
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);
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end entity rlink_core8;
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end entity rlink_core8;
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architecture syn of rlink_core8 is
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architecture syn of rlink_core8 is
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signal RL_DI : slv9 := (others=>'0');
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signal RL_DI : slv9 := (others=>'0');
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signal RL_ENA : slbit := '0';
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signal RL_ENA : slbit := '0';
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signal RL_BUSY : slbit := '0';
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signal RL_BUSY : slbit := '0';
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signal RL_DO : slv9 := (others=>'0');
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signal RL_DO : slv9 := (others=>'0');
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signal RL_VAL : slbit := '0';
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signal RL_VAL : slbit := '0';
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signal RL_HOLD : slbit := '0';
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signal RL_HOLD : slbit := '0';
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signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ
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signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ
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begin
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begin
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RL : rlink_core
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RL : rlink_core
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generic map (
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generic map (
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ATOWIDTH => ATOWIDTH,
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ATOWIDTH => ATOWIDTH,
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ITOWIDTH => ITOWIDTH)
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ITOWIDTH => ITOWIDTH)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_INT => CE_INT,
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CE_INT => CE_INT,
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RESET => RESET,
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RESET => RESET,
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RL_DI => RL_DI,
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RL_DI => RL_DI,
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RL_ENA => RL_ENA,
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RL_ENA => RL_ENA,
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RL_BUSY => RL_BUSY,
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RL_BUSY => RL_BUSY,
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RL_DO => RL_DO,
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RL_DO => RL_DO,
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RL_VAL => RL_VAL,
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RL_VAL => RL_VAL,
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RL_HOLD => RL_HOLD,
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RL_HOLD => RL_HOLD,
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RL_MONI => RL_MONI,
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RL_MONI => RL_MONI,
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RB_MREQ => RB_MREQ_L,
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RB_MREQ => RB_MREQ_L,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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RB_STAT => RB_STAT
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);
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);
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RB_MREQ <= RB_MREQ_L;
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RB_MREQ <= RB_MREQ_L;
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-- RLB -> RL converter (DI handling) -------------
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-- RLB -> RL converter (DI handling) -------------
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B2CD : byte2cdata -- byte stream -> 9bit comma,data
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B2CD : byte2cdata -- byte stream -> 9bit comma,data
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generic map (
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generic map (
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CPREF => CPREF,
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CPREF => CPREF,
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NCOMM => c_rlink_ncomm)
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NCOMM => c_rlink_ncomm)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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DI => RLB_DI,
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DI => RLB_DI,
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ENA => RLB_ENA,
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ENA => RLB_ENA,
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BUSY => RLB_BUSY,
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BUSY => RLB_BUSY,
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DO => RL_DI,
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DO => RL_DI,
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VAL => RL_ENA,
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VAL => RL_ENA,
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HOLD => RL_BUSY
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HOLD => RL_BUSY
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);
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);
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-- RL -> RLB converter (DO handling) -------------
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-- RL -> RLB converter (DO handling) -------------
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CD2B : cdata2byte -- 9bit comma,data -> byte stream
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CD2B : cdata2byte -- 9bit comma,data -> byte stream
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generic map (
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generic map (
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CPREF => CPREF,
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CPREF => CPREF,
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NCOMM => c_rlink_ncomm)
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NCOMM => c_rlink_ncomm)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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DI => RL_DO,
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DI => RL_DO,
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ENA => RL_VAL,
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ENA => RL_VAL,
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BUSY => RL_HOLD,
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BUSY => RL_HOLD,
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DO => RLB_DO,
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DO => RLB_DO,
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VAL => RLB_VAL,
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VAL => RLB_VAL,
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HOLD => RLB_HOLD
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HOLD => RLB_HOLD
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);
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);
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-- synthesis translate_off
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-- synthesis translate_off
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RLMON: if ENAPIN_RLMON >= 0 generate
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RLMON: if ENAPIN_RLMON >= 0 generate
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MON : rlink_mon_sb
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MON : rlink_mon_sb
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generic map (
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generic map (
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DWIDTH => RL_DI'length,
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DWIDTH => RL_DI'length,
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ENAPIN => ENAPIN_RLMON)
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ENAPIN => ENAPIN_RLMON)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RL_DI => RL_DI,
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RL_DI => RL_DI,
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RL_ENA => RL_ENA,
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RL_ENA => RL_ENA,
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RL_BUSY => RL_BUSY,
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RL_BUSY => RL_BUSY,
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RL_DO => RL_DO,
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RL_DO => RL_DO,
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RL_VAL => RL_VAL,
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RL_VAL => RL_VAL,
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RL_HOLD => RL_HOLD
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RL_HOLD => RL_HOLD
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);
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);
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end generate RLMON;
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end generate RLMON;
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RBMON: if ENAPIN_RBMON >= 0 generate
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RBMON: if ENAPIN_RBMON >= 0 generate
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MON : rb_mon_sb
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MON : rb_mon_sb
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generic map (
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generic map (
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DBASE => 8,
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DBASE => 8,
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ENAPIN => ENAPIN_RBMON)
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ENAPIN => ENAPIN_RBMON)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RB_MREQ => RB_MREQ_L,
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RB_MREQ => RB_MREQ_L,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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RB_STAT => RB_STAT
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);
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);
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end generate RBMON;
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end generate RBMON;
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-- synthesis translate_on
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-- synthesis translate_on
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end syn;
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end syn;
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