-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
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-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: sn_humanio_demu - syn
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-- Module Name: sn_humanio_demu - syn
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-- Description: All BTN, SWI, LED handling for atlys
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-- Description: All BTN, SWI, LED handling for atlys
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--
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--
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-- Dependencies: bpgen/bp_swibtnled
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-- Dependencies: bpgen/bp_swibtnled
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--
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--
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-- Test bench: -
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-- Test bench: -
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Tool versions: xst 13.1; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
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-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
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-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
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-- 2011-10-10 413 1.0 Initial version
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-- 2011-10-10 413 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.bpgenlib.all;
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use work.bpgenlib.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
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entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
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generic (
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generic (
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DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
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DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RESET : in slbit := '0'; -- reset
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CE_MSEC : in slbit; -- 1 ms clock enable
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CE_MSEC : in slbit; -- 1 ms clock enable
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SWI : out slv8; -- switch settings, debounced
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SWI : out slv8; -- switch settings, debounced
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BTN : out slv4; -- button settings, debounced
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BTN : out slv4; -- button settings, debounced
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LED : in slv8; -- led data
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LED : in slv8; -- led data
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DSP_DAT : in slv16; -- display data
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DSP_DAT : in slv16; -- display data
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DSP_DP : in slv4; -- display decimal points
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DSP_DP : in slv4; -- display decimal points
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I_SWI : in slv8; -- pad-i: switches
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I_SWI : in slv8; -- pad-i: switches
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I_BTN : in slv6; -- pad-i: buttons
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I_BTN : in slv6; -- pad-i: buttons
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O_LED : out slv8 -- pad-o: leds
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O_LED : out slv8 -- pad-o: leds
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);
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);
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end sn_humanio_demu;
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end sn_humanio_demu;
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architecture syn of sn_humanio_demu is
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architecture syn of sn_humanio_demu is
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constant c_mode_led : slv2 := "00";
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constant c_mode_led : slv2 := "00";
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constant c_mode_dp : slv2 := "01";
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constant c_mode_dp : slv2 := "01";
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constant c_mode_datl : slv2 := "10";
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constant c_mode_datl : slv2 := "10";
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constant c_mode_dath : slv2 := "11";
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constant c_mode_dath : slv2 := "11";
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type regs_type is record
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type regs_type is record
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mode : slv2; -- current mode
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mode : slv2; -- current mode
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cnt : slv9; -- msec counter
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cnt : slv9; -- msec counter
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up_1 : slbit; -- btn up last cycle
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up_1 : slbit; -- btn up last cycle
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dn_1 : slbit; -- btn dn last cycle
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dn_1 : slbit; -- btn dn last cycle
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led : slv8; -- led state
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led : slv8; -- led state
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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c_mode_led, -- mode
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c_mode_led, -- mode
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(others=>'0'), -- cnt
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(others=>'0'), -- cnt
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'0','0', -- up_1, dn_1
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'0','0', -- up_1, dn_1
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(others=>'0') -- led
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(others=>'0') -- led
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);
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal BTN_HW : slv6 := (others=>'0');
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signal BTN_HW : slv6 := (others=>'0');
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signal LED_HW : slv8 := (others=>'0');
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signal LED_HW : slv8 := (others=>'0');
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begin
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begin
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HIO : bp_swibtnled
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HIO : bp_swibtnled
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generic map (
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generic map (
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SWIDTH => 8,
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SWIDTH => 8,
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BWIDTH => 6,
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BWIDTH => 6,
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LWIDTH => 8,
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LWIDTH => 8,
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DEBOUNCE => DEBOUNCE)
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DEBOUNCE => DEBOUNCE)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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SWI => SWI,
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SWI => SWI,
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BTN => BTN_HW,
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BTN => BTN_HW,
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LED => LED_HW,
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LED => LED_HW,
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I_SWI => I_SWI,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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I_BTN => I_BTN,
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O_LED => O_LED
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O_LED => O_LED
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
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proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibtn : slv4 := (others=>'0');
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variable ibtn : slv4 := (others=>'0');
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variable iup : slbit := '0';
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variable iup : slbit := '0';
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variable idn : slbit := '0';
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variable idn : slbit := '0';
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variable ipuls : slbit := '0';
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variable ipuls : slbit := '0';
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
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ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
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ibtn(1) := BTN_HW(1);
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ibtn(1) := BTN_HW(1);
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ibtn(2) := BTN_HW(4);
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ibtn(2) := BTN_HW(4);
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ibtn(3) := BTN_HW(3);
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ibtn(3) := BTN_HW(3);
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iup := BTN_HW(0);
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iup := BTN_HW(0);
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idn := BTN_HW(2);
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idn := BTN_HW(2);
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ipuls := '0';
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ipuls := '0';
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n.up_1 := iup;
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n.up_1 := iup;
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n.dn_1 := idn;
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n.dn_1 := idn;
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if iup='0' and idn='0' then
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if iup='0' and idn='0' then
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n.cnt := (others=>'0');
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n.cnt := (others=>'0');
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else
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else
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if CE_MSEC = '1' then
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if CE_MSEC = '1' then
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n.cnt := slv(unsigned(r.cnt) + 1);
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n.cnt := slv(unsigned(r.cnt) + 1);
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if r.cnt = "111111111" then
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if r.cnt = "111111111" then
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ipuls := '1';
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ipuls := '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if iup='1' or idn='1' then
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if iup='1' or idn='1' then
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n.led := (others=>'0');
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n.led := (others=>'0');
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case r.mode is
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case r.mode is
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when c_mode_led => n.led(0) := '1';
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when c_mode_led => n.led(0) := '1';
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when c_mode_dp => n.led(1) := '1';
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when c_mode_dp => n.led(1) := '1';
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when c_mode_datl => n.led(2) := '1';
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when c_mode_datl => n.led(2) := '1';
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when c_mode_dath => n.led(3) := '1';
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when c_mode_dath => n.led(3) := '1';
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when others => null;
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when others => null;
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end case;
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end case;
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if iup='1' and (r.up_1='0' or ipuls='1') then
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if iup='1' and (r.up_1='0' or ipuls='1') then
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n.mode := slv(unsigned(r.mode) + 1);
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n.mode := slv(unsigned(r.mode) + 1);
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elsif idn='1' and (r.dn_1='0' or ipuls='1') then
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elsif idn='1' and (r.dn_1='0' or ipuls='1') then
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n.mode := slv(unsigned(r.mode) - 1);
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n.mode := slv(unsigned(r.mode) - 1);
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end if;
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end if;
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else
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else
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case r.mode is
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case r.mode is
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when c_mode_led => n.led := LED;
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when c_mode_led => n.led := LED;
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when c_mode_dp => n.led := "0000" & DSP_DP;
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when c_mode_dp => n.led := "0000" & DSP_DP;
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when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
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when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
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when c_mode_dath => n.led := DSP_DAT(15 downto 8);
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when c_mode_dath => n.led := DSP_DAT(15 downto 8);
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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BTN <= ibtn;
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BTN <= ibtn;
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LED_HW <= r.led;
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LED_HW <= r.led;
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end process proc_next;
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end process proc_next;
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end syn;
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end syn;
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