-- $Id: serport_xontx.vhd 476 2013-01-26 22:23:53Z mueller $
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-- $Id: serport_xontx.vhd 476 2013-01-26 22:23:53Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: serport_xontx - syn
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-- Module Name: serport_xontx - syn
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-- Description: serial port: xon/xoff logic tx path
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-- Description: serial port: xon/xoff logic tx path
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-13 425 1.0 Initial version
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-- 2011-11-13 425 1.0 Initial version
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-- 2011-10-22 417 0.5 First draft
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-- 2011-10-22 417 0.5 First draft
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.serportlib.all;
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use work.serportlib.all;
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entity serport_xontx is -- serial port: xon/xoff logic tx path
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entity serport_xontx is -- serial port: xon/xoff logic tx path
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAESC : in slbit; -- enable xon/xoff escaping
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ENAESC : in slbit; -- enable xon/xoff escaping
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UART_TXDATA : out slv8; -- uart data in
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UART_TXDATA : out slv8; -- uart data in
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UART_TXENA : out slbit; -- uart data enable
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UART_TXENA : out slbit; -- uart data enable
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UART_TXBUSY : in slbit; -- uart data busy
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UART_TXBUSY : in slbit; -- uart data busy
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TXDATA : in slv8; -- user data in
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TXDATA : in slv8; -- user data in
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TXENA : in slbit; -- user data enable
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TXENA : in slbit; -- user data enable
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TXBUSY : out slbit; -- user data busy
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TXBUSY : out slbit; -- user data busy
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RXOK : in slbit; -- rx channel ok
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RXOK : in slbit; -- rx channel ok
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TXOK : in slbit -- tx channel ok
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TXOK : in slbit -- tx channel ok
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);
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);
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end serport_xontx;
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end serport_xontx;
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architecture syn of serport_xontx is
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architecture syn of serport_xontx is
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type regs_type is record
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type regs_type is record
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ibuf : slv8; -- input buffer
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ibuf : slv8; -- input buffer
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ival : slbit; -- ibuf has valid data
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ival : slbit; -- ibuf has valid data
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obuf : slv8; -- output buffer
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obuf : slv8; -- output buffer
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oval : slbit; -- obuf has valid data
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oval : slbit; -- obuf has valid data
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rxok : slbit; -- rx channel ok state
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rxok : slbit; -- rx channel ok state
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enaxon_1 : slbit; -- last enaxon
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enaxon_1 : slbit; -- last enaxon
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escpend : slbit; -- escape pending
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escpend : slbit; -- escape pending
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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(others=>'0'),'0', -- ibuf,ival
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(others=>'0'),'0', -- ibuf,ival
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(others=>'0'),'0', -- obuf,oval
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(others=>'0'),'0', -- obuf,oval
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'1', -- rxok (startup default is ok !!)
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'1', -- rxok (startup default is ok !!)
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'0', -- enaxon_1
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'0', -- enaxon_1
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'0' -- escpend
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'0' -- escpend
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);
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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begin
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
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proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
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TXDATA, TXENA, RXOK, TXOK)
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TXDATA, TXENA, RXOK, TXOK)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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if TXENA='1' and r.ival='0' then
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if TXENA='1' and r.ival='0' then
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n.ibuf := TXDATA;
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n.ibuf := TXDATA;
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n.ival := '1';
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n.ival := '1';
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end if;
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end if;
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if r.oval = '0' then
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if r.oval = '0' then
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if ENAXON='1' and r.rxok/=RXOK then
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if ENAXON='1' and r.rxok/=RXOK then
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n.rxok := RXOK;
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n.rxok := RXOK;
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n.oval := '1';
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n.oval := '1';
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if r.rxok = '0' then
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if r.rxok = '0' then
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n.obuf := c_serport_xon;
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n.obuf := c_serport_xon;
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else
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else
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n.obuf := c_serport_xoff;
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n.obuf := c_serport_xoff;
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end if;
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end if;
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elsif TXOK = '1' then
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elsif TXOK = '1' then
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if r.escpend = '1' then
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if r.escpend = '1' then
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n.obuf := not r.ibuf;
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n.obuf := not r.ibuf;
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n.oval := '1';
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n.oval := '1';
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n.escpend := '0';
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n.escpend := '0';
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n.ival := '0';
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n.ival := '0';
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elsif r.ival = '1' then
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elsif r.ival = '1' then
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if ENAESC='1' and (r.ibuf=c_serport_xon or
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if ENAESC='1' and (r.ibuf=c_serport_xon or
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r.ibuf=c_serport_xoff or
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r.ibuf=c_serport_xoff or
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r.ibuf=c_serport_xesc)
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r.ibuf=c_serport_xesc)
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then
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then
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n.obuf := c_serport_xesc;
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n.obuf := c_serport_xesc;
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n.oval := '1';
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n.oval := '1';
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n.escpend := '1';
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n.escpend := '1';
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else
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else
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n.obuf := r.ibuf;
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n.obuf := r.ibuf;
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n.oval := '1';
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n.oval := '1';
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n.ival := '0';
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n.ival := '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if r.oval='1' and UART_TXBUSY='0' then
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if r.oval='1' and UART_TXBUSY='0' then
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n.oval := '0';
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n.oval := '0';
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end if;
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end if;
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-- FIXME: document this hack
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-- FIXME: document this hack
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n.enaxon_1 := ENAXON;
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n.enaxon_1 := ENAXON;
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if ENAXON='1' and r.enaxon_1='0' then
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if ENAXON='1' and r.enaxon_1='0' then
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n.rxok := not RXOK;
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n.rxok := not RXOK;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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TXBUSY <= r.ival;
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TXBUSY <= r.ival;
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UART_TXDATA <= r.obuf;
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UART_TXDATA <= r.obuf;
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UART_TXENA <= r.oval;
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UART_TXENA <= r.oval;
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end process proc_next;
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end process proc_next;
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end syn;
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end syn;
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