# $Id: test_rbtest_sim.tcl 516 2013-05-05 21:24:52Z mueller $
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# $Id: test_rbtest_sim.tcl 516 2013-05-05 21:24:52Z mueller $
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#
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#
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# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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#
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# This program is free software; you may redistribute and/or modify it under
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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# Software Foundation, either version 2, or at your option any later version.
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#
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#
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# This program is distributed in the hope that it will be useful, but
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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# for complete details.
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2011-04-17 376 1.0 Initial version
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# 2011-04-17 376 1.0 Initial version
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#
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#
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package provide rbemon 1.0
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package provide rbemon 1.0
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package require rbtest
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package require rbtest
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namespace eval rbemon {
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namespace eval rbemon {
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#
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#
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# some simple tests against rbd_tester registers in sim mode
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# some simple tests against rbd_tester registers in sim mode
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#
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#
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proc test_rbtest_sim {} {
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proc test_rbtest_sim {} {
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set esdval 0x00
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set esdval 0x00
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set esdmsk [regbld rlink::STAT {stat -1}]
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set esdmsk [regbld rlink::STAT {stat -1}]
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#
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#
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set errcnt 0
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set errcnt 0
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rlc errcnt -clear
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rlc errcnt -clear
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#
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#
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rlc log "rbemon::test_rbtest_sim - start"
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rlc log "rbemon::test_rbtest_sim - start"
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#
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#
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#-------------------------------------------------------------------------
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#-------------------------------------------------------------------------
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rlc log " test 1: write to te.data, verify that transitions seen"
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rlc log " test 1: write to te.data, verify that transitions seen"
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set bsize 25
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set bsize 25
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#
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#
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rlc exec -wreg em.rdiv 0 -estat $esdval $esdmsk
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rlc exec -wreg em.rdiv 0 -estat $esdval $esdmsk
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rlc log " - data - 01 10 va00 va01 va02 va03 va04 va05 va06 va07 va08 va09"
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rlc log " - data - 01 10 va00 va01 va02 va03 va04 va05 va06 va07 va08 va09"
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#
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#
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# Note: avoid chars which will be escpaped, like 10000000, for this test
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# Note: avoid chars which will be escpaped, like 10000000, for this test
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#
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#
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foreach {pat ena01 ena10 exp} \
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foreach {pat ena01 ena10 exp} \
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[list [bvi b 00000000] 1 1 [list 0 0 0 0 0 0 0 0 1 0]\
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[list [bvi b 00000000] 1 1 [list 0 0 0 0 0 0 0 0 1 0]\
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[bvi b 00000001] 1 1 [list 1 1 0 0 0 0 0 0 1 0]\
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[bvi b 00000001] 1 1 [list 1 1 0 0 0 0 0 0 1 0]\
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[bvi b 00000010] 1 1 [list 0 1 1 0 0 0 0 0 1 0]\
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[bvi b 00000010] 1 1 [list 0 1 1 0 0 0 0 0 1 0]\
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[bvi b 00000100] 1 1 [list 0 0 1 1 0 0 0 0 1 0]\
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[bvi b 00000100] 1 1 [list 0 0 1 1 0 0 0 0 1 0]\
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[bvi b 00001000] 1 1 [list 0 0 0 1 1 0 0 0 1 0]\
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[bvi b 00001000] 1 1 [list 0 0 0 1 1 0 0 0 1 0]\
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[bvi b 00010000] 1 1 [list 0 0 0 0 1 1 0 0 1 0]\
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[bvi b 00010000] 1 1 [list 0 0 0 0 1 1 0 0 1 0]\
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[bvi b 00100000] 1 1 [list 0 0 0 0 0 1 1 0 1 0]\
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[bvi b 00100000] 1 1 [list 0 0 0 0 0 1 1 0 1 0]\
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[bvi b 01000000] 1 1 [list 0 0 0 0 0 0 1 1 1 0]\
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[bvi b 01000000] 1 1 [list 0 0 0 0 0 0 1 1 1 0]\
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[bvi b 11111111] 1 1 [list 1 0 0 0 0 0 0 0 0 0]\
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[bvi b 11111111] 1 1 [list 1 0 0 0 0 0 0 0 0 0]\
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[bvi b 11111110] 1 1 [list 0 1 0 0 0 0 0 0 0 0]\
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[bvi b 11111110] 1 1 [list 0 1 0 0 0 0 0 0 0 0]\
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[bvi b 01010101] 1 1 [list 1 1 1 1 1 1 1 1 1 0]\
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[bvi b 01010101] 1 1 [list 1 1 1 1 1 1 1 1 1 0]\
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[bvi b 00110011] 1 1 [list 1 0 1 0 1 0 1 0 1 0]\
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[bvi b 00110011] 1 1 [list 1 0 1 0 1 0 1 0 1 0]\
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[bvi b 00000001] 0 1 [list 0 1 0 0 0 0 0 0 0 0]\
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[bvi b 00000001] 0 1 [list 0 1 0 0 0 0 0 0 0 0]\
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[bvi b 00000001] 1 0 [list 1 0 0 0 0 0 0 0 1 0]\
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[bvi b 00000001] 1 0 [list 1 0 0 0 0 0 0 0 1 0]\
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[bvi b 01010101] 0 1 [list 0 1 0 1 0 1 0 1 0 0]\
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[bvi b 01010101] 0 1 [list 0 1 0 1 0 1 0 1 0 0]\
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[bvi b 01010101] 1 0 [list 1 0 1 0 1 0 1 0 1 0]\
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[bvi b 01010101] 1 0 [list 1 0 1 0 1 0 1 0 1 0]\
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] {
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] {
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set bdata {}
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set bdata {}
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for {set i 0} {$i < $bsize} {incr i} {
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for {set i 0} {$i < $bsize} {incr i} {
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lappend bdata [expr {( $pat << 8 ) | $pat}]
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lappend bdata [expr {( $pat << 8 ) | $pat}]
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}
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}
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rbemon::clear
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rbemon::clear
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rbemon::start $ena01 $ena10
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rbemon::start $ena01 $ena10
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rlc exec -wblk te.data $bdata -estat $esdval $esdmsk
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rlc exec -wblk te.data $bdata -estat $esdval $esdmsk
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rbemon::stop
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rbemon::stop
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set edata [rbemon::read 10]
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set edata [rbemon::read 10]
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set oline " "
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set oline " "
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set pafa "OK"
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set pafa "OK"
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append oline [pbvi b8 $pat]
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append oline [pbvi b8 $pat]
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append oline [format " %d %d" $ena01 $ena10]
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append oline [format " %d %d" $ena01 $ena10]
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for {set i 0} {$i < 10} {incr i} {
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for {set i 0} {$i < 10} {incr i} {
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set ebin [lindex $edata $i]
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set ebin [lindex $edata $i]
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set eexp [lindex $exp $i]
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set eexp [lindex $exp $i]
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append oline [format " %3d" $ebin]
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append oline [format " %3d" $ebin]
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if {($eexp != 0 && $ebin < 2 * $bsize) ||
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if {($eexp != 0 && $ebin < 2 * $bsize) ||
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($eexp == 0 && $ebin >= 2 * $bsize)} {
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($eexp == 0 && $ebin >= 2 * $bsize)} {
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append oline "#"
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append oline "#"
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set pafa "FAIL"
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set pafa "FAIL"
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incr errcnt
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incr errcnt
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} else {
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} else {
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append oline "!"
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append oline "!"
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}
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}
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}
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}
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append oline " "
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append oline " "
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append oline $pafa
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append oline $pafa
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rlc log $oline
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rlc log $oline
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}
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}
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#
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#
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#-------------------------------------------------------------------------
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#-------------------------------------------------------------------------
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incr errcnt [rlc errcnt -clear]
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incr errcnt [rlc errcnt -clear]
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return $errcnt
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return $errcnt
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}
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}
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}
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}
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