# $Id: util.tcl 516 2013-05-05 21:24:52Z mueller $
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# $Id: util.tcl 516 2013-05-05 21:24:52Z mueller $
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#
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#
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# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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#
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# This program is free software; you may redistribute and/or modify it under
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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# Software Foundation, either version 2, or at your option any later version.
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#
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#
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# This program is distributed in the hope that it will be useful, but
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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# for complete details.
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2011-03-27 374 1.0 Initial version
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# 2011-03-27 374 1.0 Initial version
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# 2011-03-13 369 0.1 Frist draft
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# 2011-03-13 369 0.1 Frist draft
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#
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#
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package provide rbtest 1.0
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package provide rbtest 1.0
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package require rutiltpp
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package require rutiltpp
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package require rutil
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package require rutil
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package require rlink
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package require rlink
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namespace eval rbtest {
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namespace eval rbtest {
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#
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#
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# setup register descriptions for rbd_tester
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# setup register descriptions for rbd_tester
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#
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#
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regdsc CNTL {nofifo 15} {stat 14 3} {nbusy 9 10}
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regdsc CNTL {nofifo 15} {stat 14 3} {nbusy 9 10}
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regdsc INIT {fifo 2} {data 1} {cntl 0}
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regdsc INIT {fifo 2} {data 1} {cntl 0}
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#
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#
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# setup: amap definitions for rbd_tester
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# setup: amap definitions for rbd_tester
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#
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#
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proc setup {{base 0x00f0}} {
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proc setup {{base 0x00f0}} {
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rlc amap -insert te.cntl [expr {$base + 0x00}]
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rlc amap -insert te.cntl [expr {$base + 0x00}]
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rlc amap -insert te.data [expr {$base + 0x01}]
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rlc amap -insert te.data [expr {$base + 0x01}]
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rlc amap -insert te.fifo [expr {$base + 0x02}]
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rlc amap -insert te.fifo [expr {$base + 0x02}]
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rlc amap -insert te.attn [expr {$base + 0x03}]
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rlc amap -insert te.attn [expr {$base + 0x03}]
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}
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}
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#
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#
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# init: reset rbd_tester (clear via init)
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# init: reset rbd_tester (clear via init)
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#
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#
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proc init {} {
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proc init {} {
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rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl]
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rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl]
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}
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}
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#
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#
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# nbusymax: returns maximal nbusy value not causing timeout
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# nbusymax: returns maximal nbusy value not causing timeout
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#
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#
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proc nbusymax {} {
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proc nbusymax {} {
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set esdmsk [regbld rlink::STAT {stat -1} attn]
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set esdmsk [regbld rlink::STAT {stat -1} attn]
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rlc exec -estatdef 0 $esdmsk \
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rlc exec -estatdef 0 $esdmsk \
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-rreg te.cntl sav_cntl \
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-rreg te.cntl sav_cntl \
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-wreg te.cntl [regbld rbtest::CNTL {nbusy -1}] \
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-wreg te.cntl [regbld rbtest::CNTL {nbusy -1}] \
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-rreg te.data -estat [regbld rlink::STAT rbnak] $esdmsk \
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-rreg te.data -estat [regbld rlink::STAT rbnak] $esdmsk \
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-rreg te.attn ncyc
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-rreg te.attn ncyc
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rlc exec -estatdef 0 $esdmsk \
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rlc exec -estatdef 0 $esdmsk \
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-wreg te.cntl $sav_cntl
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-wreg te.cntl $sav_cntl
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return [expr {$ncyc - 1}]
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return [expr {$ncyc - 1}]
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}
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}
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#
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#
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# probe: determine rbd_tester environment (max nbusy, stat and attn wiring)
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# probe: determine rbd_tester environment (max nbusy, stat and attn wiring)
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#
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#
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proc probe {} {
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proc probe {} {
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set esdval 0x00
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set esdval 0x00
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set esdmsk [regbld rlink::STAT {stat -1}]
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set esdmsk [regbld rlink::STAT {stat -1}]
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set esdmsknak [regbld rlink::STAT {stat -1} rbnak]
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set esdmsknak [regbld rlink::STAT {stat -1} rbnak]
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set esdmskatt [regbld rlink::STAT {stat -1} attn]
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set esdmskatt [regbld rlink::STAT {stat -1} attn]
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set rbusy {}
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set rbusy {}
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set rstat {}
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set rstat {}
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set rattn {}
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set rattn {}
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#
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#
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# probe max nbusy for write and read
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# probe max nbusy for write and read
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#
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#
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set wrerr {}
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set wrerr {}
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set rderr {}
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set rderr {}
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for {set i 3} { $i < 8 } {incr i} {
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for {set i 3} { $i < 8 } {incr i} {
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set nbusy0 [expr {( 1 << $i )}]
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set nbusy0 [expr {( 1 << $i )}]
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for {set j -1} { $j <= 1 } {incr j} {
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for {set j -1} { $j <= 1 } {incr j} {
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set nbusy [expr {$nbusy0 + $j}]
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set nbusy [expr {$nbusy0 + $j}]
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set valc [regbld rbtest::CNTL [list nbusy $nbusy]]
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set valc [regbld rbtest::CNTL [list nbusy $nbusy]]
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rlc exec \
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rlc exec \
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-wreg te.cntl $valc -estat $esdval $esdmsk\
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-wreg te.cntl $valc -estat $esdval $esdmsk\
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-wreg te.data 0x0000 statwr -estat $esdval $esdmsknak \
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-wreg te.data 0x0000 statwr -estat $esdval $esdmsknak \
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-rreg te.data dummy statrd -estat $esdval $esdmsknak
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-rreg te.data dummy statrd -estat $esdval $esdmsknak
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if {[llength $wrerr] == 0 && [regget rlink::STAT(rbnak) $statwr] != 0} {
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if {[llength $wrerr] == 0 && [regget rlink::STAT(rbnak) $statwr] != 0} {
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lappend wrerr $i $j $nbusy
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lappend wrerr $i $j $nbusy
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}
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}
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if {[llength $rderr] == 0 && [regget rlink::STAT(rbnak) $statrd] != 0} {
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if {[llength $rderr] == 0 && [regget rlink::STAT(rbnak) $statrd] != 0} {
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lappend rderr $i $j $nbusy
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lappend rderr $i $j $nbusy
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}
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}
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}
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}
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}
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}
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rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl]
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rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl]
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lappend rbusy $wrerr $rderr
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lappend rbusy $wrerr $rderr
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#
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#
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# probe stat wiring
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# probe stat wiring
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#
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#
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for {set i 0} { $i < 3 } {incr i} {
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for {set i 0} { $i < 3 } {incr i} {
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set valc [regbld rbtest::CNTL [list stat [expr {1 << $i}]]]
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set valc [regbld rbtest::CNTL [list stat [expr {1 << $i}]]]
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rlc exec -estatdef $esdval $esdmsk \
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rlc exec -estatdef $esdval $esdmsk \
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-wreg te.cntl $valc \
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-wreg te.cntl $valc \
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-rreg te.data dummy statrd
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-rreg te.data dummy statrd
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lappend rstat [list $i [regget rlink::STAT(stat) $statrd]]
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lappend rstat [list $i [regget rlink::STAT(stat) $statrd]]
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}
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}
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rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl]
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rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl]
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#
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#
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# probe attn wiring
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# probe attn wiring
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#
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#
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rlc exec -attn
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rlc exec -attn
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for {set i 0} { $i < 16 } {incr i} {
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for {set i 0} { $i < 16 } {incr i} {
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rlc exec -estatdef $esdval $esdmskatt \
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rlc exec -estatdef $esdval $esdmskatt \
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-wreg te.attn [expr {1 << $i}] \
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-wreg te.attn [expr {1 << $i}] \
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-attn attnpat
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-attn attnpat
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lappend rattn [list $i $attnpat]
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lappend rattn [list $i $attnpat]
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}
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}
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rlc exec -attn
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rlc exec -attn
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#
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#
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return [list $rbusy $rstat $rattn]
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return [list $rbusy $rstat $rattn]
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}
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}
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#
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#
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# probe_print: print probe results
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# probe_print: print probe results
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#
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#
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proc probe_print {{plist {}}} {
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proc probe_print {{plist {}}} {
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set rval {}
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set rval {}
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if {[llength $plist] == 0} {
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if {[llength $plist] == 0} {
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set plist [probe]
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set plist [probe]
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}
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}
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set rbusy [lindex $plist 0]
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set rbusy [lindex $plist 0]
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set rstat [lindex $plist 1]
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set rstat [lindex $plist 1]
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set rattn [lindex $plist 2]
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set rattn [lindex $plist 2]
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#
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#
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append rval \
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append rval \
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"nbusy: write max [lindex $rbusy 0 2] --> WIDTH=[lindex $rbusy 0 0]"
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"nbusy: write max [lindex $rbusy 0 2] --> WIDTH=[lindex $rbusy 0 0]"
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append rval \
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append rval \
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"\nnbusy: read max [lindex $rbusy 1 2] --> WIDTH=[lindex $rbusy 1 0]"
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"\nnbusy: read max [lindex $rbusy 1 2] --> WIDTH=[lindex $rbusy 1 0]"
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#
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#
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for {set i 0} { $i < 3 } {incr i} {
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for {set i 0} { $i < 3 } {incr i} {
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set rcvpat [lindex $rstat $i 1]
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set rcvpat [lindex $rstat $i 1]
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set rcvind [print_bitind $rcvpat]
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set rcvind [print_bitind $rcvpat]
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append rval [format "\nstat: te.cntl line %2d --> design %2d %s" \
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append rval [format "\nstat: te.cntl line %2d --> design %2d %s" \
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$i $rcvind [pbvi b3 $rcvpat]]
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$i $rcvind [pbvi b3 $rcvpat]]
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}
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}
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#
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#
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for {set i 0} { $i < 16 } {incr i} {
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for {set i 0} { $i < 16 } {incr i} {
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set rcvpat [lindex $rattn $i 1]
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set rcvpat [lindex $rattn $i 1]
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set rcvind [print_bitind $rcvpat]
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set rcvind [print_bitind $rcvpat]
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append rval [format "\nattn: te.attn line %2d --> design %2d %s" \
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append rval [format "\nattn: te.attn line %2d --> design %2d %s" \
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$i $rcvind [pbvi b16 $rcvpat]]
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$i $rcvind [pbvi b16 $rcvpat]]
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}
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}
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return $rval
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return $rval
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}
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}
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#
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#
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# print_bitind: helper for probe_print:
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# print_bitind: helper for probe_print:
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#
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#
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proc print_bitind {pat} {
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proc print_bitind {pat} {
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for {set i 0} { $i < 16 } {incr i} {
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for {set i 0} { $i < 16 } {incr i} {
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if {[expr {$pat & [expr {1 << $i}] }] } { return $i}
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if {[expr {$pat & [expr {1 << $i}] }] } { return $i}
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}
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}
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return -1
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return -1
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}
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}
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}
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}
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