# $Id: defs.tcl 553 2014-03-17 06:40:08Z mueller $
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# $Id: defs.tcl 553 2014-03-17 06:40:08Z mueller $
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#
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#
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# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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#
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# This program is free software; you may redistribute and/or modify it under
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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# Software Foundation, either version 2, or at your option any later version.
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#
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#
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# This program is distributed in the hope that it will be useful, but
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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# for complete details.
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2014-03-07 553 1.0 Initial version (extracted from util.tcl)
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# 2014-03-07 553 1.0 Initial version (extracted from util.tcl)
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#
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#
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package provide rw11 1.0
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package provide rw11 1.0
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package require rlink
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package require rlink
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package require rwxxtpp
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package require rwxxtpp
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namespace eval rw11 {
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namespace eval rw11 {
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#
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#
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# setup cp interface register descriptions for w11a -----------------------
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# setup cp interface register descriptions for w11a -----------------------
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#
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#
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regdsc CP_CNTL {func 3 0}
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regdsc CP_CNTL {func 3 0}
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regdsc CP_STAT {rust 7 4} {halt 3} {go 2} {merr 1} {err 0}
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regdsc CP_STAT {rust 7 4} {halt 3} {go 2} {merr 1} {err 0}
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regdsc CP_IBRB {base 12 7} {bw 1 2}
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regdsc CP_IBRB {base 12 7} {bw 1 2}
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regdsc CP_AH {ubm 7} {p22 6} {addr 5 6}
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regdsc CP_AH {ubm 7} {p22 6} {addr 5 6}
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#
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#
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# setup w11a register descriptions -----------------------------------------
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# setup w11a register descriptions -----------------------------------------
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#
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#
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# PSW - processor status word --------------------------------------
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# PSW - processor status word --------------------------------------
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set A_PSW 0177776
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set A_PSW 0177776
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regdsc PSW {cmode 15 2} {pmode 13 2} {rset 11} {pri 7 3} {tflag 3} {cc 3 4}
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regdsc PSW {cmode 15 2} {pmode 13 2} {rset 11} {pri 7 3} {tflag 3} {cc 3 4}
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#
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#
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# SSR0 - MMU Segment Status Register #0 ----------------------------
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# SSR0 - MMU Segment Status Register #0 ----------------------------
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set A_SSR0 0177572
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set A_SSR0 0177572
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regdsc SSR0 {abo_nonres 15} {abo_len 14} {abo_rd 13} \
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regdsc SSR0 {abo_nonres 15} {abo_len 14} {abo_rd 13} \
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{trap_mmu 12} {ena_trap 9} {inst_compl 7} \
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{trap_mmu 12} {ena_trap 9} {inst_compl 7} \
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{mode 6 2} {dspace 4} {num 3 3} {ena 0}
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{mode 6 2} {dspace 4} {num 3 3} {ena 0}
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#
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#
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# SSR1 - MMU Segment Status Register #1 ----------------------------
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# SSR1 - MMU Segment Status Register #1 ----------------------------
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set A_SSR1 0177574
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set A_SSR1 0177574
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regdsc SSR1 {delta1 15 5} {rnum1 10 3} {delta0 7 5} {rnum0 2 3}
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regdsc SSR1 {delta1 15 5} {rnum1 10 3} {delta0 7 5} {rnum0 2 3}
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#
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#
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# SSR2 - MMU Segment Status Register #2 ----------------------------
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# SSR2 - MMU Segment Status Register #2 ----------------------------
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set A_SSR2 0177576
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set A_SSR2 0177576
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#
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#
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# SSR3 - MMU Segment Status Register #3 ----------------------------
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# SSR3 - MMU Segment Status Register #3 ----------------------------
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set A_SSR3 0172516
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set A_SSR3 0172516
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regdsc SSR3 {ena_ubm 5} {ena_22bit 4} {d_km 2} {d_sm 1} {d_um 0}
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regdsc SSR3 {ena_ubm 5} {ena_22bit 4} {d_km 2} {d_sm 1} {d_um 0}
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#
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#
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# SAR/SDR - MMU Address/Segment Descriptor Register ----------------
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# SAR/SDR - MMU Address/Segment Descriptor Register ----------------
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set A_SDR_KM 0172300
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set A_SDR_KM 0172300
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set A_SAR_KM 0172340
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set A_SAR_KM 0172340
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set A_SDR_SM 0172200
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set A_SDR_SM 0172200
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set A_SAR_SM 0172240
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set A_SAR_SM 0172240
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set A_SDR_UM 0177600
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set A_SDR_UM 0177600
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set A_SAR_UM 0177640
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set A_SAR_UM 0177640
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regdsc SDR {slf 14 7} {aia 7} {aiw 6} {ed 3} {acf 2 3}
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regdsc SDR {slf 14 7} {aia 7} {aiw 6} {ed 3} {acf 2 3}
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#
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#
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# PIRQ - Program Interrupt Requests -------------------------------
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# PIRQ - Program Interrupt Requests -------------------------------
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set A_PIRQ 0177772
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set A_PIRQ 0177772
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regdsc PIRQ {pir 15 7} {piah 7 3} {pial 3 3}
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regdsc PIRQ {pir 15 7} {piah 7 3} {pial 3 3}
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#
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#
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# CPUERR - CPU Error Register -------------------------------------
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# CPUERR - CPU Error Register -------------------------------------
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set A_CPUERR 0177766
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set A_CPUERR 0177766
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regdsc CPUERR {illhlt 7} {adderr 6} {nxm 5} {iobto 4} {ysv 3} {rsv 2}
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regdsc CPUERR {illhlt 7} {adderr 6} {nxm 5} {iobto 4} {ysv 3} {rsv 2}
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#
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#
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# other w11a definitions ---------------------------------------------------
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# other w11a definitions ---------------------------------------------------
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# Interrupt vectors -----------------------------------------------
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# Interrupt vectors -----------------------------------------------
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#
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#
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set V_004 0000004
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set V_004 0000004
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set V_010 0000010
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set V_010 0000010
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set V_BPT 0000014
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set V_BPT 0000014
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set V_IOT 0000020
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set V_IOT 0000020
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set V_PWR 0000024
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set V_PWR 0000024
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set V_EMT 0000030
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set V_EMT 0000030
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set V_TRAP 0000034
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set V_TRAP 0000034
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set V_PIRQ 0000240
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set V_PIRQ 0000240
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set V_FPU 0000244
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set V_FPU 0000244
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set V_MMU 0000250
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set V_MMU 0000250
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}
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}
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