# $Id: w11a_tb_guide.txt 688 2015-06-05 13:15:10Z mueller $
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# $Id: w11a_tb_guide.txt 688 2015-06-05 13:15:10Z mueller $
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Note: Only ISE based test benches are currently documented !
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Note: Only ISE based test benches are currently documented !
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The Vivado test environemnt is still in it's infancy !
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The Vivado test environemnt is still in it's infancy !
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Guide to running w11a test benches
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Guide to running w11a test benches
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Table of content:
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Table of content:
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1. Unit tests benches
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1. Unit tests benches
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2. Available unit tests benches
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2. Available unit tests benches
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3. System tests benches
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3. System tests benches
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4. Available system tests benches
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4. Available system tests benches
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1. Unit tests benches -----------------------------------------------------
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1. Unit tests benches -----------------------------------------------------
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All unit test benches have the same simple structure:
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All unit test benches have the same simple structure:
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- a stimulus process reads test patterns as well as the expected
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- a stimulus process reads test patterns as well as the expected
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responses from a stimulus file
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responses from a stimulus file
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- the responses are checked in very simple cases by the stimulus process,
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- the responses are checked in very simple cases by the stimulus process,
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in general by a monitoring process
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in general by a monitoring process
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- the test bench produces a comprehensive log file. For each checked
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- the test bench produces a comprehensive log file. For each checked
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response the line contains the word "CHECK" and either an "OK" or a
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response the line contains the word "CHECK" and either an "OK" or a
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"FAIL", in the later case in general with an indication of whats wrong.
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"FAIL", in the later case in general with an indication of whats wrong.
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Other unexpected behaviour, like timeouts, will also result in a line
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Other unexpected behaviour, like timeouts, will also result in a line
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containing the word "FAIL".
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containing the word "FAIL".
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- at the end a line with the word "DONE" is printed.
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- at the end a line with the word "DONE" is printed.
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- the test bench is run like
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- the test bench is run like
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tbw [stimfile] | tee | egrep "(FAIL|DONE)"
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tbw [stimfile] | tee | egrep "(FAIL|DONE)"
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where
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where
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- 'tbw' is a small perl script setting up a symbolic link to the
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- 'tbw' is a small perl script setting up a symbolic link to the
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stimulus file, the default extracted from the file tbw.dat, if
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stimulus file, the default extracted from the file tbw.dat, if
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an optional file name is give this one will be used instead.
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an optional file name is give this one will be used instead.
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- 'tee' ensures that the full log is saved
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- 'tee' ensures that the full log is saved
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- 'egrep' filters FAIL and DONE lines, a successful run will
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- 'egrep' filters FAIL and DONE lines, a successful run will
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produce a single DONE line
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produce a single DONE line
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- Most tests can be run against
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- Most tests can be run against
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- the functional model
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- the functional model
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- gate level models at three stages
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- gate level models at three stages
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- the post-xst model (produced by netgen from ngc xst output)
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- the post-xst model (produced by netgen from ngc xst output)
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- the post-map model (produced by netgen from ncd ngdbuild output)
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- the post-map model (produced by netgen from ncd ngdbuild output)
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- the post-par model (produced by netgen from ncd par output)
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- the post-par model (produced by netgen from ncd par output)
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This is simply done using
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This is simply done using
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make _ssim for post-xst
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make _ssim for post-xst
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make _fsim for post-map
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make _fsim for post-map
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make _tsim for post-par
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make _tsim for post-par
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all the rest is handled by the build environment.
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all the rest is handled by the build environment.
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An example of a post-synthesis model is given for the w11a core test.
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An example of a post-synthesis model is given for the w11a core test.
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- for convenience a wrapper script 'tbrun_tbw' is used to generate the
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- for convenience a wrapper script 'tbrun_tbw' is used to generate the
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tbw|tee|egrep pipe. This script also checks with 'make' whether the
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tbw|tee|egrep pipe. This script also checks with 'make' whether the
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test bench is up-to-date or must be (re)-compiled.
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test bench is up-to-date or must be (re)-compiled.
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2. Available unit tests benches -------------------------------------------
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2. Available unit tests benches -------------------------------------------
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In the following the available tests are listed with their tbrun_tbw which
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In the following the available tests are listed with their tbrun_tbw which
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- will call 'make' to build them
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- will call 'make' to build them
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- and create the pipe setup to run them
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- and create the pipe setup to run them
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and the expected output (the run time measured on a 3 GHz system)
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and the expected output (the run time measured on a 3 GHz system)
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- serport receiver test
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- serport receiver test
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cd $RETROBASE/rtl/vlib/serport/tb
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cd $RETROBASE/rtl/vlib/serport/tb
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tbrun_tbw tb_serport_uart_rx
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tbrun_tbw tb_serport_uart_rx
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-> 1269955.0 ns 63488: DONE
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-> 1269955.0 ns 63488: DONE
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-> real 0m01.178s user 0m01.172s sys 0m00.020s
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-> real 0m01.178s user 0m01.172s sys 0m00.020s
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- serport receiver/transmitter test
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- serport receiver/transmitter test
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tbrun_tbw tb_serport_uart_rxtx
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tbrun_tbw tb_serport_uart_rxtx
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-> 52335.0 ns 2607: DONE
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-> 52335.0 ns 2607: DONE
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-> real 0m00.094s user 0m00.092s sys 0m00.008s
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-> real 0m00.094s user 0m00.092s sys 0m00.008s
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- serport autobauder test
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- serport autobauder test
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tbrun_tbw tb_serport_autobaud
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tbrun_tbw tb_serport_autobaud
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-> 367475.0 ns 18364: DONE
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-> 367475.0 ns 18364: DONE
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-> real 0m00.610s user 0m00.612s sys 0m00.004s
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-> real 0m00.610s user 0m00.612s sys 0m00.004s
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- 9 bit comma,data to Byte stream converter test
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- 9 bit comma,data to Byte stream converter test
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cd $RETROBASE/rtl/vlib/comlib/tb
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cd $RETROBASE/rtl/vlib/comlib/tb
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tbrun_tbw tb_cdata2byte
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tbrun_tbw tb_cdata2byte
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-> 7261.0 ns 354: DONE
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-> 7261.0 ns 354: DONE
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-> real 0m0.385s user 0m0.041s sys 0m0.006s
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-> real 0m0.385s user 0m0.041s sys 0m0.006s
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- rlink core test
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- rlink core test
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cd $RETROBASE/rtl/vlib/rlink/tb
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cd $RETROBASE/rtl/vlib/rlink/tb
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tbrun_tbw tb_rlink_direct
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tbrun_tbw tb_rlink_direct
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-> 78975.0 ns 3939: DONE
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-> 78975.0 ns 3939: DONE
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-> real 0m00.508s user 0m00.262s sys 0m00.028s
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-> real 0m00.508s user 0m00.262s sys 0m00.028s
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- rlink core test via serial port interface
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- rlink core test via serial port interface
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cd $RETROBASE/rtl/vlib/rlink/tb
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cd $RETROBASE/rtl/vlib/rlink/tb
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tbrun_tbw --lsuf stim2_dsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat
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tbrun_tbw --lsuf stim2_dsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat
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-> 27595.0 ns 1370: DONE
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-> 27595.0 ns 1370: DONE
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-> real 0m0.250s user 0m0.108s sys 0m0.011s
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-> real 0m0.250s user 0m0.108s sys 0m0.011s
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tbrun_tbw --lsuf stim1_dsim tb_rlink_sp1c tb_rlink_stim.dat
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tbrun_tbw --lsuf stim1_dsim tb_rlink_sp1c tb_rlink_stim.dat
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-> 420295.0 ns 21005: DONE
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-> 420295.0 ns 21005: DONE
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-> real 0m02.271s user 0m01.360s sys 0m00.040s
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-> real 0m02.271s user 0m01.360s sys 0m00.040s
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- w11a core test (using behavioural model)
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- w11a core test (using behavioural model)
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cd $RETROBASE/rtl/w11a/tb
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cd $RETROBASE/rtl/w11a/tb
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tbrun_tbw tb_pdp11core
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tbrun_tbw tb_pdp11core
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-> 1220255.0 ns 61073: DONE
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-> 1220255.0 ns 61073: DONE
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-> real 0m10.736s user 0m10.713s sys 0m00.060s
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-> real 0m10.736s user 0m10.713s sys 0m00.060s
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- w11a core test (using post-synthesis model)
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- w11a core test (using post-synthesis model)
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tbrun_tbw tb_pdp11core_ssim
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tbrun_tbw tb_pdp11core_ssim
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-> 1220255.0 ns 61073: DONE
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-> 1220255.0 ns 61073: DONE
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-> real 1m09.738s user 1m09.588s sys 0m00.096s
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-> real 1m09.738s user 1m09.588s sys 0m00.096s
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- s3board sram controller test
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- s3board sram controller test
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cd $RETROBASE/rtl/bplib/s3board/tb
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cd $RETROBASE/rtl/bplib/s3board/tb
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tbrun_tbw tb_s3_sram_memctl
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tbrun_tbw tb_s3_sram_memctl
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-> 5015.0 ns 241: DONE
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-> 5015.0 ns 241: DONE
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-> real 0m00.113s user 0m00.068s sys 0m00.016s
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-> real 0m00.113s user 0m00.068s sys 0m00.016s
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- nexys2/nexys3 cram controller test
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- nexys2/nexys3 cram controller test
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cd $RETROBASE/rtl/bplib/nxcramlib/tb
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cd $RETROBASE/rtl/bplib/nxcramlib/tb
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tbrun_tbw tb_nx_cram_memctl_as
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tbrun_tbw tb_nx_cram_memctl_as
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-> 24272.5 ns 1204: DONE
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-> 24272.5 ns 1204: DONE
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-> real 0m00.343s user 0m00.248s sys 0m00.100s
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-> real 0m00.343s user 0m00.248s sys 0m00.100s
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3. System tests benches ---------------------------------------------------
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3. System tests benches ---------------------------------------------------
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The system tests allow to verify to verify a full system design.
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The system tests allow to verify to verify a full system design.
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In this case vhdl test bench code contains
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In this case vhdl test bench code contains
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- (simple) models of the memories used on the FPGA boards
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- (simple) models of the memories used on the FPGA boards
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- drivers for the rlink connection (currently just serialport)
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- drivers for the rlink connection (currently just serialport)
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- code to interface the rlink data stream to a UNIX 'named pipe',
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- code to interface the rlink data stream to a UNIX 'named pipe',
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implemented with a C routine which is called via VHPI from VHDL.
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implemented with a C routine which is called via VHPI from VHDL.
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This way the whole ghdl simulation can be controlled via a di-directional
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This way the whole ghdl simulation can be controlled via a di-directional
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byte stream.
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byte stream.
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The rlink backend process can connect either via a named pipe to a ghdl
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The rlink backend process can connect either via a named pipe to a ghdl
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simulation, or via a serial port to a FPGA board. This way the same tests
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simulation, or via a serial port to a FPGA board. This way the same tests
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can be executed in simulation and on real hardware.
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can be executed in simulation and on real hardware.
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4. Available system tests benches -----------------------------------------
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4. Available system tests benches -----------------------------------------
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4a. serport tester ---------------------------------------------------
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4a. serport tester ---------------------------------------------------
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The sys_tst_serloop design is a test target for validating the serial
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The sys_tst_serloop design is a test target for validating the serial
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link UART stack. Send and receive throughput as well as loop-back tests
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link UART stack. Send and receive throughput as well as loop-back tests
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are supported
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are supported
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- sys_tst_serloop_s3 test bench
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- sys_tst_serloop_s3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
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cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
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tbrun_tbw tb_tst_serloop_s3
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tbrun_tbw tb_tst_serloop_s3
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-> 301353.3 ns 18068: DONE
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-> 301353.3 ns 18068: DONE
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-> real 0m1.422s user 0m1.372s sys 0m0.024s
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-> real 0m1.422s user 0m1.372s sys 0m0.024s
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- sys_tst_serloop_n2 test bench
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- sys_tst_serloop_n2 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
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tbrun_tbw tb_tst_serloop1_n2
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tbrun_tbw tb_tst_serloop1_n2
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-> 361560.0 ns 18068: DONE
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-> 361560.0 ns 18068: DONE
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-> real 0m1.341s user 0m1.340s sys 0m0.016s
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-> real 0m1.341s user 0m1.340s sys 0m0.016s
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tbrun_tbw tb_tst_serloop2_n2
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tbrun_tbw tb_tst_serloop2_n2
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-> 304353.3 ns 18248: DONE
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-> 304353.3 ns 18248: DONE
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-> real 0m1.933s user 0m1.924s sys 0m0.024s
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-> real 0m1.933s user 0m1.924s sys 0m0.024s
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- sys_tst_serloop_n3 test bench
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- sys_tst_serloop_n3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
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tbrun_tbw tb_tst_serloop1_n3
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tbrun_tbw tb_tst_serloop1_n3
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-> 361560.0 ns 18068: DONE
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-> 361560.0 ns 18068: DONE
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-> real 0m1.371s user 0m1.372s sys 0m0.016s
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-> real 0m1.371s user 0m1.372s sys 0m0.016s
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4b. rlink tester -----------------------------------------------------
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4b. rlink tester -----------------------------------------------------
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The sys_tst_rlink design is a test target for validating the rlink
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The sys_tst_rlink design is a test target for validating the rlink
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and rbus functionality at all levels.
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and rbus functionality at all levels.
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- sys_tst_rlink_s3 test bench
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- sys_tst_rlink_s3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
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tbrun_tbwrri --pack tst_rlink tb_tst_rlink_s3 \
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tbrun_tbwrri --pack tst_rlink tb_tst_rlink_s3 \
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"tst_rlink::setup" "tst_rlink::test_all"
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"tst_rlink::setup" "tst_rlink::test_all"
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-> 1377680.0 ns 68874: DONE
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-> 1377680.0 ns 68874: DONE
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-> real 0m6.876s user 0m6.790s sys 0m0.060s
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-> real 0m6.876s user 0m6.790s sys 0m0.060s
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- sys_tst_rlink_n2 test bench
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- sys_tst_rlink_n2 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
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tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n2 \
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tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n2 \
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"tst_rlink::setup" "tst_rlink::test_all"
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"tst_rlink::setup" "tst_rlink::test_all"
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-> 1378200.0 ns 68899: DONE
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-> 1378200.0 ns 68899: DONE
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-> real 0m10.320s user 0m10.110s sys 0m0.204s
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-> real 0m10.320s user 0m10.110s sys 0m0.204s
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- sys_tst_rlink_n3 test bench
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- sys_tst_rlink_n3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
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tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n3 \
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tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n3 \
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"tst_rlink::setup" "tst_rlink::test_all"
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"tst_rlink::setup" "tst_rlink::test_all"
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-> 689210.0 ns 68900: DONE
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-> 689210.0 ns 68900: DONE
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-> real 0m7.098s user 0m6.874s sys 0m0.191s
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-> real 0m7.098s user 0m6.874s sys 0m0.191s
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4c. w11a systems -----------------------------------------------------
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4c. w11a systems -----------------------------------------------------
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The stimulus file used in the w11a core test can be executed in the
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The stimulus file used in the w11a core test can be executed in the
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full system context (both s3board and nexys2 versions) with the
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full system context (both s3board and nexys2 versions) with the
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following commands. Note that the cycle number printed in the DONE
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following commands. Note that the cycle number printed in the DONE
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line can now vary slightly because the response time of the rlink
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line can now vary slightly because the response time of the rlink
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backend process and thus scheduling of backend vs. ghdl process
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backend process and thus scheduling of backend vs. ghdl process
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can affect the result.
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can affect the result.
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For convenience a wrapper script 'tbrun_tbwrri' is used to generate the
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For convenience a wrapper script 'tbrun_tbwrri' is used to generate the
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required quite long ti_rri command. Like for 'tbrun_tbw' the script also
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required quite long ti_rri command. Like for 'tbrun_tbw' the script also
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checks with 'make' whether the test bench is up-to-date or must be
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checks with 'make' whether the test bench is up-to-date or must be
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(re)-compiled.
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(re)-compiled.
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- sys_w11a_s3 test bench
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- sys_w11a_s3 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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tbrun_tbwrri --pack rw11 tb_w11a_s3 \
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tbrun_tbwrri --pack rw11 tb_w11a_s3 \
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"rw11::setup_cpu" \
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"rw11::setup_cpu" \
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
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-> 9864500.0 ns 493215: DONE
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-> 9864500.0 ns 493215: DONE
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-> real 0m59.728s user 0m58.586s sys 0m0.576s
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-> real 0m59.728s user 0m58.586s sys 0m0.576s
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- sys_w11a_n2 test bench
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- sys_w11a_n2 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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tbrun_tbwrri --pack rw11 --cuff tb_w11a_n2 \
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tbrun_tbwrri --pack rw11 --cuff tb_w11a_n2 \
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"rw11::setup_cpu" \
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"rw11::setup_cpu" \
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
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-> 3809180.0 ns 190448: DONE
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-> 3809180.0 ns 190448: DONE
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-> real 0m55.733s user 0m55.504s sys 0m0.592s
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-> real 0m55.733s user 0m55.504s sys 0m0.592s
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- sys_w11a_n3 test bench
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- sys_w11a_n3 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
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tbrun_tbwrri --pack rw11 --cuff tb_w11a_n3 \
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tbrun_tbwrri --pack rw11 --cuff tb_w11a_n3 \
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"rw11::setup_cpu" \
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"rw11::setup_cpu" \
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
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"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
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-> 279834.9 ns 236133: DONE
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-> 279834.9 ns 236133: DONE
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-> real 0m59.998s user 0m59.676s sys 0m0.618s
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-> real 0m59.998s user 0m59.676s sys 0m0.618s
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A new, modular w11a test bench is under construction. So far it is very
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A new, modular w11a test bench is under construction. So far it is very
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incomplete. This very preliminary version can be executed with
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incomplete. This very preliminary version can be executed with
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- sys_w11a_n2 test bench
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- sys_w11a_n2 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \
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tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \
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"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
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"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
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-> 2847860.0 ns 142382: DONE
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-> 2847860.0 ns 142382: DONE
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-> real 0m33.013s user 0m31.870s sys 0m0.569s
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-> real 0m33.013s user 0m31.870s sys 0m0.569s
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|
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tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \
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tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \
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"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
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"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
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-> 1058440.0 ns 52911: DONE
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-> 1058440.0 ns 52911: DONE
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-> real 0m15.249s user 0m15.195s sys 0m0.236s
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-> real 0m15.249s user 0m15.195s sys 0m0.236s
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