-- $Id: tb_basys3_core.vhd 648 2015-02-20 20:16:21Z mueller $
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-- $Id: tb_basys3_core.vhd 648 2015-02-20 20:16:21Z mueller $
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--
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--
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-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: tb_basys3_core - sim
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-- Module Name: tb_basys3_core - sim
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-- Description: Test bench for basys3 - core device handling
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-- Description: Test bench for basys3 - core device handling
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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--
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--
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-- To test: generic, any basys3 target
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-- To test: generic, any basys3 target
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: viv 2014.4; ghdl 0.31
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-- Tool versions: viv 2014.4; ghdl 0.31
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4_core)
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-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4_core)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.serportlib.all;
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use work.serportlib.all;
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use work.simbus.all;
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use work.simbus.all;
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entity tb_basys3_core is
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entity tb_basys3_core is
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port (
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port (
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I_SWI : out slv16; -- b3 switches
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I_SWI : out slv16; -- b3 switches
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I_BTN : out slv5 -- b3 buttons
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I_BTN : out slv5 -- b3 buttons
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);
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);
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end tb_basys3_core;
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end tb_basys3_core;
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architecture sim of tb_basys3_core is
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architecture sim of tb_basys3_core is
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signal R_SWI : slv16 := (others=>'0');
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signal R_SWI : slv16 := (others=>'0');
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signal R_BTN : slv5 := (others=>'0');
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signal R_BTN : slv5 := (others=>'0');
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constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
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constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
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constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
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constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
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begin
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begin
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proc_simbus: process (SB_VAL)
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proc_simbus: process (SB_VAL)
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begin
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begin
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if SB_VAL'event and to_x01(SB_VAL)='1' then
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if SB_VAL'event and to_x01(SB_VAL)='1' then
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if SB_ADDR = sbaddr_swi then
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if SB_ADDR = sbaddr_swi then
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R_SWI <= to_x01(SB_DATA(R_SWI'range));
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R_SWI <= to_x01(SB_DATA(R_SWI'range));
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end if;
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end if;
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if SB_ADDR = sbaddr_btn then
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if SB_ADDR = sbaddr_btn then
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R_BTN <= to_x01(SB_DATA(R_BTN'range));
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R_BTN <= to_x01(SB_DATA(R_BTN'range));
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end if;
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end if;
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end if;
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end if;
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end process proc_simbus;
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end process proc_simbus;
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I_SWI <= R_SWI;
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I_SWI <= R_SWI;
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I_BTN <= R_BTN;
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I_BTN <= R_BTN;
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end sim;
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end sim;
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