-- $Id: tb_nexys3_core.vhd 649 2015-02-21 21:10:16Z mueller $
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-- $Id: tb_nexys3_core.vhd 649 2015-02-21 21:10:16Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: tb_nexys3_core - sim
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-- Module Name: tb_nexys3_core - sim
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-- Description: Test bench for nexys3 - core device handling
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-- Description: Test bench for nexys3 - core device handling
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--
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--
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-- Dependencies: vlib/parts/micron/mt45w8mw16b
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-- Dependencies: vlib/parts/micron/mt45w8mw16b
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--
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--
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-- To test: generic, any nexys3 target
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-- To test: generic, any nexys3 target
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
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-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
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-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.serportlib.all;
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use work.serportlib.all;
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use work.simbus.all;
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use work.simbus.all;
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entity tb_nexys3_core is
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entity tb_nexys3_core is
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port (
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port (
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I_SWI : out slv8; -- n3 switches
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I_SWI : out slv8; -- n3 switches
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I_BTN : out slv5; -- n3 buttons
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I_BTN : out slv5; -- n3 buttons
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O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
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O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
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O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
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O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
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O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
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O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
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O_MEM_CLK : in slbit; -- cram: clock
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O_MEM_CLK : in slbit; -- cram: clock
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O_MEM_CRE : in slbit; -- cram: command register enable
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O_MEM_CRE : in slbit; -- cram: command register enable
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I_MEM_WAIT : out slbit; -- cram: mem wait
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I_MEM_WAIT : out slbit; -- cram: mem wait
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O_MEM_ADDR : in slv23; -- cram: address lines
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O_MEM_ADDR : in slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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);
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);
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end tb_nexys3_core;
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end tb_nexys3_core;
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architecture sim of tb_nexys3_core is
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architecture sim of tb_nexys3_core is
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signal R_SWI : slv8 := (others=>'0');
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signal R_SWI : slv8 := (others=>'0');
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signal R_BTN : slv5 := (others=>'0');
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signal R_BTN : slv5 := (others=>'0');
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constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
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constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
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constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
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constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
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begin
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begin
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MEM : entity work.mt45w8mw16b
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MEM : entity work.mt45w8mw16b
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port map (
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port map (
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CLK => O_MEM_CLK,
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CLK => O_MEM_CLK,
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CE_N => O_MEM_CE_N,
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CE_N => O_MEM_CE_N,
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OE_N => O_MEM_OE_N,
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OE_N => O_MEM_OE_N,
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WE_N => O_MEM_WE_N,
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WE_N => O_MEM_WE_N,
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UB_N => O_MEM_BE_N(1),
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UB_N => O_MEM_BE_N(1),
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LB_N => O_MEM_BE_N(0),
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LB_N => O_MEM_BE_N(0),
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ADV_N => O_MEM_ADV_N,
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ADV_N => O_MEM_ADV_N,
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CRE => O_MEM_CRE,
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CRE => O_MEM_CRE,
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MWAIT => I_MEM_WAIT,
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MWAIT => I_MEM_WAIT,
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ADDR => O_MEM_ADDR,
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ADDR => O_MEM_ADDR,
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DATA => IO_MEM_DATA
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DATA => IO_MEM_DATA
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);
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);
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proc_simbus: process (SB_VAL)
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proc_simbus: process (SB_VAL)
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begin
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begin
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if SB_VAL'event and to_x01(SB_VAL)='1' then
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if SB_VAL'event and to_x01(SB_VAL)='1' then
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if SB_ADDR = sbaddr_swi then
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if SB_ADDR = sbaddr_swi then
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R_SWI <= to_x01(SB_DATA(R_SWI'range));
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R_SWI <= to_x01(SB_DATA(R_SWI'range));
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end if;
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end if;
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if SB_ADDR = sbaddr_btn then
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if SB_ADDR = sbaddr_btn then
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R_BTN <= to_x01(SB_DATA(R_BTN'range));
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R_BTN <= to_x01(SB_DATA(R_BTN'range));
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end if;
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end if;
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end if;
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end if;
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end process proc_simbus;
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end process proc_simbus;
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I_SWI <= R_SWI;
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I_SWI <= R_SWI;
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I_BTN <= R_BTN;
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I_BTN <= R_BTN;
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end sim;
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end sim;
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