-- $Id: tb_nexys3_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
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-- $Id: tb_nexys3_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
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--
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--
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-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: tb_nexys3_fusp - sim
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-- Module Name: tb_nexys3_fusp - sim
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-- Description: Test bench for nexys3 (base+fusp)
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-- Description: Test bench for nexys3 (base+fusp)
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--
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--
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-- Dependencies: simlib/simclk
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-- Dependencies: simlib/simclk
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-- simlib/simclkcnt
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-- simlib/simclkcnt
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-- xlib/s6_cmt_sfs
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-- xlib/s6_cmt_sfs
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-- rlink/tb/tbcore_rlink
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-- rlink/tb/tbcore_rlink
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-- tb_nexys3_core
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-- tb_nexys3_core
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-- serport/serport_master
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-- serport/serport_master
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-- nexys3_fusp_aif [UUT]
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-- nexys3_fusp_aif [UUT]
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--
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--
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-- To test: generic, any nexys3_fusp_aif target
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-- To test: generic, any nexys3_fusp_aif target
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
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-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
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-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
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-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
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-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
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-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
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-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
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-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
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-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.rlinklib.all;
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use work.rlinklib.all;
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use work.rlinktblib.all;
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use work.rlinktblib.all;
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use work.serportlib.all;
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use work.serportlib.all;
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use work.xlib.all;
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use work.xlib.all;
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use work.nexys3lib.all;
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use work.nexys3lib.all;
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use work.simlib.all;
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use work.simlib.all;
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use work.simbus.all;
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use work.simbus.all;
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use work.sys_conf.all;
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use work.sys_conf.all;
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entity tb_nexys3_fusp is
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entity tb_nexys3_fusp is
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end tb_nexys3_fusp;
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end tb_nexys3_fusp;
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architecture sim of tb_nexys3_fusp is
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architecture sim of tb_nexys3_fusp is
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signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
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signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
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signal CLKCOM : slbit := '0'; -- communication clock
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signal CLKCOM : slbit := '0'; -- communication clock
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signal CLK_STOP : slbit := '0';
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signal CLK_STOP : slbit := '0';
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signal CLKCOM_CYCLE : integer := 0;
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signal CLKCOM_CYCLE : integer := 0;
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signal RESET : slbit := '0';
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signal RESET : slbit := '0';
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signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
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signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
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signal RXDATA : slv8 := (others=>'0');
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signal RXDATA : slv8 := (others=>'0');
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signal RXVAL : slbit := '0';
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signal RXVAL : slbit := '0';
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signal RXERR : slbit := '0';
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signal RXERR : slbit := '0';
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signal RXACT : slbit := '0';
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signal RXACT : slbit := '0';
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signal TXDATA : slv8 := (others=>'0');
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signal TXDATA : slv8 := (others=>'0');
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signal TXENA : slbit := '0';
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signal TXENA : slbit := '0';
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signal TXBUSY : slbit := '0';
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signal TXBUSY : slbit := '0';
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signal RX_HOLD : slbit := '0';
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signal RX_HOLD : slbit := '0';
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signal I_RXD : slbit := '1';
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signal I_RXD : slbit := '1';
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signal O_TXD : slbit := '1';
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signal O_TXD : slbit := '1';
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signal I_SWI : slv8 := (others=>'0');
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signal I_SWI : slv8 := (others=>'0');
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signal I_BTN : slv5 := (others=>'0');
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signal I_BTN : slv5 := (others=>'0');
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signal O_LED : slv8 := (others=>'0');
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signal O_LED : slv8 := (others=>'0');
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signal O_ANO_N : slv4 := (others=>'0');
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signal O_ANO_N : slv4 := (others=>'0');
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signal O_SEG_N : slv8 := (others=>'0');
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signal O_SEG_N : slv8 := (others=>'0');
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signal O_MEM_CE_N : slbit := '1';
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signal O_MEM_CE_N : slbit := '1';
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signal O_MEM_BE_N : slv2 := (others=>'1');
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signal O_MEM_BE_N : slv2 := (others=>'1');
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signal O_MEM_WE_N : slbit := '1';
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signal O_MEM_WE_N : slbit := '1';
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signal O_MEM_OE_N : slbit := '1';
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signal O_MEM_OE_N : slbit := '1';
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signal O_MEM_ADV_N : slbit := '1';
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signal O_MEM_ADV_N : slbit := '1';
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signal O_MEM_CLK : slbit := '0';
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signal O_MEM_CLK : slbit := '0';
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signal O_MEM_CRE : slbit := '0';
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signal O_MEM_CRE : slbit := '0';
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signal I_MEM_WAIT : slbit := '0';
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signal I_MEM_WAIT : slbit := '0';
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signal O_MEM_ADDR : slv23 := (others=>'Z');
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signal O_MEM_ADDR : slv23 := (others=>'Z');
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signal IO_MEM_DATA : slv16 := (others=>'0');
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signal IO_MEM_DATA : slv16 := (others=>'0');
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signal O_PPCM_CE_N : slbit := '0';
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signal O_PPCM_CE_N : slbit := '0';
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signal O_PPCM_RST_N : slbit := '0';
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signal O_PPCM_RST_N : slbit := '0';
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signal O_FUSP_RTS_N : slbit := '0';
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signal O_FUSP_RTS_N : slbit := '0';
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signal I_FUSP_CTS_N : slbit := '0';
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signal I_FUSP_CTS_N : slbit := '0';
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signal I_FUSP_RXD : slbit := '1';
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signal I_FUSP_RXD : slbit := '1';
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signal O_FUSP_TXD : slbit := '1';
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signal O_FUSP_TXD : slbit := '1';
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signal UART_RESET : slbit := '0';
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signal UART_RESET : slbit := '0';
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signal UART_RXD : slbit := '1';
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signal UART_RXD : slbit := '1';
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signal UART_TXD : slbit := '1';
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signal UART_TXD : slbit := '1';
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signal CTS_N : slbit := '0';
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signal CTS_N : slbit := '0';
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signal RTS_N : slbit := '0';
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signal RTS_N : slbit := '0';
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signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
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signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
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signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
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signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
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constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
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constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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constant clock_offset : time := 200 ns;
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constant clock_offset : time := 200 ns;
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begin
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begin
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CLKGEN : simclk
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CLKGEN : simclk
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generic map (
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generic map (
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PERIOD => clock_period,
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PERIOD => clock_period,
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OFFSET => clock_offset)
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OFFSET => clock_offset)
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port map (
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port map (
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CLK => CLKOSC,
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CLK => CLKOSC,
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CLK_STOP => CLK_STOP
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CLK_STOP => CLK_STOP
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);
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);
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CLKGEN_COM : s6_cmt_sfs
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CLKGEN_COM : s6_cmt_sfs
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generic map (
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generic map (
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VCO_DIVIDE => sys_conf_clksys_vcodivide,
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VCO_DIVIDE => sys_conf_clksys_vcodivide,
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VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
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VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
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OUT_DIVIDE => sys_conf_clksys_outdivide,
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OUT_DIVIDE => sys_conf_clksys_outdivide,
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CLKIN_PERIOD => 10.0,
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CLKIN_PERIOD => 10.0,
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CLKIN_JITTER => 0.01,
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CLKIN_JITTER => 0.01,
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STARTUP_WAIT => false,
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STARTUP_WAIT => false,
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GEN_TYPE => sys_conf_clksys_gentype)
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GEN_TYPE => sys_conf_clksys_gentype)
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port map (
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port map (
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CLKIN => CLKOSC,
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CLKIN => CLKOSC,
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CLKFX => CLKCOM,
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CLKFX => CLKCOM,
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LOCKED => open
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LOCKED => open
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);
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);
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CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
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CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
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TBCORE : tbcore_rlink
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TBCORE : tbcore_rlink
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port map (
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port map (
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CLK => CLKCOM,
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CLK => CLKCOM,
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CLK_STOP => CLK_STOP,
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CLK_STOP => CLK_STOP,
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RX_DATA => TXDATA,
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RX_DATA => TXDATA,
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RX_VAL => TXENA,
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RX_VAL => TXENA,
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RX_HOLD => RX_HOLD,
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RX_HOLD => RX_HOLD,
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TX_DATA => RXDATA,
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TX_DATA => RXDATA,
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TX_ENA => RXVAL
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TX_ENA => RXVAL
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);
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);
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RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
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RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
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N3CORE : entity work.tb_nexys3_core
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N3CORE : entity work.tb_nexys3_core
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port map (
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port map (
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I_SWI => I_SWI,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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I_BTN => I_BTN,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_ADV_N => O_MEM_ADV_N,
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O_MEM_ADV_N => O_MEM_ADV_N,
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O_MEM_CLK => O_MEM_CLK,
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O_MEM_CLK => O_MEM_CLK,
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O_MEM_CRE => O_MEM_CRE,
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O_MEM_CRE => O_MEM_CRE,
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I_MEM_WAIT => I_MEM_WAIT,
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I_MEM_WAIT => I_MEM_WAIT,
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O_MEM_ADDR => O_MEM_ADDR,
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O_MEM_ADDR => O_MEM_ADDR,
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IO_MEM_DATA => IO_MEM_DATA
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IO_MEM_DATA => IO_MEM_DATA
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);
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);
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UUT : nexys3_fusp_aif
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UUT : nexys3_fusp_aif
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port map (
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port map (
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I_CLK100 => CLKOSC,
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I_CLK100 => CLKOSC,
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I_RXD => I_RXD,
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I_RXD => I_RXD,
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O_TXD => O_TXD,
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O_TXD => O_TXD,
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I_SWI => I_SWI,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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I_BTN => I_BTN,
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O_LED => O_LED,
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O_LED => O_LED,
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O_ANO_N => O_ANO_N,
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O_ANO_N => O_ANO_N,
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O_SEG_N => O_SEG_N,
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O_SEG_N => O_SEG_N,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_ADV_N => O_MEM_ADV_N,
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O_MEM_ADV_N => O_MEM_ADV_N,
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O_MEM_CLK => O_MEM_CLK,
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O_MEM_CLK => O_MEM_CLK,
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O_MEM_CRE => O_MEM_CRE,
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O_MEM_CRE => O_MEM_CRE,
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I_MEM_WAIT => I_MEM_WAIT,
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I_MEM_WAIT => I_MEM_WAIT,
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O_MEM_ADDR => O_MEM_ADDR,
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O_MEM_ADDR => O_MEM_ADDR,
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IO_MEM_DATA => IO_MEM_DATA,
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IO_MEM_DATA => IO_MEM_DATA,
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O_PPCM_CE_N => O_PPCM_CE_N,
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O_PPCM_CE_N => O_PPCM_CE_N,
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O_PPCM_RST_N => O_PPCM_RST_N,
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O_PPCM_RST_N => O_PPCM_RST_N,
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O_FUSP_RTS_N => O_FUSP_RTS_N,
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O_FUSP_RTS_N => O_FUSP_RTS_N,
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I_FUSP_CTS_N => I_FUSP_CTS_N,
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I_FUSP_CTS_N => I_FUSP_CTS_N,
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I_FUSP_RXD => I_FUSP_RXD,
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I_FUSP_RXD => I_FUSP_RXD,
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O_FUSP_TXD => O_FUSP_TXD
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O_FUSP_TXD => O_FUSP_TXD
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);
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);
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SERMSTR : serport_master
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SERMSTR : serport_master
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generic map (
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generic map (
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CDWIDTH => CLKDIV'length)
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CDWIDTH => CLKDIV'length)
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port map (
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port map (
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CLK => CLKCOM,
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CLK => CLKCOM,
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RESET => UART_RESET,
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RESET => UART_RESET,
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CLKDIV => CLKDIV,
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CLKDIV => CLKDIV,
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ENAXON => R_PORTSEL_XON,
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ENAXON => R_PORTSEL_XON,
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ENAESC => '0',
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ENAESC => '0',
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RXDATA => RXDATA,
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RXDATA => RXDATA,
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RXVAL => RXVAL,
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RXVAL => RXVAL,
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RXERR => RXERR,
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RXERR => RXERR,
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RXOK => '1',
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RXOK => '1',
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TXDATA => TXDATA,
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TXDATA => TXDATA,
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TXENA => TXENA,
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TXENA => TXENA,
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TXBUSY => TXBUSY,
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TXBUSY => TXBUSY,
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RXSD => UART_RXD,
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RXSD => UART_RXD,
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TXSD => UART_TXD,
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TXSD => UART_TXD,
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RXRTS_N => RTS_N,
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RXRTS_N => RTS_N,
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TXCTS_N => CTS_N
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TXCTS_N => CTS_N
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);
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);
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proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
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proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
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O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
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O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
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begin
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begin
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if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
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if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
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I_RXD <= UART_TXD; -- write port 0 inputs
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I_RXD <= UART_TXD; -- write port 0 inputs
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UART_RXD <= O_TXD; -- get port 0 outputs
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UART_RXD <= O_TXD; -- get port 0 outputs
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RTS_N <= '0';
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RTS_N <= '0';
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I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
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I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
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I_FUSP_CTS_N <= '0';
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I_FUSP_CTS_N <= '0';
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else -- otherwise use pmod1 rs232
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else -- otherwise use pmod1 rs232
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I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
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I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
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I_FUSP_CTS_N <= CTS_N;
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I_FUSP_CTS_N <= CTS_N;
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UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
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UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
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RTS_N <= O_FUSP_RTS_N;
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RTS_N <= O_FUSP_RTS_N;
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I_RXD <= '1'; -- port 0 inputs to idle state
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I_RXD <= '1'; -- port 0 inputs to idle state
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end if;
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end if;
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end process proc_port_mux;
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end process proc_port_mux;
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proc_moni: process
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proc_moni: process
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variable oline : line;
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variable oline : line;
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begin
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begin
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loop
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loop
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wait until rising_edge(CLKCOM);
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wait until rising_edge(CLKCOM);
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if RXERR = '1' then
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if RXERR = '1' then
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writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
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writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
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writeline(output, oline);
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writeline(output, oline);
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end if;
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end if;
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end loop;
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end loop;
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end process proc_moni;
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end process proc_moni;
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proc_simbus: process (SB_VAL)
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proc_simbus: process (SB_VAL)
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begin
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begin
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if SB_VAL'event and to_x01(SB_VAL)='1' then
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if SB_VAL'event and to_x01(SB_VAL)='1' then
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if SB_ADDR = sbaddr_portsel then
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if SB_ADDR = sbaddr_portsel then
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R_PORTSEL_SER <= to_x01(SB_DATA(0));
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R_PORTSEL_SER <= to_x01(SB_DATA(0));
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R_PORTSEL_XON <= to_x01(SB_DATA(1));
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R_PORTSEL_XON <= to_x01(SB_DATA(1));
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end if;
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end if;
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end if;
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end if;
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end process proc_simbus;
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end process proc_simbus;
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end sim;
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end sim;
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