-- $Id: ibdr_minisys.vhd 676 2015-05-09 16:31:54Z mueller $
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-- $Id: ibdr_minisys.vhd 676 2015-05-09 16:31:54Z mueller $
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--
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--
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: ibdr_minisys - syn
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-- Module Name: ibdr_minisys - syn
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-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK
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-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK
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--
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--
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-- Dependencies: ibdr_sdreg
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-- Dependencies: ibdr_sdreg
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-- ibd_kw11l
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-- ibd_kw11l
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-- ibdr_dl11
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-- ibdr_dl11
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-- ibdr_rk11
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-- ibdr_rk11
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-- ib_sres_or_4
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-- ib_sres_or_4
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-- ib_intmap
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-- ib_intmap
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8
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-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6
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-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.1.2 now numeric_std clean
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-- 2011-11-18 427 1.1.2 now numeric_std clean
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-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
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-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
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-- to _dl11
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-- to _dl11
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-- 2009-05-31 221 1.0.6 add RESET to kw11l;
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-- 2009-05-31 221 1.0.6 add RESET to kw11l;
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-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
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-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
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-- 2008-08-22 161 1.0.4 use iblib, ibdlib
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-- 2008-08-22 161 1.0.4 use iblib, ibdlib
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-- 2008-05-09 144 1.0.3 use EI_ACK with _kw11l, _dl11
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-- 2008-05-09 144 1.0.3 use EI_ACK with _kw11l, _dl11
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-- 2008-04-18 136 1.0.2 add RESET port, use for ibdr_sdreg
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-- 2008-04-18 136 1.0.2 add RESET port, use for ibdr_sdreg
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-- 2008-01-20 113 1.0.1 RRI_LAM now vector
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-- 2008-01-20 113 1.0.1 RRI_LAM now vector
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-- 2008-01-20 112 1.0 Initial version
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-- 2008-01-20 112 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- mini system setup
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-- mini system setup
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--
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--
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-- ibbase vec pri slot attn device name
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-- ibbase vec pri slot attn device name
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--
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--
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-- 177546 100 6 4 - KW11-L
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-- 177546 100 6 4 - KW11-L
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-- 177400 220 5 3 4 RK11
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-- 177400 220 5 3 4 RK11
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-- 177560 060 4 2 1 DL11-RX 1st
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-- 177560 060 4 2 1 DL11-RX 1st
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-- 064 4 1 ^ DL11-TX 1st
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-- 064 4 1 ^ DL11-TX 1st
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-- 177570 - - - - sdreg
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-- 177570 - - - - sdreg
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.iblib.all;
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use work.ibdlib.all;
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use work.ibdlib.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
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entity ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_USEC : in slbit; -- usec pulse
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CE_MSEC : in slbit; -- msec pulse
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CE_MSEC : in slbit; -- msec pulse
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slv16_1; -- remote attention vector
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RB_LAM : out slv16_1; -- remote attention vector
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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DISPREG : out slv16 -- display register
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DISPREG : out slv16 -- display register
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);
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);
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end ibdr_minisys;
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end ibdr_minisys;
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architecture syn of ibdr_minisys is
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architecture syn of ibdr_minisys is
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constant conf_intmap : intmap_array_type :=
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constant conf_intmap : intmap_array_type :=
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(intmap_init, -- line 15
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(intmap_init, -- line 15
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intmap_init, -- line 14
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intmap_init, -- line 14
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intmap_init, -- line 13
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intmap_init, -- line 13
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intmap_init, -- line 12
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intmap_init, -- line 12
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intmap_init, -- line 11
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intmap_init, -- line 11
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intmap_init, -- line 10
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intmap_init, -- line 10
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intmap_init, -- line 9
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intmap_init, -- line 9
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intmap_init, -- line 8
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intmap_init, -- line 8
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intmap_init, -- line 7
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intmap_init, -- line 7
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intmap_init, -- line 6
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intmap_init, -- line 6
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intmap_init, -- line 5
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intmap_init, -- line 5
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(8#100#,6), -- line 4 KW11-L
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(8#100#,6), -- line 4 KW11-L
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(8#220#,5), -- line 3 RK11
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(8#220#,5), -- line 3 RK11
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(8#060#,4), -- line 2 DL11-RX
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(8#060#,4), -- line 2 DL11-RX
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(8#064#,4), -- line 1 DL11-TX
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(8#064#,4), -- line 1 DL11-TX
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intmap_init -- line 0
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intmap_init -- line 0
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);
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);
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signal RB_LAM_DL11 : slbit := '0';
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signal RB_LAM_DL11 : slbit := '0';
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signal RB_LAM_RK11 : slbit := '0';
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signal RB_LAM_RK11 : slbit := '0';
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signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
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signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
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signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
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signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
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signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
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signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
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signal EI_REQ : slv16_1 := (others=>'0');
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signal EI_REQ : slv16_1 := (others=>'0');
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signal EI_ACK : slv16_1 := (others=>'0');
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signal EI_ACK : slv16_1 := (others=>'0');
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signal EI_REQ_KW11L : slbit := '0';
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signal EI_REQ_KW11L : slbit := '0';
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signal EI_REQ_DL11RX : slbit := '0';
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signal EI_REQ_DL11RX : slbit := '0';
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signal EI_REQ_DL11TX : slbit := '0';
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signal EI_REQ_DL11TX : slbit := '0';
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signal EI_REQ_RK11 : slbit := '0';
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signal EI_REQ_RK11 : slbit := '0';
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signal EI_ACK_KW11L : slbit := '0';
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signal EI_ACK_KW11L : slbit := '0';
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signal EI_ACK_DL11RX : slbit := '0';
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signal EI_ACK_DL11RX : slbit := '0';
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signal EI_ACK_DL11TX : slbit := '0';
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signal EI_ACK_DL11TX : slbit := '0';
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signal EI_ACK_RK11 : slbit := '0';
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signal EI_ACK_RK11 : slbit := '0';
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begin
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begin
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SDREG : ibdr_sdreg
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SDREG : ibdr_sdreg
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_SDREG,
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IB_SRES => IB_SRES_SDREG,
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DISPREG => DISPREG
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DISPREG => DISPREG
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);
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);
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KW11L : ibd_kw11l
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KW11L : ibd_kw11l
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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RESET => RESET,
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RESET => RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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CPUSUSP => '0',
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CPUSUSP => '0',
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_KW11L,
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IB_SRES => IB_SRES_KW11L,
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EI_REQ => EI_REQ_KW11L,
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EI_REQ => EI_REQ_KW11L,
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EI_ACK => EI_ACK_KW11L
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EI_ACK => EI_ACK_KW11L
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);
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);
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DL11 : ibdr_dl11
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DL11 : ibdr_dl11
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RESET => RESET,
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RESET => RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RB_LAM => RB_LAM_DL11,
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RB_LAM => RB_LAM_DL11,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_DL11,
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IB_SRES => IB_SRES_DL11,
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EI_REQ_RX => EI_REQ_DL11RX,
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EI_REQ_RX => EI_REQ_DL11RX,
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EI_REQ_TX => EI_REQ_DL11TX,
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EI_REQ_TX => EI_REQ_DL11TX,
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EI_ACK_RX => EI_ACK_DL11RX,
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EI_ACK_RX => EI_ACK_DL11RX,
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EI_ACK_TX => EI_ACK_DL11TX
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EI_ACK_TX => EI_ACK_DL11TX
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);
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);
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RK11 : ibdr_rk11
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RK11 : ibdr_rk11
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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BRESET => BRESET,
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BRESET => BRESET,
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RB_LAM => RB_LAM_RK11,
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RB_LAM => RB_LAM_RK11,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_RK11,
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IB_SRES => IB_SRES_RK11,
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EI_REQ => EI_REQ_RK11,
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EI_REQ => EI_REQ_RK11,
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EI_ACK => EI_ACK_RK11
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EI_ACK => EI_ACK_RK11
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);
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);
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SRES_OR : ib_sres_or_4
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SRES_OR : ib_sres_or_4
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port map (
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port map (
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IB_SRES_1 => IB_SRES_SDREG,
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IB_SRES_1 => IB_SRES_SDREG,
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IB_SRES_2 => IB_SRES_KW11L,
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IB_SRES_2 => IB_SRES_KW11L,
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IB_SRES_3 => IB_SRES_DL11,
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IB_SRES_3 => IB_SRES_DL11,
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IB_SRES_4 => IB_SRES_RK11,
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IB_SRES_4 => IB_SRES_RK11,
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IB_SRES_OR => IB_SRES
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IB_SRES_OR => IB_SRES
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);
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);
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INTMAP : ib_intmap
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INTMAP : ib_intmap
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generic map (
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generic map (
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INTMAP => conf_intmap)
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INTMAP => conf_intmap)
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port map (
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port map (
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EI_REQ => EI_REQ,
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EI_REQ => EI_REQ,
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EI_ACKM => EI_ACKM,
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EI_ACKM => EI_ACKM,
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EI_ACK => EI_ACK,
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EI_ACK => EI_ACK,
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EI_PRI => EI_PRI,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT
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EI_VECT => EI_VECT
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);
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);
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EI_REQ(4) <= EI_REQ_KW11L;
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EI_REQ(4) <= EI_REQ_KW11L;
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EI_REQ(3) <= EI_REQ_RK11;
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EI_REQ(3) <= EI_REQ_RK11;
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EI_REQ(2) <= EI_REQ_DL11RX;
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EI_REQ(2) <= EI_REQ_DL11RX;
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EI_REQ(1) <= EI_REQ_DL11TX;
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EI_REQ(1) <= EI_REQ_DL11TX;
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EI_ACK_KW11L <= EI_ACK(4);
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EI_ACK_KW11L <= EI_ACK(4);
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EI_ACK_RK11 <= EI_ACK(3);
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EI_ACK_RK11 <= EI_ACK(3);
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EI_ACK_DL11RX <= EI_ACK(2);
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EI_ACK_DL11RX <= EI_ACK(2);
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EI_ACK_DL11TX <= EI_ACK(1);
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EI_ACK_DL11TX <= EI_ACK(1);
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RB_LAM(1) <= RB_LAM_DL11;
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RB_LAM(1) <= RB_LAM_DL11;
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RB_LAM(2) <= '0'; -- for 2nd DL11
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RB_LAM(2) <= '0'; -- for 2nd DL11
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RB_LAM(3) <= '0'; -- for DZ11
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RB_LAM(3) <= '0'; -- for DZ11
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RB_LAM(4) <= RB_LAM_RK11;
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RB_LAM(4) <= RB_LAM_RK11;
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RB_LAM(15 downto 5) <= (others=>'0');
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RB_LAM(15 downto 5) <= (others=>'0');
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end syn;
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end syn;
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