-- $Id: ibdr_rk11.vhd 672 2015-05-02 21:58:28Z mueller $
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-- $Id: ibdr_rk11.vhd 672 2015-05-02 21:58:28Z mueller $
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--
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--
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-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: ibdr_rk11 - syn
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-- Module Name: ibdr_rk11 - syn
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-- Description: ibus dev(rem): RK11-A/B
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-- Description: ibus dev(rem): RK11-A/B
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--
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--
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-- Dependencies: ram_1swar_gen
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-- Dependencies: ram_1swar_gen
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2014-06-08 561 14.7 131013 xc6slx16-2 44 139 9 60 s 5.6
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-- 2014-06-08 561 14.7 131013 xc6slx16-2 44 139 9 60 s 5.6
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
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-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
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-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
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-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
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-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start
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-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
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-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
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-- BUGFIX: sector counter now counts 000,...,013.
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-- BUGFIX: sector counter now counts 000,...,013.
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-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
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-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
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-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
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-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
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-- BUGFIX: re-work the seek complete handling
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-- BUGFIX: re-work the seek complete handling
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-- 2008-08-22 161 1.0.6 use iblib
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-- 2008-08-22 161 1.0.6 use iblib
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-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE
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-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE
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-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0
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-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0
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-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code
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-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code
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-- fix bug in control reset logic (we's missing)
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-- fix bug in control reset logic (we's missing)
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-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done
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-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done
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-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET
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-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET
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-- 2008-01-06 111 1.0 Initial version
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-- 2008-01-06 111 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.iblib.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity ibdr_rk11 is -- ibus dev(rem): RK11
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entity ibdr_rk11 is -- ibus dev(rem): RK11
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-- fixed address: 177400
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-- fixed address: 177400
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- msec pulse
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CE_MSEC : in slbit; -- msec pulse
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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EI_ACK : in slbit -- interrupt acknowledge
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);
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);
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end ibdr_rk11;
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end ibdr_rk11;
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architecture syn of ibdr_rk11 is
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architecture syn of ibdr_rk11 is
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constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
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constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
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constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
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constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
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constant ibaddr_rker : slv3 := "001"; -- rker address offset
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constant ibaddr_rker : slv3 := "001"; -- rker address offset
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constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
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constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
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constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
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constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
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constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
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constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
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constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
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constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
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constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
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constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
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constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
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constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
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subtype rkds_ibf_id is integer range 15 downto 13;
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subtype rkds_ibf_id is integer range 15 downto 13;
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constant rkds_ibf_adry : integer := 6;
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constant rkds_ibf_adry : integer := 6;
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constant rkds_ibf_scsa : integer := 4;
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constant rkds_ibf_scsa : integer := 4;
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subtype rkds_ibf_sc is integer range 3 downto 0;
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subtype rkds_ibf_sc is integer range 3 downto 0;
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subtype rker_ibf_he is integer range 15 downto 5;
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subtype rker_ibf_he is integer range 15 downto 5;
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constant rker_ibf_cse : integer := 1;
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constant rker_ibf_cse : integer := 1;
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constant rker_ibf_wce : integer := 0;
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constant rker_ibf_wce : integer := 0;
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constant rkcs_ibf_err : integer := 15;
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constant rkcs_ibf_err : integer := 15;
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constant rkcs_ibf_he : integer := 14;
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constant rkcs_ibf_he : integer := 14;
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constant rkcs_ibf_scp : integer := 13;
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constant rkcs_ibf_scp : integer := 13;
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constant rkcs_ibf_maint : integer := 12;
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constant rkcs_ibf_maint : integer := 12;
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constant rkcs_ibf_rdy : integer := 7;
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constant rkcs_ibf_rdy : integer := 7;
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constant rkcs_ibf_ide : integer := 6;
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constant rkcs_ibf_ide : integer := 6;
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subtype rkcs_ibf_mex is integer range 5 downto 4;
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subtype rkcs_ibf_mex is integer range 5 downto 4;
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subtype rkcs_ibf_func is integer range 3 downto 1;
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subtype rkcs_ibf_func is integer range 3 downto 1;
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constant rkcs_ibf_go : integer := 0;
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constant rkcs_ibf_go : integer := 0;
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subtype rkda_ibf_drsel is integer range 15 downto 13;
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subtype rkda_ibf_drsel is integer range 15 downto 13;
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subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id
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subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id
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constant rkmr_ibf_crdone: integer := 11; -- contr. reset done
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constant rkmr_ibf_crdone: integer := 11; -- contr. reset done
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constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's
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constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's
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constant rkmr_ibf_creset: integer := 9; -- control reset
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constant rkmr_ibf_creset: integer := 9; -- control reset
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constant rkmr_ibf_fdone : integer := 8; -- func done
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constant rkmr_ibf_fdone : integer := 8; -- func done
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subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done
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subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done
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constant func_creset : slv3 := "000"; -- func: control reset
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constant func_creset : slv3 := "000"; -- func: control reset
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constant func_write : slv3 := "001"; -- func: write
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constant func_write : slv3 := "001"; -- func: write
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constant func_read : slv3 := "010"; -- func: read
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constant func_read : slv3 := "010"; -- func: read
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constant func_wchk : slv3 := "011"; -- func: write check
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constant func_wchk : slv3 := "011"; -- func: write check
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constant func_seek : slv3 := "100"; -- func: seek
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constant func_seek : slv3 := "100"; -- func: seek
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constant func_rchk : slv3 := "101"; -- func: read check
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constant func_rchk : slv3 := "101"; -- func: read check
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constant func_dreset : slv3 := "110"; -- func: drive reset
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constant func_dreset : slv3 := "110"; -- func: drive reset
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constant func_wlock : slv3 := "111"; -- func: write lock
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constant func_wlock : slv3 := "111"; -- func: write lock
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type state_type is (
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type state_type is (
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s_idle,
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s_idle,
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s_init
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s_init
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);
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);
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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ibsel : slbit; -- ibus select
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state : state_type; -- state
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state : state_type; -- state
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id : slv3; -- rkds: drive id of search done
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id : slv3; -- rkds: drive id of search done
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sc : slv4; -- rkds: sector counter
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sc : slv4; -- rkds: sector counter
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cse : slbit; -- rker: check sum error
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cse : slbit; -- rker: check sum error
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wce : slbit; -- rker: write check error
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wce : slbit; -- rker: write check error
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he : slbit; -- rkcs: hard error
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he : slbit; -- rkcs: hard error
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scp : slbit; -- rkcs: seek complete
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scp : slbit; -- rkcs: seek complete
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maint : slbit; -- rkcs: maintenance mode
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maint : slbit; -- rkcs: maintenance mode
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rdy : slbit; -- rkcs: control ready
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rdy : slbit; -- rkcs: control ready
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ide : slbit; -- rkcs: interrupt on done enable
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ide : slbit; -- rkcs: interrupt on done enable
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drsel : slv3; -- rkda: currently selected drive
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drsel : slv3; -- rkda: currently selected drive
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fireq : slbit; -- func done interrupt request flag
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fireq : slbit; -- func done interrupt request flag
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sireq : slv8; -- seek done interrupt request flags
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sireq : slv8; -- seek done interrupt request flags
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sbusy : slv8; -- seek busy flags
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sbusy : slv8; -- seek busy flags
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rid : slv3; -- drive id for rem ds reads
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rid : slv3; -- drive id for rem ds reads
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icnt : slv3; -- init state counter
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icnt : slv3; -- init state counter
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creset : slbit; -- control reset flag
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creset : slbit; -- control reset flag
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crdone : slbit; -- control reset done since last fdone
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crdone : slbit; -- control reset done since last fdone
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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'0', -- ibsel
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'0', -- ibsel
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s_init, -- state
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s_init, -- state
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(others=>'0'), -- id
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(others=>'0'), -- id
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(others=>'0'), -- sc
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(others=>'0'), -- sc
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'0','0', -- cse, wce
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'0','0', -- cse, wce
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'0','0','0', -- he, scp, maint
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'0','0','0', -- he, scp, maint
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'1', -- rdy (SET TO 1)
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'1', -- rdy (SET TO 1)
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'0', -- ide
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'0', -- ide
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(others=>'0'), -- drsel
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(others=>'0'), -- drsel
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'0', -- fireq
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'0', -- fireq
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(others=>'0'), -- sireq
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(others=>'0'), -- sireq
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(others=>'0'), -- sbusy
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(others=>'0'), -- sbusy
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(others=>'0'), -- rid
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(others=>'0'), -- rid
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(others=>'0'), -- icnt
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(others=>'0'), -- icnt
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'0','1' -- creset, crdone
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'0','1' -- creset, crdone
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);
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);
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signal R_REGS : regs_type := regs_init;
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal MEM_1_WE : slbit := '0';
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signal MEM_1_WE : slbit := '0';
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signal MEM_0_WE : slbit := '0';
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signal MEM_0_WE : slbit := '0';
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signal MEM_ADDR : slv4 := (others=>'0');
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signal MEM_ADDR : slv4 := (others=>'0');
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signal MEM_DIN : slv16 := (others=>'0');
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signal MEM_DIN : slv16 := (others=>'0');
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signal MEM_DOUT : slv16 := (others=>'0');
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signal MEM_DOUT : slv16 := (others=>'0');
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begin
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begin
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MEM_1 : ram_1swar_gen
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MEM_1 : ram_1swar_gen
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generic map (
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generic map (
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AWIDTH => 4,
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AWIDTH => 4,
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DWIDTH => 8)
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DWIDTH => 8)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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WE => MEM_1_WE,
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WE => MEM_1_WE,
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ADDR => MEM_ADDR,
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ADDR => MEM_ADDR,
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DI => MEM_DIN(ibf_byte1),
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DI => MEM_DIN(ibf_byte1),
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DO => MEM_DOUT(ibf_byte1));
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DO => MEM_DOUT(ibf_byte1));
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MEM_0 : ram_1swar_gen
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MEM_0 : ram_1swar_gen
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generic map (
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generic map (
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AWIDTH => 4,
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AWIDTH => 4,
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DWIDTH => 8)
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DWIDTH => 8)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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WE => MEM_0_WE,
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WE => MEM_0_WE,
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ADDR => MEM_ADDR,
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ADDR => MEM_ADDR,
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DI => MEM_DIN(ibf_byte0),
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DI => MEM_DIN(ibf_byte0),
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DO => MEM_DOUT(ibf_byte0));
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DO => MEM_DOUT(ibf_byte0));
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if BRESET='1' or R_REGS.creset='1' then
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if BRESET='1' or R_REGS.creset='1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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if R_REGS.creset = '1' then
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if R_REGS.creset = '1' then
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R_REGS.sbusy <= N_REGS.sbusy;
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R_REGS.sbusy <= N_REGS.sbusy;
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end if;
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end if;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
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proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibhold : slbit := '0';
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variable ibhold : slbit := '0';
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variable icrip : slbit := '0';
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variable icrip : slbit := '0';
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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variable ibrem : slbit := '0';
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variable ibrem : slbit := '0';
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variable ibreq : slbit := '0';
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variable ibreq : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ibwrem : slbit := '0';
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variable ibwrem : slbit := '0';
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variable ilam : slbit := '0';
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variable ilam : slbit := '0';
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variable iscval : slbit := '0';
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variable iscval : slbit := '0';
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variable iscid : slv3 := (others=>'0');
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variable iscid : slv3 := (others=>'0');
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variable iei_req : slbit := '0';
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variable iei_req : slbit := '0';
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variable imem_we0 : slbit := '0';
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variable imem_we0 : slbit := '0';
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variable imem_we1 : slbit := '0';
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variable imem_we1 : slbit := '0';
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variable imem_addr : slv4 := (others=>'0');
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variable imem_addr : slv4 := (others=>'0');
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variable imem_din : slv16 := (others=>'0');
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variable imem_din : slv16 := (others=>'0');
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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ibhold := '0';
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ibhold := '0';
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icrip := '0';
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icrip := '0';
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idout := (others=>'0');
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idout := (others=>'0');
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ibrem := IB_MREQ.racc or r.maint;
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ibrem := IB_MREQ.racc or r.maint;
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibrd := IB_MREQ.re;
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ibrd := IB_MREQ.re;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ibwrem := IB_MREQ.we and ibrem;
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ibwrem := IB_MREQ.we and ibrem;
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ilam := '0';
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ilam := '0';
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iscval := '0';
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iscval := '0';
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iscid := (others=>'0');
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iscid := (others=>'0');
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iei_req := '0';
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iei_req := '0';
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imem_we0 := '0';
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imem_we0 := '0';
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imem_we1 := '0';
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imem_we1 := '0';
|
imem_addr := '0' & IB_MREQ.addr(3 downto 1);
|
imem_addr := '0' & IB_MREQ.addr(3 downto 1);
|
imem_din := IB_MREQ.din;
|
imem_din := IB_MREQ.din;
|
|
|
-- ibus address decoder
|
-- ibus address decoder
|
n.ibsel := '0';
|
n.ibsel := '0';
|
if IB_MREQ.aval = '1' and
|
if IB_MREQ.aval = '1' and
|
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
|
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
|
n.ibsel := '1';
|
n.ibsel := '1';
|
end if;
|
end if;
|
|
|
-- internal state machine (for control reset)
|
-- internal state machine (for control reset)
|
case r.state is
|
case r.state is
|
when s_idle =>
|
when s_idle =>
|
null;
|
null;
|
|
|
when s_init =>
|
when s_init =>
|
ibhold := r.ibsel; -- hold ibus when controller busy
|
ibhold := r.ibsel; -- hold ibus when controller busy
|
icrip := '1';
|
icrip := '1';
|
n.icnt := slv(unsigned(r.icnt) + 1);
|
n.icnt := slv(unsigned(r.icnt) + 1);
|
if unsigned(r.icnt) = 7 then
|
if unsigned(r.icnt) = 7 then
|
n.state := s_idle;
|
n.state := s_idle;
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
|
|
-- ibus transactions
|
-- ibus transactions
|
|
|
if r.ibsel='1' and ibhold='0' then -- selected and not holding
|
if r.ibsel='1' and ibhold='0' then -- selected and not holding
|
idout := MEM_DOUT;
|
idout := MEM_DOUT;
|
imem_we0 := ibw0;
|
imem_we0 := ibw0;
|
imem_we1 := ibw1;
|
imem_we1 := ibw1;
|
|
|
case IB_MREQ.addr(3 downto 1) is
|
case IB_MREQ.addr(3 downto 1) is
|
|
|
when ibaddr_rkds => -- RKDS -- drive status register ----
|
when ibaddr_rkds => -- RKDS -- drive status register ----
|
if ibrem = '0' then
|
if ibrem = '0' then
|
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr.
|
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr.
|
else
|
else
|
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr.
|
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr.
|
end if;
|
end if;
|
idout(rkds_ibf_id) := r.id;
|
idout(rkds_ibf_id) := r.id;
|
if ibrem = '0' then -- loc ? simulate drive sector monitor
|
if ibrem = '0' then -- loc ? simulate drive sector monitor
|
if r.sc = MEM_DOUT(rkds_ibf_sc) then
|
if r.sc = MEM_DOUT(rkds_ibf_sc) then
|
idout(rkds_ibf_scsa) := '1';
|
idout(rkds_ibf_scsa) := '1';
|
else
|
else
|
idout(rkds_ibf_scsa) := '0';
|
idout(rkds_ibf_scsa) := '0';
|
end if;
|
end if;
|
idout(rkds_ibf_sc) := r.sc;
|
idout(rkds_ibf_sc) := r.sc;
|
end if;
|
end if;
|
|
|
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
|
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
|
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
|
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
|
end if;
|
end if;
|
|
|
if ibwrem = '1' then -- rem write ? than update ds data
|
if ibwrem = '1' then -- rem write ? than update ds data
|
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr
|
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr
|
else -- loc write ?
|
else -- loc write ?
|
imem_we0 := '0'; -- suppress we, is read-only
|
imem_we0 := '0'; -- suppress we, is read-only
|
imem_we1 := '0';
|
imem_we1 := '0';
|
end if;
|
end if;
|
|
|
when ibaddr_rker => -- RKER -- error register ------------
|
when ibaddr_rker => -- RKER -- error register ------------
|
idout(4 downto 2) := (others=>'0'); -- unassigned bits
|
idout(4 downto 2) := (others=>'0'); -- unassigned bits
|
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !)
|
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !)
|
idout(rker_ibf_wce) := r.wce;
|
idout(rker_ibf_wce) := r.wce;
|
|
|
if ibwrem = '1' then -- rem write ?
|
if ibwrem = '1' then -- rem write ?
|
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ?
|
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ?
|
n.he := '1';
|
n.he := '1';
|
else
|
else
|
n.he := '0';
|
n.he := '0';
|
end if;
|
end if;
|
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit
|
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit
|
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit
|
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit
|
else -- loc write ?
|
else -- loc write ?
|
imem_we0 := '0'; -- suppress we, is read-only
|
imem_we0 := '0'; -- suppress we, is read-only
|
imem_we1 := '0';
|
imem_we1 := '0';
|
end if;
|
end if;
|
|
|
when ibaddr_rkcs => -- RKCS -- control status register ---
|
when ibaddr_rkcs => -- RKCS -- control status register ---
|
idout(rkcs_ibf_err) := r.he or r.cse or r.wce;
|
idout(rkcs_ibf_err) := r.he or r.cse or r.wce;
|
idout(rkcs_ibf_he) := r.he;
|
idout(rkcs_ibf_he) := r.he;
|
idout(rkcs_ibf_scp) := r.scp;
|
idout(rkcs_ibf_scp) := r.scp;
|
idout(rkcs_ibf_rdy) := r.rdy;
|
idout(rkcs_ibf_rdy) := r.rdy;
|
idout(rkcs_ibf_go) := not r.rdy;
|
idout(rkcs_ibf_go) := not r.rdy;
|
|
|
if ibw1 = '1' then
|
if ibw1 = '1' then
|
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit
|
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit
|
end if;
|
end if;
|
|
|
if ibw0 = '1' then
|
if ibw0 = '1' then
|
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit
|
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit
|
if n.ide = '0' then -- if IE set to 0
|
if n.ide = '0' then -- if IE set to 0
|
n.fireq := '0'; -- cancel all pending
|
n.fireq := '0'; -- cancel all pending
|
n.sireq := (others=>'0'); -- interrupt requests
|
n.sireq := (others=>'0'); -- interrupt requests
|
end if;
|
end if;
|
|
|
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ?
|
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ?
|
if r.rdy = '1' then -- ready and GO ?
|
if r.rdy = '1' then -- ready and GO ?
|
n.scp := '0'; -- go clears scp !
|
n.scp := '0'; -- go clears scp !
|
n.rdy := '0'; -- mark busy
|
n.rdy := '0'; -- mark busy
|
n.cse := '0'; -- clear soft errors
|
n.cse := '0'; -- clear soft errors
|
n.wce := '0';
|
n.wce := '0';
|
n.fireq := '0'; -- cancel pend. int
|
n.fireq := '0'; -- cancel pend. int
|
|
|
if IB_MREQ.din(rkcs_ibf_func)=func_creset then -- control reset?
|
if IB_MREQ.din(rkcs_ibf_func)=func_creset then -- control reset?
|
n.creset := '1'; -- handle locally
|
n.creset := '1'; -- handle locally
|
else
|
else
|
ilam := '1'; -- issue lam
|
ilam := '1'; -- issue lam
|
end if;
|
end if;
|
|
|
if IB_MREQ.din(rkcs_ibf_func)=func_seek or -- if seek
|
if IB_MREQ.din(rkcs_ibf_func)=func_seek or -- if seek
|
IB_MREQ.din(rkcs_ibf_func)=func_dreset then -- or drive reset
|
IB_MREQ.din(rkcs_ibf_func)=func_dreset then -- or drive reset
|
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- drive busy
|
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- drive busy
|
if n.ide = '1' then -- if enabled
|
if n.ide = '1' then -- if enabled
|
n.fireq := '1'; -- interrupt !
|
n.fireq := '1'; -- interrupt !
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
else -- GO=0
|
else -- GO=0
|
if r.ide='0' and n.ide='1' and -- if IDE 0->1 transition
|
if r.ide='0' and n.ide='1' and -- if IDE 0->1 transition
|
r.rdy='1' then -- and controller ready
|
r.rdy='1' then -- and controller ready
|
n.fireq := '1'; -- issue interrupt
|
n.fireq := '1'; -- issue interrupt
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when ibaddr_rkda => -- RKDA -- disk address register -----
|
when ibaddr_rkda => -- RKDA -- disk address register -----
|
if ibrem = '0' then -- loc access ?
|
if ibrem = '0' then -- loc access ?
|
if r.rdy = '0' then -- controller busy ?
|
if r.rdy = '0' then -- controller busy ?
|
imem_we0 := '0'; -- suppress write
|
imem_we0 := '0'; -- suppress write
|
imem_we1 := '0';
|
imem_we1 := '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
if imem_we1 = '1' then
|
if imem_we1 = '1' then
|
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits
|
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits
|
end if;
|
end if;
|
|
|
when ibaddr_rkmr => -- RKMR -- maintenance register ------
|
when ibaddr_rkmr => -- RKMR -- maintenance register ------
|
idout := (others=>'0');
|
idout := (others=>'0');
|
idout(rkmr_ibf_rid) := r.rid;
|
idout(rkmr_ibf_rid) := r.rid;
|
idout(rkmr_ibf_crdone) := r.crdone;
|
idout(rkmr_ibf_crdone) := r.crdone;
|
idout(rkmr_ibf_sdone) := r.sbusy;
|
idout(rkmr_ibf_sdone) := r.sbusy;
|
if ibwrem = '1' then -- rem write ?
|
if ibwrem = '1' then -- rem write ?
|
n.rid := IB_MREQ.din(rkmr_ibf_rid);
|
n.rid := IB_MREQ.din(rkmr_ibf_rid);
|
|
|
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then
|
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then
|
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy);
|
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy);
|
end if;
|
end if;
|
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone);
|
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone);
|
|
|
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed
|
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed
|
n.rdy := '1';
|
n.rdy := '1';
|
n.crdone := '0';
|
n.crdone := '0';
|
if r.ide = '1' then
|
if r.ide = '1' then
|
n.fireq := '1';
|
n.fireq := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset
|
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset
|
n.creset := '1';
|
n.creset := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when others => -- all other regs
|
when others => -- all other regs
|
null;
|
null;
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
|
|
iscval := '1';
|
iscval := '1';
|
if r.sireq(7) = '1' then iscid := "111";
|
if r.sireq(7) = '1' then iscid := "111";
|
elsif r.sireq(6) = '1' then iscid := "110";
|
elsif r.sireq(6) = '1' then iscid := "110";
|
elsif r.sireq(5) = '1' then iscid := "101";
|
elsif r.sireq(5) = '1' then iscid := "101";
|
elsif r.sireq(4) = '1' then iscid := "100";
|
elsif r.sireq(4) = '1' then iscid := "100";
|
elsif r.sireq(3) = '1' then iscid := "011";
|
elsif r.sireq(3) = '1' then iscid := "011";
|
elsif r.sireq(2) = '1' then iscid := "010";
|
elsif r.sireq(2) = '1' then iscid := "010";
|
elsif r.sireq(1) = '1' then iscid := "001";
|
elsif r.sireq(1) = '1' then iscid := "001";
|
elsif r.sireq(0) = '1' then iscid := "000";
|
elsif r.sireq(0) = '1' then iscid := "000";
|
else
|
else
|
iscval := '0';
|
iscval := '0';
|
end if;
|
end if;
|
|
|
if r.ide = '1' then
|
if r.ide = '1' then
|
if r.fireq='1' or iscval='1' then
|
if r.fireq='1' or iscval='1' then
|
iei_req := '1';
|
iei_req := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if EI_ACK = '1' then -- interrupt executed
|
if EI_ACK = '1' then -- interrupt executed
|
if r.fireq = '1' then
|
if r.fireq = '1' then
|
n.scp := '0'; -- clear scp flag, is command end
|
n.scp := '0'; -- clear scp flag, is command end
|
n.fireq := '0';
|
n.fireq := '0';
|
elsif iscval = '1' then -- was a seek done
|
elsif iscval = '1' then -- was a seek done
|
n.scp := '1'; -- signal seek complete interrupt
|
n.scp := '1'; -- signal seek complete interrupt
|
n.id := iscid; -- load id
|
n.id := iscid; -- load id
|
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
|
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if icrip = '1' then -- control reset in progress ?
|
if icrip = '1' then -- control reset in progress ?
|
imem_addr := '0' & r.icnt; -- use icnt as addr
|
imem_addr := '0' & r.icnt; -- use icnt as addr
|
imem_din := (others=>'0'); -- force data to zero
|
imem_din := (others=>'0'); -- force data to zero
|
imem_we0 := '1'; -- enable writes
|
imem_we0 := '1'; -- enable writes
|
imem_we1 := '1';
|
imem_we1 := '1';
|
end if;
|
end if;
|
|
|
if CE_MSEC = '1' then -- advance sector counter every msec
|
if CE_MSEC = '1' then -- advance sector counter every msec
|
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
|
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
|
n.sc := (others=>'0');
|
n.sc := (others=>'0');
|
else
|
else
|
n.sc := slv(unsigned(r.sc) + 1);
|
n.sc := slv(unsigned(r.sc) + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
MEM_0_WE <= imem_we0;
|
MEM_0_WE <= imem_we0;
|
MEM_1_WE <= imem_we1;
|
MEM_1_WE <= imem_we1;
|
MEM_ADDR <= imem_addr;
|
MEM_ADDR <= imem_addr;
|
MEM_DIN <= imem_din;
|
MEM_DIN <= imem_din;
|
|
|
IB_SRES.dout <= idout;
|
IB_SRES.dout <= idout;
|
IB_SRES.ack <= r.ibsel and ibreq;
|
IB_SRES.ack <= r.ibsel and ibreq;
|
IB_SRES.busy <= ibhold and ibreq;
|
IB_SRES.busy <= ibhold and ibreq;
|
|
|
RB_LAM <= ilam;
|
RB_LAM <= ilam;
|
EI_REQ <= iei_req;
|
EI_REQ <= iei_req;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
|
|
end syn;
|
end syn;
|
|
|