-- $Id: ibdr_rl11.vhd 655 2015-03-04 20:35:21Z mueller $
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-- $Id: ibdr_rl11.vhd 655 2015-03-04 20:35:21Z mueller $
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--
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--
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-- Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: ibdr_rl11 - syn
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-- Module Name: ibdr_rl11 - syn
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-- Description: ibus dev(rem): RL11
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-- Description: ibus dev(rem): RL11
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--
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--
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-- Dependencies: ram_1swar_gen
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-- Dependencies: ram_1swar_gen
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
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-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2015-02-28 653 14.7 131013 xc6slx16-2 80 197 12 80 s 7.9
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-- 2015-02-28 653 14.7 131013 xc6slx16-2 80 197 12 80 s 7.9
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-- 2014-06-15 562 14.7 131013 xc6slx16-2 81 199 13 78 s 8.0
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-- 2014-06-15 562 14.7 131013 xc6slx16-2 81 199 13 78 s 8.0
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore
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-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore
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-- 2015-02-28 653 1.0 Initial verison
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-- 2015-02-28 653 1.0 Initial verison
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-- 2014-06-09 561 0.1 First draft
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-- 2014-06-09 561 0.1 First draft
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.iblib.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity ibdr_rl11 is -- ibus dev(rem): RL11
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entity ibdr_rl11 is -- ibus dev(rem): RL11
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-- fixed address: 174400
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-- fixed address: 174400
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- msec pulse
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CE_MSEC : in slbit; -- msec pulse
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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EI_ACK : in slbit -- interrupt acknowledge
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);
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);
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end ibdr_rl11;
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end ibdr_rl11;
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architecture syn of ibdr_rl11 is
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architecture syn of ibdr_rl11 is
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constant ibaddr_rl11 : slv16 := slv(to_unsigned(8#174400#,16));
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constant ibaddr_rl11 : slv16 := slv(to_unsigned(8#174400#,16));
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constant ibaddr_rlcs : slv2 := "00"; -- rlcs address offset
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constant ibaddr_rlcs : slv2 := "00"; -- rlcs address offset
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constant ibaddr_rlba : slv2 := "01"; -- rlba address offset
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constant ibaddr_rlba : slv2 := "01"; -- rlba address offset
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constant ibaddr_rlda : slv2 := "10"; -- rlda address offset
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constant ibaddr_rlda : slv2 := "10"; -- rlda address offset
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constant ibaddr_rlmp : slv2 := "11"; -- rlmp address offset
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constant ibaddr_rlmp : slv2 := "11"; -- rlmp address offset
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-- usage of 16x16 memory bank
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-- usage of 16x16 memory bank
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-- 0 0000 unused (but mirrors rlcs)
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-- 0 0000 unused (but mirrors rlcs)
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-- 1 0001 rlba
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-- 1 0001 rlba
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-- 2 0010 unused (but mirrors rlda)
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-- 2 0010 unused (but mirrors rlda)
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-- 3 0011 rlmp (1st value)
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-- 3 0011 rlmp (1st value)
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-- 4 0100 rlmp (3rd value after gs; the crc)
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-- 4 0100 rlmp (3rd value after gs; the crc)
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-- 5 0101 unused
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-- 5 0101 unused
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-- 6 0110 unused
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-- 6 0110 unused
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-- 7 0111 unused (target for bad mprem states)
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-- 7 0111 unused (target for bad mprem states)
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-- 11: 8 10-- sta(ds) (drive status)
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-- 11: 8 10-- sta(ds) (drive status)
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-- 15:12 11-- pos(ds) (drive disk address)
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-- 15:12 11-- pos(ds) (drive disk address)
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constant imem_cs : slv4 := "0000"; -- unused
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constant imem_cs : slv4 := "0000"; -- unused
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constant imem_ba : slv4 := "0001";
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constant imem_ba : slv4 := "0001";
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constant imem_da : slv4 := "0010"; -- unused
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constant imem_da : slv4 := "0010"; -- unused
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constant imem_mp : slv4 := "0011";
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constant imem_mp : slv4 := "0011";
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constant imem_crc : slv4 := "0100";
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constant imem_crc : slv4 := "0100";
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constant imem_bad : slv4 := "0111"; -- target for bad mprem states
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constant imem_bad : slv4 := "0111"; -- target for bad mprem states
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constant imem_sta : slv4 := "1000";
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constant imem_sta : slv4 := "1000";
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constant imem_pos : slv4 := "1100";
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constant imem_pos : slv4 := "1100";
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subtype imf_typ is integer range 3 downto 2;
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subtype imf_typ is integer range 3 downto 2;
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subtype imf_ds is integer range 1 downto 0;
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subtype imf_ds is integer range 1 downto 0;
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constant rlcs_ibf_err : integer := 15;
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constant rlcs_ibf_err : integer := 15;
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constant rlcs_ibf_de : integer := 14;
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constant rlcs_ibf_de : integer := 14;
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subtype rlcs_ibf_e is integer range 13 downto 10;
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subtype rlcs_ibf_e is integer range 13 downto 10;
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subtype rlcs_ibf_ds is integer range 9 downto 8;
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subtype rlcs_ibf_ds is integer range 9 downto 8;
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constant rlcs_ibf_crdy : integer := 7;
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constant rlcs_ibf_crdy : integer := 7;
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constant rlcs_ibf_ie : integer := 6;
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constant rlcs_ibf_ie : integer := 6;
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subtype rlcs_ibf_bae is integer range 5 downto 4;
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subtype rlcs_ibf_bae is integer range 5 downto 4;
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subtype rlcs_ibf_func is integer range 3 downto 1;
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subtype rlcs_ibf_func is integer range 3 downto 1;
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constant rlcs_ibf_drdy : integer := 0;
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constant rlcs_ibf_drdy : integer := 0;
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constant func_noop : slv3 := "000"; -- func: noop
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constant func_noop : slv3 := "000"; -- func: noop
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constant func_wchk : slv3 := "001"; -- func: write check
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constant func_wchk : slv3 := "001"; -- func: write check
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constant func_gs : slv3 := "010"; -- func: get status
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constant func_gs : slv3 := "010"; -- func: get status
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constant func_seek : slv3 := "011"; -- func: seek
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constant func_seek : slv3 := "011"; -- func: seek
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constant func_rhdr : slv3 := "100"; -- func: read header
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constant func_rhdr : slv3 := "100"; -- func: read header
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constant func_write : slv3 := "101"; -- func: write data
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constant func_write : slv3 := "101"; -- func: write data
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constant func_read : slv3 := "110"; -- func: read data
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constant func_read : slv3 := "110"; -- func: read data
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constant func_rnhc : slv3 := "111"; -- func: read data without header check
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constant func_rnhc : slv3 := "111"; -- func: read data without header check
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constant e_ok : slv4 := "0000"; -- e code: ok
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constant e_ok : slv4 := "0000"; -- e code: ok
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constant e_incomp : slv4 := "0001"; -- e code: operation incomplete
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constant e_incomp : slv4 := "0001"; -- e code: operation incomplete
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-- defs for rem access of rlcs; func codes
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-- defs for rem access of rlcs; func codes
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constant rfunc_wcs : slv3 := "001"; -- rem func: write cs (err,de,e,drdy)
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constant rfunc_wcs : slv3 := "001"; -- rem func: write cs (err,de,e,drdy)
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constant rfunc_wmp : slv3 := "010"; -- rem func: write mprem or mploc
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constant rfunc_wmp : slv3 := "010"; -- rem func: write mprem or mploc
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-- rlcs usage or rem func=wmp
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-- rlcs usage or rem func=wmp
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subtype rlcs_ibf_mprem is integer range 15 downto 11;
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subtype rlcs_ibf_mprem is integer range 15 downto 11;
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subtype rlcs_ibf_mploc is integer range 10 downto 8;
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subtype rlcs_ibf_mploc is integer range 10 downto 8;
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constant rlcs_ibf_ena_mprem : integer := 5;
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constant rlcs_ibf_ena_mprem : integer := 5;
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constant rlcs_ibf_ena_mploc : integer := 4;
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constant rlcs_ibf_ena_mploc : integer := 4;
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subtype rlda_ibf_seek_df is integer range 15 downto 7;
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subtype rlda_ibf_seek_df is integer range 15 downto 7;
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constant rlda_ibf_seek_hs : integer := 4;
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constant rlda_ibf_seek_hs : integer := 4;
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constant rlda_ibf_seek_dir : integer := 2;
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constant rlda_ibf_seek_dir : integer := 2;
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constant rlda_msk_seek : slv16 := "0000000000001011";
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constant rlda_msk_seek : slv16 := "0000000000001011";
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constant rlda_val_seek : slv16 := "0000000000000001";
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constant rlda_val_seek : slv16 := "0000000000000001";
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constant rlda_ibf_gs_rst : integer := 3;
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constant rlda_ibf_gs_rst : integer := 3;
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constant rlda_msk_gs : slv16 := "0000000011110111";
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constant rlda_msk_gs : slv16 := "0000000011110111";
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constant rlda_val_gs : slv16 := "0000000000000011";
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constant rlda_val_gs : slv16 := "0000000000000011";
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constant sta_ibf_wde : integer := 15; -- Write data error - always 0
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constant sta_ibf_wde : integer := 15; -- Write data error - always 0
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constant sta_ibf_che : integer := 14; -- Current head error - always 0
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constant sta_ibf_che : integer := 14; -- Current head error - always 0
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constant sta_ibf_wl : integer := 13; -- Write lock - used
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constant sta_ibf_wl : integer := 13; -- Write lock - used
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constant sta_ibf_sto : integer := 12; -- Seek time out - used
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constant sta_ibf_sto : integer := 12; -- Seek time out - used
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constant sta_ibf_spe : integer := 11; -- Spin error - used
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constant sta_ibf_spe : integer := 11; -- Spin error - used
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constant sta_ibf_wge : integer := 10; -- Write gate error - used
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constant sta_ibf_wge : integer := 10; -- Write gate error - used
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constant sta_ibf_vce : integer := 9; -- Volume check - used
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constant sta_ibf_vce : integer := 9; -- Volume check - used
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constant sta_ibf_dse : integer := 8; -- Drive select error - used
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constant sta_ibf_dse : integer := 8; -- Drive select error - used
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constant sta_ibf_dt : integer := 7; -- Drive type - used
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constant sta_ibf_dt : integer := 7; -- Drive type - used
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constant sta_ibf_hs : integer := 6; -- Head select - used
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constant sta_ibf_hs : integer := 6; -- Head select - used
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constant sta_ibf_co : integer := 5; -- Cover open - used
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constant sta_ibf_co : integer := 5; -- Cover open - used
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constant sta_ibf_ho : integer := 4; -- Heads out - used
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constant sta_ibf_ho : integer := 4; -- Heads out - used
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constant sta_ibf_bh : integer := 3; -- Brush home - always 1
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constant sta_ibf_bh : integer := 3; -- Brush home - always 1
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subtype sta_ibf_st is integer range 2 downto 0; -- Drive state
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subtype sta_ibf_st is integer range 2 downto 0; -- Drive state
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constant st_load : slv3 := "000"; -- st: Load(ing) cartidge - used
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constant st_load : slv3 := "000"; -- st: Load(ing) cartidge - used
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constant st_spin : slv3 := "001"; -- st: Spin(ing) up - !unused!
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constant st_spin : slv3 := "001"; -- st: Spin(ing) up - !unused!
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constant st_brush : slv3 := "010"; -- st: Brush(ing) cycle - !unused!
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constant st_brush : slv3 := "010"; -- st: Brush(ing) cycle - !unused!
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constant st_hload : slv3 := "011"; -- st: Load(ing) heads - !unused!
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constant st_hload : slv3 := "011"; -- st: Load(ing) heads - !unused!
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constant st_seek : slv3 := "100"; -- st: Seek(ing) - may be used
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constant st_seek : slv3 := "100"; -- st: Seek(ing) - may be used
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constant st_lock : slv3 := "101"; -- st: Lock(ed) on - used
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constant st_lock : slv3 := "101"; -- st: Lock(ed) on - used
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constant st_unl : slv3 := "110"; -- st: Unload(ing) heads - !unused!
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constant st_unl : slv3 := "110"; -- st: Unload(ing) heads - !unused!
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constant st_down : slv3 := "111"; -- st: Spin(ing) down - !unused!
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constant st_down : slv3 := "111"; -- st: Spin(ing) down - !unused!
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-- only two mayor drive states are used
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-- only two mayor drive states are used
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-- on: st=lock; ho=1; co=0; ( file connected in backend)
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-- on: st=lock; ho=1; co=0; ( file connected in backend)
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-- off: st=load; ho=0; co=1; (no file connected in backend)
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-- off: st=load; ho=0; co=1; (no file connected in backend)
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subtype pos_ibf_ca is integer range 15 downto 7;
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subtype pos_ibf_ca is integer range 15 downto 7;
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constant pos_ibf_hs : integer := 6;
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constant pos_ibf_hs : integer := 6;
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subtype pos_ibf_sa is integer range 5 downto 0;
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subtype pos_ibf_sa is integer range 5 downto 0;
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constant mploc_mp : slv3 := "000"; -- return imem(mp)
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constant mploc_mp : slv3 := "000"; -- return imem(mp)
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constant mploc_sta : slv3 := "001"; -- return sta(ds)
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constant mploc_sta : slv3 := "001"; -- return sta(ds)
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constant mploc_pos : slv3 := "010"; -- return pos(ds)
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constant mploc_pos : slv3 := "010"; -- return pos(ds)
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constant mploc_zero : slv3 := "011"; -- return 0
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constant mploc_zero : slv3 := "011"; -- return 0
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constant mploc_crc : slv3 := "100"; -- return imem(crc)
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constant mploc_crc : slv3 := "100"; -- return imem(crc)
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constant mprem_f_map : integer := 4; -- mprem map enable
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constant mprem_f_map : integer := 4; -- mprem map enable
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subtype mprem_f_addr is integer range 3 downto 0;
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subtype mprem_f_addr is integer range 3 downto 0;
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constant mprem_f_seq : integer := 3; -- mprem seq enable
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constant mprem_f_seq : integer := 3; -- mprem seq enable
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subtype mprem_f_state is integer range 2 downto 0;
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subtype mprem_f_state is integer range 2 downto 0;
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constant mprem_mapseq : slv2 := "11"; -- enable map + seq
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constant mprem_mapseq : slv2 := "11"; -- enable map + seq
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constant mprem_s_mp : slv3 := "000"; -- access imem(mp)
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constant mprem_s_mp : slv3 := "000"; -- access imem(mp)
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constant mprem_s_sta : slv3 := "001"; -- access sta(ds)
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constant mprem_s_sta : slv3 := "001"; -- access sta(ds)
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constant mprem_s_pos : slv3 := "010"; -- access pos(ds)
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constant mprem_s_pos : slv3 := "010"; -- access pos(ds)
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constant mprem_init : slv5 := "10000"; -- enable map,fix, show mp
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constant mprem_init : slv5 := "10000"; -- enable map,fix, show mp
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constant ca_max_rl01 : slv9 := "011111111"; -- max cylinder for RL01 (255)
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constant ca_max_rl01 : slv9 := "011111111"; -- max cylinder for RL01 (255)
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constant ca_max_rl02 : slv9 := "111111111"; -- max cylinder for RL02 (511)
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constant ca_max_rl02 : slv9 := "111111111"; -- max cylinder for RL02 (511)
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type state_type is (
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type state_type is (
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s_idle, -- idle: handle ibus
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s_idle, -- idle: handle ibus
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s_csread, -- csread: handle cs read
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s_csread, -- csread: handle cs read
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s_gs_rpos, -- gs_rpos: read pos(ds)
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s_gs_rpos, -- gs_rpos: read pos(ds)
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s_gs_sta, -- gs_sta: handle status
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s_gs_sta, -- gs_sta: handle status
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s_seek_rsta, -- seek_rsta: read sta(ds)
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s_seek_rsta, -- seek_rsta: read sta(ds)
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s_seek_rpos, -- seek_rpos: read pos(ds)
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s_seek_rpos, -- seek_rpos: read pos(ds)
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s_seek_clip, -- seek_clip: clip new ca
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s_seek_clip, -- seek_clip: clip new ca
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s_seek_wpos, -- seek_wpos: write pos(ds)
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s_seek_wpos, -- seek_wpos: write pos(ds)
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s_init -- init: handle init
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s_init -- init: handle init
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);
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);
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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ibsel : slbit; -- ibus select
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state : state_type; -- state
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state : state_type; -- state
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iaddr : slv4; -- init addr counter
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iaddr : slv4; -- init addr counter
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cserr : slbit; -- rlcs: composite error
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cserr : slbit; -- rlcs: composite error
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csde : slbit; -- rlcs: drive error
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csde : slbit; -- rlcs: drive error
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cse : slv4; -- rlcs: error
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cse : slv4; -- rlcs: error
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csds : slv2; -- rlcs: drive select
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csds : slv2; -- rlcs: drive select
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cscrdy : slbit; -- rlcs: controller ready
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cscrdy : slbit; -- rlcs: controller ready
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csie : slbit; -- rlcs: interrupt enable
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csie : slbit; -- rlcs: interrupt enable
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csbae : slv2; -- rlcs: bus address extenstion
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csbae : slv2; -- rlcs: bus address extenstion
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csfunc : slv3; -- rlcs: function code
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csfunc : slv3; -- rlcs: function code
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csdrdy : slbit; -- rlcs: drive ready
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csdrdy : slbit; -- rlcs: drive ready
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da : slv16; -- rlda shadow reg
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da : slv16; -- rlda shadow reg
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gshs : slbit; -- gs: pos(ds)(hs) (head select)
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gshs : slbit; -- gs: pos(ds)(hs) (head select)
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seekdt : slbit; -- seek: drive type: 0=RL01, 1=RL02
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seekdt : slbit; -- seek: drive type: 0=RL01, 1=RL02
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seekcan: slv10; -- seek: cylinder address, new
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seekcan: slv10; -- seek: cylinder address, new
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seekcac: slv9; -- seek: cylinder address, clipped
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seekcac: slv9; -- seek: cylinder address, clipped
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ireq : slbit; -- interrupt request flag
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ireq : slbit; -- interrupt request flag
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mploc : slv3; -- mp loc state
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mploc : slv3; -- mp loc state
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mprem : slv5; -- mp rem state
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mprem : slv5; -- mp rem state
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crdone : slbit; -- control reset done since last fdone
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crdone : slbit; -- control reset done since last fdone
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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'0', -- ibsel
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'0', -- ibsel
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s_init, -- state
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s_init, -- state
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imem_ba, -- iaddr
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imem_ba, -- iaddr
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'0','0', -- cserr,csde
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'0','0', -- cserr,csde
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(others=>'0'), -- cse
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(others=>'0'), -- cse
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(others=>'0'), -- csds
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(others=>'0'), -- csds
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'1','0', -- cscrdy, csie
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'1','0', -- cscrdy, csie
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(others=>'0'), -- csbae
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(others=>'0'), -- csbae
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(others=>'0'), -- csfunc
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(others=>'0'), -- csfunc
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'0', -- csdrdy
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'0', -- csdrdy
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(others=>'0'), -- da
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(others=>'0'), -- da
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'0', -- gshs
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'0', -- gshs
|
'0', -- seekdt
|
'0', -- seekdt
|
(others=>'0'), -- seekcan
|
(others=>'0'), -- seekcan
|
(others=>'0'), -- seekcac
|
(others=>'0'), -- seekcac
|
'0', -- ireq
|
'0', -- ireq
|
mploc_mp, -- mploc
|
mploc_mp, -- mploc
|
mprem_init, -- mprem
|
mprem_init, -- mprem
|
'1' -- crdone
|
'1' -- crdone
|
);
|
);
|
|
|
signal R_REGS : regs_type := regs_init;
|
signal R_REGS : regs_type := regs_init;
|
signal N_REGS : regs_type := regs_init;
|
signal N_REGS : regs_type := regs_init;
|
|
|
signal MEM_1_WE : slbit := '0';
|
signal MEM_1_WE : slbit := '0';
|
signal MEM_0_WE : slbit := '0';
|
signal MEM_0_WE : slbit := '0';
|
signal MEM_ADDR : slv4 := (others=>'0');
|
signal MEM_ADDR : slv4 := (others=>'0');
|
signal MEM_DIN : slv16 := (others=>'0');
|
signal MEM_DIN : slv16 := (others=>'0');
|
signal MEM_DOUT : slv16 := (others=>'0');
|
signal MEM_DOUT : slv16 := (others=>'0');
|
|
|
begin
|
begin
|
|
|
MEM_1 : ram_1swar_gen
|
MEM_1 : ram_1swar_gen
|
generic map (
|
generic map (
|
AWIDTH => 4,
|
AWIDTH => 4,
|
DWIDTH => 8)
|
DWIDTH => 8)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
WE => MEM_1_WE,
|
WE => MEM_1_WE,
|
ADDR => MEM_ADDR,
|
ADDR => MEM_ADDR,
|
DI => MEM_DIN(ibf_byte1),
|
DI => MEM_DIN(ibf_byte1),
|
DO => MEM_DOUT(ibf_byte1));
|
DO => MEM_DOUT(ibf_byte1));
|
|
|
MEM_0 : ram_1swar_gen
|
MEM_0 : ram_1swar_gen
|
generic map (
|
generic map (
|
AWIDTH => 4,
|
AWIDTH => 4,
|
DWIDTH => 8)
|
DWIDTH => 8)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
WE => MEM_0_WE,
|
WE => MEM_0_WE,
|
ADDR => MEM_ADDR,
|
ADDR => MEM_ADDR,
|
DI => MEM_DIN(ibf_byte0),
|
DI => MEM_DIN(ibf_byte0),
|
DO => MEM_DOUT(ibf_byte0));
|
DO => MEM_DOUT(ibf_byte0));
|
|
|
proc_regs: process (CLK)
|
proc_regs: process (CLK)
|
begin
|
begin
|
if rising_edge(CLK) then
|
if rising_edge(CLK) then
|
if BRESET='1' then
|
if BRESET='1' then
|
R_REGS <= regs_init;
|
R_REGS <= regs_init;
|
else
|
else
|
R_REGS <= N_REGS;
|
R_REGS <= N_REGS;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process proc_regs;
|
end process proc_regs;
|
|
|
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
|
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
|
variable r : regs_type := regs_init;
|
variable r : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
variable ibhold : slbit := '0';
|
variable ibhold : slbit := '0';
|
variable idout : slv16 := (others=>'0');
|
variable idout : slv16 := (others=>'0');
|
variable ibrem : slbit := '0';
|
variable ibrem : slbit := '0';
|
variable ibreq : slbit := '0';
|
variable ibreq : slbit := '0';
|
variable ibrd : slbit := '0';
|
variable ibrd : slbit := '0';
|
variable ibw0 : slbit := '0';
|
variable ibw0 : slbit := '0';
|
variable ibw1 : slbit := '0';
|
variable ibw1 : slbit := '0';
|
variable ibwrem : slbit := '0';
|
variable ibwrem : slbit := '0';
|
variable ilam : slbit := '0';
|
variable ilam : slbit := '0';
|
variable iei_req : slbit := '0';
|
variable iei_req : slbit := '0';
|
|
|
variable imem_we0 : slbit := '0';
|
variable imem_we0 : slbit := '0';
|
variable imem_we1 : slbit := '0';
|
variable imem_we1 : slbit := '0';
|
variable imem_addr : slv4 := (others=>'0');
|
variable imem_addr : slv4 := (others=>'0');
|
variable imem_din : slv16 := (others=>'0');
|
variable imem_din : slv16 := (others=>'0');
|
begin
|
begin
|
|
|
r := R_REGS;
|
r := R_REGS;
|
n := R_REGS;
|
n := R_REGS;
|
|
|
ibhold := '0';
|
ibhold := '0';
|
idout := (others=>'0');
|
idout := (others=>'0');
|
ibrem := IB_MREQ.racc;
|
ibrem := IB_MREQ.racc;
|
ibreq := IB_MREQ.re or IB_MREQ.we;
|
ibreq := IB_MREQ.re or IB_MREQ.we;
|
ibrd := IB_MREQ.re;
|
ibrd := IB_MREQ.re;
|
ibw0 := IB_MREQ.we and IB_MREQ.be0;
|
ibw0 := IB_MREQ.we and IB_MREQ.be0;
|
ibw1 := IB_MREQ.we and IB_MREQ.be1;
|
ibw1 := IB_MREQ.we and IB_MREQ.be1;
|
ibwrem := IB_MREQ.we and ibrem;
|
ibwrem := IB_MREQ.we and ibrem;
|
ilam := '0';
|
ilam := '0';
|
iei_req := '0';
|
iei_req := '0';
|
|
|
imem_we0 := '0';
|
imem_we0 := '0';
|
imem_we1 := '0';
|
imem_we1 := '0';
|
imem_addr := "00" & IB_MREQ.addr(2 downto 1);
|
imem_addr := "00" & IB_MREQ.addr(2 downto 1);
|
imem_din := IB_MREQ.din;
|
imem_din := IB_MREQ.din;
|
|
|
-- ibus address decoder
|
-- ibus address decoder
|
n.ibsel := '0';
|
n.ibsel := '0';
|
if IB_MREQ.aval = '1' and
|
if IB_MREQ.aval = '1' and
|
IB_MREQ.addr(12 downto 3)=ibaddr_rl11(12 downto 3) then
|
IB_MREQ.addr(12 downto 3)=ibaddr_rl11(12 downto 3) then
|
n.ibsel := '1';
|
n.ibsel := '1';
|
end if;
|
end if;
|
|
|
-- internal state machine
|
-- internal state machine
|
case r.state is
|
case r.state is
|
when s_idle => -- idle: handle ibus -----------------
|
when s_idle => -- idle: handle ibus -----------------
|
|
|
if r.ibsel='1' then -- selected
|
if r.ibsel='1' then -- selected
|
idout := MEM_DOUT;
|
idout := MEM_DOUT;
|
imem_we0 := ibw0;
|
imem_we0 := ibw0;
|
imem_we1 := ibw1;
|
imem_we1 := ibw1;
|
|
|
case IB_MREQ.addr(2 downto 1) is
|
case IB_MREQ.addr(2 downto 1) is
|
|
|
when ibaddr_rlcs => -- RLCS - control register -------
|
when ibaddr_rlcs => -- RLCS - control register -------
|
imem_we0 := '0'; -- MEM not used for rlcs
|
imem_we0 := '0'; -- MEM not used for rlcs
|
imem_we1 := '0';
|
imem_we1 := '0';
|
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
|
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
|
|
|
-- determine DRDY
|
-- determine DRDY
|
n.csdrdy := '1';
|
n.csdrdy := '1';
|
if MEM_DOUT(sta_ibf_st) /= st_lock or -- drive not on and locked
|
if MEM_DOUT(sta_ibf_st) /= st_lock or -- drive not on and locked
|
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
|
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
|
-- ??? also CRDY=0 here ???
|
-- ??? also CRDY=0 here ???
|
n.csdrdy := '0';
|
n.csdrdy := '0';
|
end if;
|
end if;
|
|
|
-- determine DE and ERR
|
-- determine DE and ERR
|
n.cserr := '0';
|
n.cserr := '0';
|
if MEM_DOUT(sta_ibf_st) = st_load or -- drive off
|
if MEM_DOUT(sta_ibf_st) = st_load or -- drive off
|
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
|
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
|
n.csde := '1';
|
n.csde := '1';
|
n.cserr := '1';
|
n.cserr := '1';
|
end if;
|
end if;
|
if r.csde = '1' or r.cse /= e_ok then
|
if r.csde = '1' or r.cse /= e_ok then
|
n.cserr := '1';
|
n.cserr := '1';
|
end if;
|
end if;
|
|
|
if ibrd = '1' then -- cs read
|
if ibrd = '1' then -- cs read
|
ibhold := '1';
|
ibhold := '1';
|
n.state := s_csread;
|
n.state := s_csread;
|
|
|
elsif IB_MREQ.we = '1' then -- cs write
|
elsif IB_MREQ.we = '1' then -- cs write
|
|
|
if ibrem = '0' then -- loc write access
|
if ibrem = '0' then -- loc write access
|
|
|
if IB_MREQ.be1 = '1' then
|
if IB_MREQ.be1 = '1' then
|
if r.cscrdy = '1' then -- freeze csds when busy
|
if r.cscrdy = '1' then -- freeze csds when busy
|
n.csds := IB_MREQ.din(rlcs_ibf_ds);
|
n.csds := IB_MREQ.din(rlcs_ibf_ds);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if IB_MREQ.be0 = '1' then
|
if IB_MREQ.be0 = '1' then
|
n.csie := IB_MREQ.din(rlcs_ibf_ie);
|
n.csie := IB_MREQ.din(rlcs_ibf_ie);
|
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
|
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
|
|
|
if r.cscrdy = '1' then -- controller ready
|
if r.cscrdy = '1' then -- controller ready
|
|
|
n.csfunc := IB_MREQ.din(rlcs_ibf_func); -- latch func
|
n.csfunc := IB_MREQ.din(rlcs_ibf_func); -- latch func
|
if IB_MREQ.din(rlcs_ibf_crdy) = '1' then -- no crdy clr
|
if IB_MREQ.din(rlcs_ibf_crdy) = '1' then -- no crdy clr
|
if IB_MREQ.din(rlcs_ibf_ie) = '1' and r.csie = '0' then
|
if IB_MREQ.din(rlcs_ibf_ie) = '1' and r.csie = '0' then
|
n.ireq := '1';
|
n.ireq := '1';
|
end if;
|
end if;
|
else -- crdy clr --> handle func
|
else -- crdy clr --> handle func
|
|
|
n.cserr := '0'; -- clear errors
|
n.cserr := '0'; -- clear errors
|
n.csde := '0';
|
n.csde := '0';
|
n.cse := "0000";
|
n.cse := "0000";
|
|
|
case IB_MREQ.din(rlcs_ibf_func) is
|
case IB_MREQ.din(rlcs_ibf_func) is
|
when func_noop => -- noop -------
|
when func_noop => -- noop -------
|
n.ireq := r.csie; -- interrupt
|
n.ireq := r.csie; -- interrupt
|
|
|
when func_gs => -- get status -
|
when func_gs => -- get status -
|
if (r.da and rlda_msk_gs) /= rlda_val_gs then
|
if (r.da and rlda_msk_gs) /= rlda_val_gs then
|
n.cserr := '1';
|
n.cserr := '1';
|
n.cse := e_incomp;
|
n.cse := e_incomp;
|
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
|
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
|
else
|
else
|
ibhold := '1';
|
ibhold := '1';
|
n.state := s_gs_rpos;
|
n.state := s_gs_rpos;
|
end if;
|
end if;
|
|
|
when func_seek => -- seek -------
|
when func_seek => -- seek -------
|
if (r.da and rlda_msk_seek) /= rlda_val_seek then
|
if (r.da and rlda_msk_seek) /= rlda_val_seek then
|
n.cserr := '1';
|
n.cserr := '1';
|
n.cse := e_incomp;
|
n.cse := e_incomp;
|
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
|
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
|
else
|
else
|
ibhold := '1';
|
ibhold := '1';
|
n.state := s_seek_rsta;
|
n.state := s_seek_rsta;
|
end if;
|
end if;
|
|
|
when others => -- all other funcs
|
when others => -- all other funcs
|
n.cscrdy := '0'; -- signal cntl busy
|
n.cscrdy := '0'; -- signal cntl busy
|
ilam := '1'; -- issue lam
|
ilam := '1'; -- issue lam
|
end case;
|
end case;
|
|
|
end if; -- else IB_MREQ.din(rlcs_ibf_crdy) = '1'
|
end if; -- else IB_MREQ.din(rlcs_ibf_crdy) = '1'
|
end if; -- r.cscrdy = '1'
|
end if; -- r.cscrdy = '1'
|
end if; -- IB_MREQ.be0 = '1'
|
end if; -- IB_MREQ.be0 = '1'
|
|
|
else -- rem write access
|
else -- rem write access
|
case IB_MREQ.din(rlcs_ibf_func) is
|
case IB_MREQ.din(rlcs_ibf_func) is
|
|
|
when rfunc_wcs =>
|
when rfunc_wcs =>
|
n.csde := IB_MREQ.din(rlcs_ibf_de);
|
n.csde := IB_MREQ.din(rlcs_ibf_de);
|
n.cse := IB_MREQ.din(rlcs_ibf_e);
|
n.cse := IB_MREQ.din(rlcs_ibf_e);
|
n.cscrdy := IB_MREQ.din(rlcs_ibf_crdy);
|
n.cscrdy := IB_MREQ.din(rlcs_ibf_crdy);
|
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
|
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
|
if r.cscrdy = '0' and IB_MREQ.din(rlcs_ibf_crdy) = '1' then
|
if r.cscrdy = '0' and IB_MREQ.din(rlcs_ibf_crdy) = '1' then
|
n.ireq := r.csie;
|
n.ireq := r.csie;
|
end if;
|
end if;
|
|
|
when rfunc_wmp =>
|
when rfunc_wmp =>
|
if IB_MREQ.din(rlcs_ibf_ena_mprem) = '1' then
|
if IB_MREQ.din(rlcs_ibf_ena_mprem) = '1' then
|
n.mprem := IB_MREQ.din(rlcs_ibf_mprem);
|
n.mprem := IB_MREQ.din(rlcs_ibf_mprem);
|
end if;
|
end if;
|
if IB_MREQ.din(rlcs_ibf_ena_mploc) = '1' then
|
if IB_MREQ.din(rlcs_ibf_ena_mploc) = '1' then
|
n.mploc := IB_MREQ.din(rlcs_ibf_mploc);
|
n.mploc := IB_MREQ.din(rlcs_ibf_mploc);
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when ibaddr_rlba => -- RLBA - bus address register ---
|
when ibaddr_rlba => -- RLBA - bus address register ---
|
imem_din(0) := '0'; -- lsb forced 0
|
imem_din(0) := '0'; -- lsb forced 0
|
null;
|
null;
|
|
|
when ibaddr_rlda => -- RLDA - disk address register --
|
when ibaddr_rlda => -- RLDA - disk address register --
|
if ibw1 = '1' then
|
if ibw1 = '1' then
|
n.da(15 downto 8) := IB_MREQ.din(15 downto 8);
|
n.da(15 downto 8) := IB_MREQ.din(15 downto 8);
|
end if;
|
end if;
|
if ibw0 = '1' then
|
if ibw0 = '1' then
|
n.da( 7 downto 0) := IB_MREQ.din( 7 downto 0);
|
n.da( 7 downto 0) := IB_MREQ.din( 7 downto 0);
|
end if;
|
end if;
|
|
|
when ibaddr_rlmp => -- RLMP - multipurpose register --
|
when ibaddr_rlmp => -- RLMP - multipurpose register --
|
|
|
if ibrem = '0' then -- loc access
|
if ibrem = '0' then -- loc access
|
if ibrd = '1' then -- loc mp read
|
if ibrd = '1' then -- loc mp read
|
case r.mploc is
|
case r.mploc is
|
when mploc_mp => -- return imem(mp)
|
when mploc_mp => -- return imem(mp)
|
null;
|
null;
|
when mploc_sta => -- return sta(ds)
|
when mploc_sta => -- return sta(ds)
|
imem_addr := imem_sta(imf_typ) & r.csds;
|
imem_addr := imem_sta(imf_typ) & r.csds;
|
when mploc_pos => -- return pos(ds)
|
when mploc_pos => -- return pos(ds)
|
imem_addr := imem_pos(imf_typ) & r.csds;
|
imem_addr := imem_pos(imf_typ) & r.csds;
|
n.mploc := mploc_zero;
|
n.mploc := mploc_zero;
|
when mploc_zero => -- return 0
|
when mploc_zero => -- return 0
|
idout := (others => '0');
|
idout := (others => '0');
|
n.mploc := mploc_crc;
|
n.mploc := mploc_crc;
|
when mploc_crc => -- return imem(crc)
|
when mploc_crc => -- return imem(crc)
|
imem_addr := imem_crc;
|
imem_addr := imem_crc;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
elsif IB_MREQ.we = '1' then -- loc mp write
|
elsif IB_MREQ.we = '1' then -- loc mp write
|
n.mploc := mploc_mp; -- use main mp reg in future
|
n.mploc := mploc_mp; -- use main mp reg in future
|
end if;
|
end if;
|
|
|
else -- rem access
|
else -- rem access
|
if r.mprem(mprem_f_map) = '0' then -- map off - fixed addr
|
if r.mprem(mprem_f_map) = '0' then -- map off - fixed addr
|
imem_addr := r.mprem(mprem_f_addr);
|
imem_addr := r.mprem(mprem_f_addr);
|
else -- sequence
|
else -- sequence
|
case r.mprem(mprem_f_state) is
|
case r.mprem(mprem_f_state) is
|
when mprem_s_mp => -- mp {used as wc}
|
when mprem_s_mp => -- mp {used as wc}
|
imem_addr := imem_mp;
|
imem_addr := imem_mp;
|
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
|
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
|
n.mprem := mprem_mapseq & mprem_s_sta;
|
n.mprem := mprem_mapseq & mprem_s_sta;
|
end if;
|
end if;
|
when mprem_s_sta => -- sta(ds)
|
when mprem_s_sta => -- sta(ds)
|
imem_addr := imem_sta(imf_typ) & r.csds;
|
imem_addr := imem_sta(imf_typ) & r.csds;
|
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
|
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
|
n.mprem := mprem_mapseq & mprem_s_pos;
|
n.mprem := mprem_mapseq & mprem_s_pos;
|
end if;
|
end if;
|
when mprem_s_pos => -- pos(ds)
|
when mprem_s_pos => -- pos(ds)
|
imem_addr := imem_pos(imf_typ) & r.csds;
|
imem_addr := imem_pos(imf_typ) & r.csds;
|
when others => -- bad state
|
when others => -- bad state
|
imem_addr := imem_bad;
|
imem_addr := imem_bad;
|
|
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
|
|
when s_csread => -- csread: handle cs read -----------
|
when s_csread => -- csread: handle cs read -----------
|
idout(rlcs_ibf_err) := r.cserr;
|
idout(rlcs_ibf_err) := r.cserr;
|
idout(rlcs_ibf_de) := r.csde;
|
idout(rlcs_ibf_de) := r.csde;
|
idout(rlcs_ibf_e) := r.cse;
|
idout(rlcs_ibf_e) := r.cse;
|
idout(rlcs_ibf_ds) := r.csds;
|
idout(rlcs_ibf_ds) := r.csds;
|
idout(rlcs_ibf_crdy) := r.cscrdy;
|
idout(rlcs_ibf_crdy) := r.cscrdy;
|
idout(rlcs_ibf_ie) := r.csie;
|
idout(rlcs_ibf_ie) := r.csie;
|
idout(rlcs_ibf_bae) := r.csbae;
|
idout(rlcs_ibf_bae) := r.csbae;
|
idout(rlcs_ibf_func) := r.csfunc;
|
idout(rlcs_ibf_func) := r.csfunc;
|
idout(rlcs_ibf_drdy) := r.csdrdy;
|
idout(rlcs_ibf_drdy) := r.csdrdy;
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
when s_gs_rpos => -- gs_rpos: read pos(ds) -----------
|
when s_gs_rpos => -- gs_rpos: read pos(ds) -----------
|
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
|
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
|
n.gshs := MEM_DOUT(pos_ibf_hs); -- get hs bit
|
n.gshs := MEM_DOUT(pos_ibf_hs); -- get hs bit
|
ibhold := r.ibsel;
|
ibhold := r.ibsel;
|
n.state := s_gs_sta;
|
n.state := s_gs_sta;
|
|
|
when s_gs_sta => -- gs_sta: handle status -----------
|
when s_gs_sta => -- gs_sta: handle status -----------
|
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
|
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
|
imem_we0 := '1'; -- always update
|
imem_we0 := '1'; -- always update
|
imem_we1 := '1';
|
imem_we1 := '1';
|
imem_din := MEM_DOUT;
|
imem_din := MEM_DOUT;
|
imem_din(sta_ibf_hs) := r.gshs;
|
imem_din(sta_ibf_hs) := r.gshs;
|
if r.da(rlda_ibf_gs_rst) = '1' then -- if RST set
|
if r.da(rlda_ibf_gs_rst) = '1' then -- if RST set
|
imem_din(sta_ibf_wde) := '0'; -- clear error bits
|
imem_din(sta_ibf_wde) := '0'; -- clear error bits
|
imem_din(sta_ibf_che) := '0';
|
imem_din(sta_ibf_che) := '0';
|
imem_din(sta_ibf_sto) := '0';
|
imem_din(sta_ibf_sto) := '0';
|
imem_din(sta_ibf_spe) := '0';
|
imem_din(sta_ibf_spe) := '0';
|
imem_din(sta_ibf_wge) := '0';
|
imem_din(sta_ibf_wge) := '0';
|
imem_din(sta_ibf_vce) := '0';
|
imem_din(sta_ibf_vce) := '0';
|
imem_din(sta_ibf_dse) := '0';
|
imem_din(sta_ibf_dse) := '0';
|
end if;
|
end if;
|
n.mploc := mploc_sta; -- use sta(ds) as mp
|
n.mploc := mploc_sta; -- use sta(ds) as mp
|
n.ireq := r.csie; -- interrupt
|
n.ireq := r.csie; -- interrupt
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
when s_seek_rsta => -- seek_rsta: read sta(ds) -----------
|
when s_seek_rsta => -- seek_rsta: read sta(ds) -----------
|
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
|
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
|
n.seekdt := MEM_DOUT(sta_ibf_dt);
|
n.seekdt := MEM_DOUT(sta_ibf_dt);
|
imem_din := MEM_DOUT;
|
imem_din := MEM_DOUT;
|
if MEM_DOUT(sta_ibf_st) /= st_lock then -- drive off
|
if MEM_DOUT(sta_ibf_st) /= st_lock then -- drive off
|
imem_we0 := '1'; -- update sta
|
imem_we0 := '1'; -- update sta
|
imem_we1 := '1';
|
imem_we1 := '1';
|
imem_din(sta_ibf_sto) := '1'; -- set STO (seek time out)
|
imem_din(sta_ibf_sto) := '1'; -- set STO (seek time out)
|
n.cse := e_incomp;
|
n.cse := e_incomp;
|
n.ireq := r.csie; -- interrupt
|
n.ireq := r.csie; -- interrupt
|
n.state := s_idle;
|
n.state := s_idle;
|
else -- drive on
|
else -- drive on
|
ibhold := r.ibsel;
|
ibhold := r.ibsel;
|
n.state := s_seek_rpos;
|
n.state := s_seek_rpos;
|
end if;
|
end if;
|
|
|
when s_seek_rpos => -- seek_rpos: read pos(ds) -----------
|
when s_seek_rpos => -- seek_rpos: read pos(ds) -----------
|
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
|
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
|
if r.da(rlda_ibf_seek_dir) = '1' then
|
if r.da(rlda_ibf_seek_dir) = '1' then
|
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) +
|
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) +
|
unsigned('0' & r.da(rlda_ibf_seek_df)) );
|
unsigned('0' & r.da(rlda_ibf_seek_df)) );
|
else
|
else
|
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) -
|
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) -
|
unsigned('0' & r.da(rlda_ibf_seek_df)) );
|
unsigned('0' & r.da(rlda_ibf_seek_df)) );
|
end if;
|
end if;
|
ibhold := r.ibsel;
|
ibhold := r.ibsel;
|
n.state := s_seek_clip;
|
n.state := s_seek_clip;
|
|
|
when s_seek_clip => -- seek_clip: clip new ca ------------
|
when s_seek_clip => -- seek_clip: clip new ca ------------
|
n.seekcac := r.seekcan(8 downto 0);
|
n.seekcac := r.seekcan(8 downto 0);
|
-- new ca overflowed ? for RL02 (9) and for RL01 (9:8) must be "00"
|
-- new ca overflowed ? for RL02 (9) and for RL01 (9:8) must be "00"
|
if r.seekcan(9) = '1' or
|
if r.seekcan(9) = '1' or
|
(r.seekdt = '0' and r.seekcan(8) = '1') then
|
(r.seekdt = '0' and r.seekcan(8) = '1') then
|
if r.da(rlda_ibf_seek_dir) = '1' then -- outward seek
|
if r.da(rlda_ibf_seek_dir) = '1' then -- outward seek
|
if r.seekdt = '1' then -- is RL02
|
if r.seekdt = '1' then -- is RL02
|
n.seekcac := ca_max_rl02; -- clip to RL02 max ca
|
n.seekcac := ca_max_rl02; -- clip to RL02 max ca
|
else -- is RL01
|
else -- is RL01
|
n.seekcac := ca_max_rl01; -- clip to RL01 max ca
|
n.seekcac := ca_max_rl01; -- clip to RL01 max ca
|
end if;
|
end if;
|
else -- inward seek
|
else -- inward seek
|
n.seekcac := "000000000"; -- clip to 0
|
n.seekcac := "000000000"; -- clip to 0
|
end if;
|
end if;
|
end if;
|
end if;
|
ibhold := r.ibsel;
|
ibhold := r.ibsel;
|
n.state := s_seek_wpos;
|
n.state := s_seek_wpos;
|
|
|
when s_seek_wpos => -- seek_wpos: write pos(ds) ----------
|
when s_seek_wpos => -- seek_wpos: write pos(ds) ----------
|
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
|
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
|
imem_we0 := '1';
|
imem_we0 := '1';
|
imem_we1 := '1';
|
imem_we1 := '1';
|
imem_din := MEM_DOUT;
|
imem_din := MEM_DOUT;
|
imem_din(pos_ibf_ca) := r.seekcac;
|
imem_din(pos_ibf_ca) := r.seekcac;
|
imem_din(pos_ibf_hs) := r.da(rlda_ibf_seek_hs);
|
imem_din(pos_ibf_hs) := r.da(rlda_ibf_seek_hs);
|
n.ireq := r.csie; -- interrupt
|
n.ireq := r.csie; -- interrupt
|
n.state := s_idle;
|
n.state := s_idle;
|
|
|
when s_init => -- init: handle init -----------------
|
when s_init => -- init: handle init -----------------
|
ibhold := r.ibsel; -- hold ibus when controller busy
|
ibhold := r.ibsel; -- hold ibus when controller busy
|
imem_addr := r.iaddr;
|
imem_addr := r.iaddr;
|
imem_din := (others=>'0');
|
imem_din := (others=>'0');
|
imem_we0 := '1';
|
imem_we0 := '1';
|
imem_we1 := '1';
|
imem_we1 := '1';
|
if r.iaddr(imf_typ) = imem_sta(imf_typ) then -- if sta(x)
|
if r.iaddr(imf_typ) = imem_sta(imf_typ) then -- if sta(x)
|
imem_din := MEM_DOUT; -- keep state
|
imem_din := MEM_DOUT; -- keep state
|
imem_din(sta_ibf_wde) := '0'; -- and clear err
|
imem_din(sta_ibf_wde) := '0'; -- and clear err
|
imem_din(sta_ibf_che) := '0';
|
imem_din(sta_ibf_che) := '0';
|
imem_din(sta_ibf_sto) := '0';
|
imem_din(sta_ibf_sto) := '0';
|
imem_din(sta_ibf_spe) := '0';
|
imem_din(sta_ibf_spe) := '0';
|
imem_din(sta_ibf_wge) := '0';
|
imem_din(sta_ibf_wge) := '0';
|
imem_din(sta_ibf_vce) := '0';
|
imem_din(sta_ibf_vce) := '0';
|
imem_din(sta_ibf_dse) := '0';
|
imem_din(sta_ibf_dse) := '0';
|
end if;
|
end if;
|
n.iaddr := slv(unsigned(r.iaddr) + 1);
|
n.iaddr := slv(unsigned(r.iaddr) + 1);
|
if unsigned(r.iaddr) = unsigned(imem_sta)+3 then -- stop after sta(3)
|
if unsigned(r.iaddr) = unsigned(imem_sta)+3 then -- stop after sta(3)
|
n.state := s_idle;
|
n.state := s_idle;
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
iei_req := r.ireq; -- ??? simplify, use r.ireq directly
|
iei_req := r.ireq; -- ??? simplify, use r.ireq directly
|
|
|
if EI_ACK = '1' or r.csie = '0' then -- interrupt executed or ie disabled
|
if EI_ACK = '1' or r.csie = '0' then -- interrupt executed or ie disabled
|
n.ireq := '0'; -- cancel request
|
n.ireq := '0'; -- cancel request
|
end if;
|
end if;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
MEM_0_WE <= imem_we0;
|
MEM_0_WE <= imem_we0;
|
MEM_1_WE <= imem_we1;
|
MEM_1_WE <= imem_we1;
|
MEM_ADDR <= imem_addr;
|
MEM_ADDR <= imem_addr;
|
MEM_DIN <= imem_din;
|
MEM_DIN <= imem_din;
|
|
|
IB_SRES.dout <= idout;
|
IB_SRES.dout <= idout;
|
IB_SRES.ack <= r.ibsel and ibreq;
|
IB_SRES.ack <= r.ibsel and ibreq;
|
IB_SRES.busy <= ibhold and ibreq;
|
IB_SRES.busy <= ibhold and ibreq;
|
|
|
RB_LAM <= ilam;
|
RB_LAM <= ilam;
|
EI_REQ <= iei_req;
|
EI_REQ <= iei_req;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
|
|
end syn;
|
end syn;
|
|
|