# $Id: viv_tools_model.tcl 646 2015-02-15 12:04:55Z mueller $
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# $Id: viv_tools_model.tcl 646 2015-02-15 12:04:55Z mueller $
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#
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#
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# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2015-02-14 646 1.0 Initial version
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# 2015-02-14 646 1.0 Initial version
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#
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#
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#
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#
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# --------------------------------------------------------------------
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# --------------------------------------------------------------------
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#
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#
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proc rvtb_default_model {stem mode} {
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proc rvtb_default_model {stem mode} {
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switch $mode {
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switch $mode {
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ssim {
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ssim {
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open_checkpoint "${stem}_syn.dcp"
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open_checkpoint "${stem}_syn.dcp"
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write_vhdl -mode funcsim -force "${stem}_ssim.vhd"
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write_vhdl -mode funcsim -force "${stem}_ssim.vhd"
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}
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}
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osim {
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osim {
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open_checkpoint "${stem}_opt.dcp"
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open_checkpoint "${stem}_opt.dcp"
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write_vhdl -mode funcsim -force "${stem}_osim.vhd"
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write_vhdl -mode funcsim -force "${stem}_osim.vhd"
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}
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}
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tsim {
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tsim {
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open_checkpoint "${stem}_rou.dcp"
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open_checkpoint "${stem}_rou.dcp"
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write_verilog -mode timesim -force -sdf_anno true "${stem}_tsim.v"
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write_verilog -mode timesim -force -sdf_anno true "${stem}_tsim.v"
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write_sdf -mode timesim -force "${stem}_tsim.sdf"
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write_sdf -mode timesim -force "${stem}_tsim.sdf"
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}
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}
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default {
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default {
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error "-E: bad mode: $mode";
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error "-E: bad mode: $mode";
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}
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}
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}
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}
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return "";
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return "";
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}
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}
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