-- $Id: tst_rlink_cuff.vhd 666 2015-04-12 21:17:54Z mueller $
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-- $Id: tst_rlink_cuff.vhd 666 2015-04-12 21:17:54Z mueller $
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--
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--
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-- Copyright 2012-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2012-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: tst_rlink_cuff - syn
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-- Module Name: tst_rlink_cuff - syn
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-- Description: tester for rlink over cuff
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-- Description: tester for rlink over cuff
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--
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--
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-- Dependencies: vlib/rlink/rlink_core8
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-- Dependencies: vlib/rlink/rlink_core8
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-- vlib/rlink/rlink_rlbmux
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-- vlib/rlink/rlink_rlbmux
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-- vlib/serport/serport_1clock
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-- vlib/serport/serport_1clock
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-- ../tst_rlink/rbd_tst_rlink
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-- ../tst_rlink/rbd_tst_rlink
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-- vlib/rbus/rb_sres_or_2
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-- vlib/rbus/rb_sres_or_2
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-- vlib/genlib/led_pulse_stretch
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-- vlib/genlib/led_pulse_stretch
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--
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--
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-- Test bench: -
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-- Test bench: -
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
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-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-04-11 666 1.2 rearrange XON handling
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-- 2015-04-11 666 1.2 rearrange XON handling
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-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
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-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
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-- 2013-01-02 467 1.0.1 use 64 usec led pulse width
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-- 2013-01-02 467 1.0.1 use 64 usec led pulse width
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-- 2012-12-29 466 1.0 Initial version
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-- 2012-12-29 466 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.genlib.all;
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use work.genlib.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.rlinklib.all;
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use work.serportlib.all;
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use work.serportlib.all;
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use work.fx2lib.all;
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use work.fx2lib.all;
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use work.sys_conf.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity tst_rlink_cuff is -- tester for rlink over cuff
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entity tst_rlink_cuff is -- tester for rlink over cuff
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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CE_USEC : in slbit; -- usec pulse
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CE_USEC : in slbit; -- usec pulse
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CE_MSEC : in slbit; -- msec pulse
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CE_MSEC : in slbit; -- msec pulse
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RB_MREQ_TOP : out rb_mreq_type; -- rbus: request
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RB_MREQ_TOP : out rb_mreq_type; -- rbus: request
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RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level
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RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level
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SWI : in slv8; -- hio: switches
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SWI : in slv8; -- hio: switches
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BTN : in slv4; -- hio: buttons
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BTN : in slv4; -- hio: buttons
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LED : out slv8; -- hio: leds
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LED : out slv8; -- hio: leds
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DSP_DAT : out slv16; -- hio: display data
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DSP_DAT : out slv16; -- hio: display data
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DSP_DP : out slv4; -- hio: display decimal points
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DSP_DP : out slv4; -- hio: display decimal points
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RXSD : in slbit; -- receive serial data (uart view)
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RXSD : in slbit; -- receive serial data (uart view)
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TXSD : out slbit; -- transmit serial data (uart view)
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TXSD : out slbit; -- transmit serial data (uart view)
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RTS_N : out slbit; -- receive rts (uart view, act.low)
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RTS_N : out slbit; -- receive rts (uart view, act.low)
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CTS_N : in slbit; -- transmit cts (uart view, act.low)
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CTS_N : in slbit; -- transmit cts (uart view, act.low)
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FX2_RXDATA : in slv8; -- fx2: receiver data out
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FX2_RXDATA : in slv8; -- fx2: receiver data out
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FX2_RXVAL : in slbit; -- fx2: receiver data valid
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FX2_RXVAL : in slbit; -- fx2: receiver data valid
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FX2_RXHOLD : out slbit; -- fx2: receiver data hold
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FX2_RXHOLD : out slbit; -- fx2: receiver data hold
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FX2_TXDATA : out slv8; -- fx2: transmit data in
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FX2_TXDATA : out slv8; -- fx2: transmit data in
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FX2_TXENA : out slbit; -- fx2: transmit data enable
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FX2_TXENA : out slbit; -- fx2: transmit data enable
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FX2_TXBUSY : in slbit; -- fx2: transmit busy
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FX2_TXBUSY : in slbit; -- fx2: transmit busy
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FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in
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FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in
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FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable
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FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable
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FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy
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FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy
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FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor
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FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor
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);
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);
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end tst_rlink_cuff;
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end tst_rlink_cuff;
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architecture syn of tst_rlink_cuff is
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architecture syn of tst_rlink_cuff is
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES_TST : rb_sres_type := rb_sres_init;
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signal RB_SRES_TST : rb_sres_type := rb_sres_init;
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_STAT : slv4 := (others=>'0');
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signal RB_STAT : slv4 := (others=>'0');
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal STAT : slv8 := (others=>'0');
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signal STAT : slv8 := (others=>'0');
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signal RLB_DI : slv8 := (others=>'0');
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signal RLB_DI : slv8 := (others=>'0');
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signal RLB_ENA : slbit := '0';
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signal RLB_ENA : slbit := '0';
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signal RLB_BUSY : slbit := '0';
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signal RLB_BUSY : slbit := '0';
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signal RLB_DO : slv8 := (others=>'0');
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signal RLB_DO : slv8 := (others=>'0');
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signal RLB_VAL : slbit := '0';
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signal RLB_VAL : slbit := '0';
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signal RLB_HOLD : slbit := '0';
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signal RLB_HOLD : slbit := '0';
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signal SER_RXDATA : slv8 := (others=>'0');
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signal SER_RXDATA : slv8 := (others=>'0');
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signal SER_RXVAL : slbit := '0';
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signal SER_RXVAL : slbit := '0';
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signal SER_RXHOLD : slbit := '0';
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signal SER_RXHOLD : slbit := '0';
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signal SER_TXDATA : slv8 := (others=>'0');
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signal SER_TXDATA : slv8 := (others=>'0');
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signal SER_TXENA : slbit := '0';
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signal SER_TXENA : slbit := '0';
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signal SER_TXBUSY : slbit := '0';
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signal SER_TXBUSY : slbit := '0';
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signal FX2_TX2ENA_L : slbit := '0';
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signal FX2_TX2ENA_L : slbit := '0';
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signal FX2_TXENA_L : slbit := '0';
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signal FX2_TXENA_L : slbit := '0';
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signal FX2_TX2ENA_LED : slbit := '0';
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signal FX2_TX2ENA_LED : slbit := '0';
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signal FX2_TXENA_LED : slbit := '0';
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signal FX2_TXENA_LED : slbit := '0';
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signal FX2_RXVAL_LED : slbit := '0';
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signal FX2_RXVAL_LED : slbit := '0';
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signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
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signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
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signal R_LEDCE : slbit := '0'; -- ce every 64 usec
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signal R_LEDCE : slbit := '0'; -- ce every 64 usec
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begin
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begin
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RLCORE : rlink_core8
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RLCORE : rlink_core8
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generic map (
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generic map (
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BTOWIDTH => 6,
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BTOWIDTH => 6,
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RTAWIDTH => 12,
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RTAWIDTH => 12,
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SYSID => (others=>'0'),
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SYSID => (others=>'0'),
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ENAPIN_RLMON => sbcntl_sbf_rlmon,
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ENAPIN_RLMON => sbcntl_sbf_rlmon,
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ENAPIN_RBMON => sbcntl_sbf_rbmon)
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ENAPIN_RBMON => sbcntl_sbf_rbmon)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_INT => CE_MSEC,
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CE_INT => CE_MSEC,
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RESET => RESET,
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RESET => RESET,
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ESCXON => SWI(1),
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ESCXON => SWI(1),
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ESCFILL => '0',
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ESCFILL => '0',
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RLB_DI => RLB_DI,
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RLB_DI => RLB_DI,
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RLB_ENA => RLB_ENA,
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RLB_ENA => RLB_ENA,
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RLB_BUSY => RLB_BUSY,
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RLB_BUSY => RLB_BUSY,
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RLB_DO => RLB_DO,
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RLB_DO => RLB_DO,
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RLB_VAL => RLB_VAL,
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RLB_VAL => RLB_VAL,
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RLB_HOLD => RLB_HOLD,
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RLB_HOLD => RLB_HOLD,
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RL_MONI => open,
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RL_MONI => open,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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RB_STAT => RB_STAT
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);
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);
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RLBMUX : rlink_rlbmux
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RLBMUX : rlink_rlbmux
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port map (
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port map (
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SEL => SWI(2),
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SEL => SWI(2),
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RLB_DI => RLB_DI,
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RLB_DI => RLB_DI,
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RLB_ENA => RLB_ENA,
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RLB_ENA => RLB_ENA,
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RLB_BUSY => RLB_BUSY,
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RLB_BUSY => RLB_BUSY,
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RLB_DO => RLB_DO,
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RLB_DO => RLB_DO,
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RLB_VAL => RLB_VAL,
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RLB_VAL => RLB_VAL,
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RLB_HOLD => RLB_HOLD,
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RLB_HOLD => RLB_HOLD,
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P0_RXDATA => SER_RXDATA,
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P0_RXDATA => SER_RXDATA,
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P0_RXVAL => SER_RXVAL,
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P0_RXVAL => SER_RXVAL,
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P0_RXHOLD => SER_RXHOLD,
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P0_RXHOLD => SER_RXHOLD,
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P0_TXDATA => SER_TXDATA,
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P0_TXDATA => SER_TXDATA,
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P0_TXENA => SER_TXENA,
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P0_TXENA => SER_TXENA,
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P0_TXBUSY => SER_TXBUSY,
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P0_TXBUSY => SER_TXBUSY,
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P1_RXDATA => FX2_RXDATA,
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P1_RXDATA => FX2_RXDATA,
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P1_RXVAL => FX2_RXVAL,
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P1_RXVAL => FX2_RXVAL,
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P1_RXHOLD => FX2_RXHOLD,
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P1_RXHOLD => FX2_RXHOLD,
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P1_TXDATA => FX2_TXDATA,
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P1_TXDATA => FX2_TXDATA,
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P1_TXENA => FX2_TXENA_L,
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P1_TXENA => FX2_TXENA_L,
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P1_TXBUSY => FX2_TXBUSY
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P1_TXBUSY => FX2_TXBUSY
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);
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);
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SERPORT : serport_1clock
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SERPORT : serport_1clock
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generic map (
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generic map (
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CDWIDTH => 15,
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CDWIDTH => 15,
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CDINIT => sys_conf_ser2rri_cdinit,
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CDINIT => sys_conf_ser2rri_cdinit,
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RXFAWIDTH => 5,
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RXFAWIDTH => 5,
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TXFAWIDTH => 5)
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TXFAWIDTH => 5)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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RESET => RESET,
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RESET => RESET,
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ENAXON => SWI(1),
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ENAXON => SWI(1),
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ENAESC => '0', -- escaping now in rlink_core8
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ENAESC => '0', -- escaping now in rlink_core8
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RXDATA => SER_RXDATA,
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RXDATA => SER_RXDATA,
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RXVAL => SER_RXVAL,
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RXVAL => SER_RXVAL,
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RXHOLD => SER_RXHOLD,
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RXHOLD => SER_RXHOLD,
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TXDATA => SER_TXDATA,
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TXDATA => SER_TXDATA,
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TXENA => SER_TXENA,
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TXENA => SER_TXENA,
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TXBUSY => SER_TXBUSY,
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TXBUSY => SER_TXBUSY,
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MONI => SER_MONI,
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MONI => SER_MONI,
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RXSD => RXSD,
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RXSD => RXSD,
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TXSD => TXSD,
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TXSD => TXSD,
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RXRTS_N => RTS_N,
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RXRTS_N => RTS_N,
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TXCTS_N => CTS_N
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TXCTS_N => CTS_N
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);
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);
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RBDTST : entity work.rbd_tst_rlink
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RBDTST : entity work.rbd_tst_rlink
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_TST,
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RB_SRES => RB_SRES_TST,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT,
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RB_STAT => RB_STAT,
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RB_SRES_TOP => RB_SRES,
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RB_SRES_TOP => RB_SRES,
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RXSD => RXSD,
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RXSD => RXSD,
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RXACT => SER_MONI.rxact,
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RXACT => SER_MONI.rxact,
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STAT => STAT
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STAT => STAT
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);
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);
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RB_SRES_OR1 : rb_sres_or_2
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RB_SRES_OR1 : rb_sres_or_2
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port map (
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port map (
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RB_SRES_1 => RB_SRES_TOP,
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RB_SRES_1 => RB_SRES_TOP,
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RB_SRES_2 => RB_SRES_TST,
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RB_SRES_2 => RB_SRES_TST,
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RB_SRES_OR => RB_SRES
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RB_SRES_OR => RB_SRES
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);
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);
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TX2ENA_PSTR : led_pulse_stretch
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TX2ENA_PSTR : led_pulse_stretch
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_INT => R_LEDCE,
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CE_INT => R_LEDCE,
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RESET => '0',
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RESET => '0',
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DIN => FX2_TX2ENA_L,
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DIN => FX2_TX2ENA_L,
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POUT => FX2_TX2ENA_LED
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POUT => FX2_TX2ENA_LED
|
);
|
);
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TXENA_PSTR : led_pulse_stretch
|
TXENA_PSTR : led_pulse_stretch
|
port map (
|
port map (
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CLK => CLK,
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CLK => CLK,
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CE_INT => R_LEDCE,
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CE_INT => R_LEDCE,
|
RESET => '0',
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RESET => '0',
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DIN => FX2_TXENA_L,
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DIN => FX2_TXENA_L,
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POUT => FX2_TXENA_LED
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POUT => FX2_TXENA_LED
|
);
|
);
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RXVAL_PSTR : led_pulse_stretch
|
RXVAL_PSTR : led_pulse_stretch
|
port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_INT => R_LEDCE,
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CE_INT => R_LEDCE,
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RESET => '0',
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RESET => '0',
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DIN => FX2_RXVAL,
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DIN => FX2_RXVAL,
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POUT => FX2_RXVAL_LED
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POUT => FX2_RXVAL_LED
|
);
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);
|
|
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proc_clkdiv: process (CLK)
|
proc_clkdiv: process (CLK)
|
begin
|
begin
|
|
|
if rising_edge(CLK) then
|
if rising_edge(CLK) then
|
R_LEDCE <= '0';
|
R_LEDCE <= '0';
|
if CE_USEC = '1' then
|
if CE_USEC = '1' then
|
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
|
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
|
if unsigned(R_LEDDIV) = 0 then
|
if unsigned(R_LEDDIV) = 0 then
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R_LEDCE <= '1';
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R_LEDCE <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end process proc_clkdiv;
|
end process proc_clkdiv;
|
|
|
proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY,
|
proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY,
|
FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED)
|
FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED)
|
begin
|
begin
|
|
|
DSP_DAT <= SER_MONI.abclkdiv;
|
DSP_DAT <= SER_MONI.abclkdiv;
|
|
|
LED(7) <= SER_MONI.abact;
|
LED(7) <= SER_MONI.abact;
|
LED(6 downto 2) <= (others=>'0');
|
LED(6 downto 2) <= (others=>'0');
|
LED(1) <= STAT(1);
|
LED(1) <= STAT(1);
|
LED(0) <= STAT(0);
|
LED(0) <= STAT(0);
|
|
|
if SWI(2) = '0' then
|
if SWI(2) = '0' then
|
DSP_DP(3) <= not SER_MONI.txok;
|
DSP_DP(3) <= not SER_MONI.txok;
|
DSP_DP(2) <= SER_MONI.txact;
|
DSP_DP(2) <= SER_MONI.txact;
|
DSP_DP(1) <= not SER_MONI.rxok;
|
DSP_DP(1) <= not SER_MONI.rxok;
|
DSP_DP(0) <= SER_MONI.rxact;
|
DSP_DP(0) <= SER_MONI.rxact;
|
else
|
else
|
DSP_DP(3) <= FX2_TX2BUSY;
|
DSP_DP(3) <= FX2_TX2BUSY;
|
DSP_DP(2) <= FX2_TX2ENA_LED;
|
DSP_DP(2) <= FX2_TX2ENA_LED;
|
DSP_DP(1) <= FX2_TXENA_LED;
|
DSP_DP(1) <= FX2_TXENA_LED;
|
DSP_DP(0) <= FX2_RXVAL_LED;
|
DSP_DP(0) <= FX2_RXVAL_LED;
|
end if;
|
end if;
|
|
|
end process proc_hiomux;
|
end process proc_hiomux;
|
|
|
RB_MREQ_TOP <= RB_MREQ;
|
RB_MREQ_TOP <= RB_MREQ;
|
FX2_TX2ENA <= FX2_TX2ENA_L;
|
FX2_TX2ENA <= FX2_TX2ENA_L;
|
FX2_TXENA <= FX2_TXENA_L;
|
FX2_TXENA <= FX2_TXENA_L;
|
|
|
end syn;
|
end syn;
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