-- $Id: rbd_tester.vhd 593 2014-09-14 22:21:33Z mueller $
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-- $Id: rbd_tester.vhd 593 2014-09-14 22:21:33Z mueller $
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--
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--
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-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rbd_tester - syn
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-- Module Name: rbd_tester - syn
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-- Description: rbus dev: rbus tester
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-- Description: rbus dev: rbus tester
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--
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--
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-- Dependencies: memlib/fifo_1c_dram_raw
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-- Dependencies: memlib/fifo_1c_dram_raw
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--
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--
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-- Test bench: rlink/tb/tb_rlink (used as test target)
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-- Test bench: rlink/tb/tb_rlink (used as test target)
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
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-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2014-08-31 590 14.7 131013 xc6slx16-2 74 162 16 73 s 5.8 ver 4.1
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-- 2014-08-31 590 14.7 131013 xc6slx16-2 74 162 16 73 s 5.8 ver 4.1
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-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
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-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
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-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
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-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2014-09-05 591 4.1 use new iface with 8 regs
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-- 2014-09-05 591 4.1 use new iface with 8 regs
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-- 2014-08-30 589 4.0 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-30 589 4.0 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
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-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
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-- 2011-11-19 427 1.0.4 now numeric_std clean
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-- 2011-11-19 427 1.0.4 now numeric_std clean
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-- 2010-12-31 352 1.0.3 simplify irb_ack logic
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-- 2010-12-31 352 1.0.3 simplify irb_ack logic
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-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
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-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
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-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
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-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
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-- 2010-12-04 343 1.0 Initial version
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-- 2010-12-04 343 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- rbus registers:
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-- rbus registers:
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--
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--
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-- Addr Bits Name r/w/f Function
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-- Addr Bits Name r/w/f Function
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-- 000 cntl r/w/- Control register
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-- 000 cntl r/w/- Control register
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-- 15 wchk r/w/- write check seen (cleared on data write)
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-- 15 wchk r/w/- write check seen (cleared on data write)
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-- 09:00 nbusy r/w/- busy cycles (for data,dinc,fifo,lnak)
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-- 09:00 nbusy r/w/- busy cycles (for data,dinc,fifo,lnak)
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-- 001 03:00 stat r/w/- status send to RB_STAT
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-- 001 03:00 stat r/w/- status send to RB_STAT
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-- 010 attn -/w/f Attn register: ping RB_LAM lines
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-- 010 attn -/w/f Attn register: ping RB_LAM lines
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-- 011 09:00 ncyc r/-/- return cycle length of last access
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-- 011 09:00 ncyc r/-/- return cycle length of last access
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-- 100 data r/w/- Data register (plain read/write)
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-- 100 data r/w/- Data register (plain read/write)
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-- 101 dinc r/w/- Data register (autoinc and write check)
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-- 101 dinc r/w/- Data register (autoinc and write check)
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-- 110 fifo r/w/- Fifo interface register
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-- 110 fifo r/w/- Fifo interface register
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-- 111 lnak r/w/- delayed ack deassert
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-- 111 lnak r/w/- delayed ack deassert
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.rblib.all;
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use work.rblib.all;
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entity rbd_tester is -- rbus dev: rbus tester
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entity rbd_tester is -- rbus dev: rbus tester
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-- complete rrirp_aif interface
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-- complete rrirp_aif interface
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generic (
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generic (
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RB_ADDR : slv16 := slv(to_unsigned(16#ffe0#,16)));
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RB_ADDR : slv16 := slv(to_unsigned(16#ffe0#,16)));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_LAM : out slv16; -- rbus: look at me
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RB_LAM : out slv16; -- rbus: look at me
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RB_STAT : out slv4 -- rbus: status flags
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RB_STAT : out slv4 -- rbus: status flags
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);
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);
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end entity rbd_tester;
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end entity rbd_tester;
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architecture syn of rbd_tester is
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architecture syn of rbd_tester is
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constant awidth : positive := 4; -- fifo address width
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constant awidth : positive := 4; -- fifo address width
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constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
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constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
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constant rbaddr_stat : slv3 := "001"; -- stat address offset
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constant rbaddr_stat : slv3 := "001"; -- stat address offset
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constant rbaddr_attn : slv3 := "010"; -- attn address offset
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constant rbaddr_attn : slv3 := "010"; -- attn address offset
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constant rbaddr_ncyc : slv3 := "011"; -- ncyc address offset
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constant rbaddr_ncyc : slv3 := "011"; -- ncyc address offset
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constant rbaddr_data : slv3 := "100"; -- data address offset
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constant rbaddr_data : slv3 := "100"; -- data address offset
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constant rbaddr_dinc : slv3 := "101"; -- dinc address offset
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constant rbaddr_dinc : slv3 := "101"; -- dinc address offset
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constant rbaddr_fifo : slv3 := "110"; -- fifo address offset
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constant rbaddr_fifo : slv3 := "110"; -- fifo address offset
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constant rbaddr_lnak : slv3 := "111"; -- lnak address offset
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constant rbaddr_lnak : slv3 := "111"; -- lnak address offset
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constant cntl_rbf_wchk : integer := 15;
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constant cntl_rbf_wchk : integer := 15;
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subtype cntl_rbf_nbusy is integer range 9 downto 0;
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subtype cntl_rbf_nbusy is integer range 9 downto 0;
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constant init_rbf_cntl : integer := 0;
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constant init_rbf_cntl : integer := 0;
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constant init_rbf_data : integer := 1;
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constant init_rbf_data : integer := 1;
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constant init_rbf_fifo : integer := 2;
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constant init_rbf_fifo : integer := 2;
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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rbsel : slbit; -- rbus select
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rbsel : slbit; -- rbus select
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wchk : slbit; -- write check flag
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wchk : slbit; -- write check flag
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stat : slv4; -- stat setting
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stat : slv4; -- stat setting
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nbusy : slv10; -- nbusy setting
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nbusy : slv10; -- nbusy setting
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data : slv16; -- data register
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data : slv16; -- data register
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act_1 : slbit; -- rbsel and (re or we) in last cycle
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act_1 : slbit; -- rbsel and (re or we) in last cycle
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ncyc : slv10; -- cycle length of last access
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ncyc : slv10; -- cycle length of last access
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cntbusy : slv10; -- busy timer
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cntbusy : slv10; -- busy timer
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cntcyc : slv10; -- cycle length counter
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cntcyc : slv10; -- cycle length counter
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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'0','0', -- rbsel, wchk
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'0','0', -- rbsel, wchk
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(others=>'0'), -- stat
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(others=>'0'), -- stat
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(others=>'0'), -- nbusy
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(others=>'0'), -- nbusy
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(others=>'0'), -- data
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(others=>'0'), -- data
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'0', -- act_1
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'0', -- act_1
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(others=>'0'), -- ncyc
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(others=>'0'), -- ncyc
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(others=>'0'), -- cntbusy
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(others=>'0'), -- cntbusy
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(others=>'0') -- cntcyc
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(others=>'0') -- cntcyc
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);
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);
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constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
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constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
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signal R_REGS : regs_type := regs_init;
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal FIFO_RESET : slbit := '0';
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signal FIFO_RESET : slbit := '0';
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signal FIFO_RE : slbit := '0';
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signal FIFO_RE : slbit := '0';
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signal FIFO_WE : slbit := '0';
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signal FIFO_WE : slbit := '0';
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signal FIFO_EMPTY : slbit := '0';
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signal FIFO_EMPTY : slbit := '0';
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signal FIFO_FULL : slbit := '0';
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signal FIFO_FULL : slbit := '0';
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signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
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signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
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signal FIFO_DO : slv16 := (others=>'0');
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signal FIFO_DO : slv16 := (others=>'0');
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begin
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begin
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FIFO : fifo_1c_dram_raw
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FIFO : fifo_1c_dram_raw
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generic map (
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generic map (
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AWIDTH => awidth,
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AWIDTH => awidth,
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DWIDTH => 16)
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DWIDTH => 16)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => FIFO_RESET,
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RESET => FIFO_RESET,
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RE => FIFO_RE,
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RE => FIFO_RE,
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WE => FIFO_WE,
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WE => FIFO_WE,
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DI => RB_MREQ.din,
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DI => RB_MREQ.din,
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DO => FIFO_DO,
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DO => FIFO_DO,
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SIZE => FIFO_SIZE,
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SIZE => FIFO_SIZE,
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EMPTY => FIFO_EMPTY,
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EMPTY => FIFO_EMPTY,
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FULL => FIFO_FULL
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FULL => FIFO_FULL
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
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proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable irb_ack : slbit := '0';
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variable irb_ack : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_dout : slv16 := (others=>'0');
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variable irb_dout : slv16 := (others=>'0');
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variable irbena : slbit := '0';
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variable irbena : slbit := '0';
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variable irblam : slv16 := (others=>'0');
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variable irblam : slv16 := (others=>'0');
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variable ififo_re : slbit := '0';
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variable ififo_re : slbit := '0';
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variable ififo_we : slbit := '0';
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variable ififo_we : slbit := '0';
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variable ififo_reset : slbit := '0';
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variable ififo_reset : slbit := '0';
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variable isbusy : slbit := '0';
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variable isbusy : slbit := '0';
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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irb_ack := '0';
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irb_ack := '0';
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irb_busy := '0';
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irb_busy := '0';
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irb_err := '0';
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irb_err := '0';
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irb_dout := (others=>'0');
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irb_dout := (others=>'0');
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irblam := (others=>'0');
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irblam := (others=>'0');
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irbena := RB_MREQ.re or RB_MREQ.we;
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irbena := RB_MREQ.re or RB_MREQ.we;
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ififo_re := '0';
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ififo_re := '0';
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ififo_we := '0';
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ififo_we := '0';
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ififo_reset := '0';
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ififo_reset := '0';
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isbusy := '0';
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isbusy := '0';
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if unsigned(r.cntbusy) /= 0 then
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if unsigned(r.cntbusy) /= 0 then
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isbusy := '1';
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isbusy := '1';
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end if;
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end if;
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-- rbus address decoder
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-- rbus address decoder
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n.rbsel := '0';
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n.rbsel := '0';
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if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
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if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
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n.rbsel := '1';
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n.rbsel := '1';
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if irbena = '0' then -- addr valid and selected, but no req
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if irbena = '0' then -- addr valid and selected, but no req
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n.cntbusy := r.nbusy; -- preset busy timer
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n.cntbusy := r.nbusy; -- preset busy timer
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n.cntcyc := (others=>'0'); -- clear cycle length counter
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n.cntcyc := (others=>'0'); -- clear cycle length counter
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end if;
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end if;
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end if;
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end if;
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-- rbus transactions
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-- rbus transactions
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if r.rbsel = '1' then
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if r.rbsel = '1' then
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if irbena = '1' then -- if request active
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if irbena = '1' then -- if request active
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if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
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if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
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n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
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n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
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end if;
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end if;
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if r.cntcyc /= cntcyc_max then -- if cycle counter < max
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if r.cntcyc /= cntcyc_max then -- if cycle counter < max
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n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
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n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
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end if;
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end if;
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end if;
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end if;
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irb_ack := irbena; -- ack all (some rejects later)
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irb_ack := irbena; -- ack all (some rejects later)
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case RB_MREQ.addr(2 downto 0) is
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case RB_MREQ.addr(2 downto 0) is
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when rbaddr_cntl =>
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when rbaddr_cntl =>
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if RB_MREQ.we='1' then
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if RB_MREQ.we='1' then
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n.wchk := RB_MREQ.din(cntl_rbf_wchk);
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n.wchk := RB_MREQ.din(cntl_rbf_wchk);
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n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
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n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
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end if;
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end if;
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when rbaddr_stat =>
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when rbaddr_stat =>
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if RB_MREQ.we='1' then
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if RB_MREQ.we='1' then
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n.stat := RB_MREQ.din(r.stat'range);
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n.stat := RB_MREQ.din(r.stat'range);
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end if;
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end if;
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when rbaddr_attn =>
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when rbaddr_attn =>
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if RB_MREQ.we = '1' then -- on we
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if RB_MREQ.we = '1' then -- on we
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irblam := RB_MREQ.din; -- ping lam lines
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irblam := RB_MREQ.din; -- ping lam lines
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elsif RB_MREQ.re = '1' then -- on re
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elsif RB_MREQ.re = '1' then -- on re
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irb_err := '1'; -- reject
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irb_err := '1'; -- reject
|
end if;
|
end if;
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|
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when rbaddr_ncyc =>
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when rbaddr_ncyc =>
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if RB_MREQ.we = '1' then -- on we
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if RB_MREQ.we = '1' then -- on we
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irb_err := '1'; -- reject
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irb_err := '1'; -- reject
|
end if;
|
end if;
|
|
|
when rbaddr_data =>
|
when rbaddr_data =>
|
irb_busy := irbena and isbusy;
|
irb_busy := irbena and isbusy;
|
if RB_MREQ.we='1' and isbusy='0' then
|
if RB_MREQ.we='1' and isbusy='0' then
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n.wchk := '0';
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n.wchk := '0';
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n.data := RB_MREQ.din;
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n.data := RB_MREQ.din;
|
end if;
|
end if;
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|
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when rbaddr_dinc =>
|
when rbaddr_dinc =>
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irb_busy := irbena and isbusy;
|
irb_busy := irbena and isbusy;
|
if RB_MREQ.we = '1' then
|
if RB_MREQ.we = '1' then
|
if r.data /= RB_MREQ.din then
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if r.data /= RB_MREQ.din then
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n.wchk := '1';
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n.wchk := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
if (RB_MREQ.re='1' or RB_MREQ.we='1') and isbusy='0' then
|
if (RB_MREQ.re='1' or RB_MREQ.we='1') and isbusy='0' then
|
n.data := slv(unsigned(r.data) + 1);
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n.data := slv(unsigned(r.data) + 1);
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end if;
|
end if;
|
|
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when rbaddr_fifo =>
|
when rbaddr_fifo =>
|
irb_busy := irbena and isbusy;
|
irb_busy := irbena and isbusy;
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if RB_MREQ.re='1' and isbusy='0' then
|
if RB_MREQ.re='1' and isbusy='0' then
|
if FIFO_EMPTY = '1' then
|
if FIFO_EMPTY = '1' then
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irb_err := '1';
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irb_err := '1';
|
else
|
else
|
ififo_re := '1';
|
ififo_re := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
if RB_MREQ.we='1' and isbusy='0' then
|
if RB_MREQ.we='1' and isbusy='0' then
|
if FIFO_FULL = '1' then
|
if FIFO_FULL = '1' then
|
irb_err := '1';
|
irb_err := '1';
|
else
|
else
|
ififo_we := '1';
|
ififo_we := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when rbaddr_lnak =>
|
when rbaddr_lnak =>
|
irb_ack := '0'; -- nak it
|
irb_ack := '0'; -- nak it
|
if isbusy = '1' then -- or do a delayed nak
|
if isbusy = '1' then -- or do a delayed nak
|
irb_ack := irbena;
|
irb_ack := irbena;
|
irb_busy := irbena;
|
irb_busy := irbena;
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- rbus output driver
|
-- rbus output driver
|
-- send a '0101...' pattern when selected and busy or err
|
-- send a '0101...' pattern when selected and busy or err
|
-- send data only when busy=0 and err=0
|
-- send data only when busy=0 and err=0
|
-- this extra logic allows to debug rlink state machine
|
-- this extra logic allows to debug rlink state machine
|
if r.rbsel = '1' then
|
if r.rbsel = '1' then
|
irb_dout := "0101010101010101"; -- drive this pattern when selected
|
irb_dout := "0101010101010101"; -- drive this pattern when selected
|
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
|
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
|
case RB_MREQ.addr(2 downto 0) is
|
case RB_MREQ.addr(2 downto 0) is
|
when rbaddr_cntl =>
|
when rbaddr_cntl =>
|
irb_dout := (others=>'0');
|
irb_dout := (others=>'0');
|
irb_dout(cntl_rbf_wchk) := r.wchk;
|
irb_dout(cntl_rbf_wchk) := r.wchk;
|
irb_dout(cntl_rbf_nbusy) := r.nbusy;
|
irb_dout(cntl_rbf_nbusy) := r.nbusy;
|
when rbaddr_stat =>
|
when rbaddr_stat =>
|
irb_dout := (others=>'0');
|
irb_dout := (others=>'0');
|
irb_dout(r.stat'range) := r.stat;
|
irb_dout(r.stat'range) := r.stat;
|
when rbaddr_attn => null;
|
when rbaddr_attn => null;
|
when rbaddr_ncyc =>
|
when rbaddr_ncyc =>
|
irb_dout := (others=>'0');
|
irb_dout := (others=>'0');
|
irb_dout(r.cntcyc'range) := r.ncyc;
|
irb_dout(r.cntcyc'range) := r.ncyc;
|
when rbaddr_data | rbaddr_dinc =>
|
when rbaddr_data | rbaddr_dinc =>
|
irb_dout := r.data;
|
irb_dout := r.data;
|
when rbaddr_fifo =>
|
when rbaddr_fifo =>
|
if FIFO_EMPTY = '0' then
|
if FIFO_EMPTY = '0' then
|
irb_dout := FIFO_DO;
|
irb_dout := FIFO_DO;
|
end if;
|
end if;
|
when rbaddr_lnak => null;
|
when rbaddr_lnak => null;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- init transactions
|
-- init transactions
|
if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR then
|
if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR then
|
if RB_MREQ.din(init_rbf_cntl) = '1' then
|
if RB_MREQ.din(init_rbf_cntl) = '1' then
|
n.wchk := '0';
|
n.wchk := '0';
|
n.stat := (others=>'0');
|
n.stat := (others=>'0');
|
n.nbusy := (others=>'0');
|
n.nbusy := (others=>'0');
|
end if;
|
end if;
|
if RB_MREQ.din(init_rbf_data) = '1' then
|
if RB_MREQ.din(init_rbf_data) = '1' then
|
n.data := (others=>'0');
|
n.data := (others=>'0');
|
end if;
|
end if;
|
if RB_MREQ.din(init_rbf_fifo) = '1' then
|
if RB_MREQ.din(init_rbf_fifo) = '1' then
|
ififo_reset := '1';
|
ififo_reset := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- other transactions
|
-- other transactions
|
if irbena='0' and r.act_1='1' then
|
if irbena='0' and r.act_1='1' then
|
n.ncyc := r.cntcyc;
|
n.ncyc := r.cntcyc;
|
end if;
|
end if;
|
n.act_1 := irbena;
|
n.act_1 := irbena;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
FIFO_RE <= ififo_re;
|
FIFO_RE <= ififo_re;
|
FIFO_WE <= ififo_we;
|
FIFO_WE <= ififo_we;
|
FIFO_RESET <= ififo_reset;
|
FIFO_RESET <= ififo_reset;
|
|
|
RB_SRES.dout <= irb_dout;
|
RB_SRES.dout <= irb_dout;
|
RB_SRES.ack <= irb_ack;
|
RB_SRES.ack <= irb_ack;
|
RB_SRES.err <= irb_err;
|
RB_SRES.err <= irb_err;
|
RB_SRES.busy <= irb_busy;
|
RB_SRES.busy <= irb_busy;
|
|
|
RB_LAM <= irblam;
|
RB_LAM <= irblam;
|
RB_STAT <= r.stat;
|
RB_STAT <= r.stat;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
end syn;
|
end syn;
|
|
|