# $Id: test_rhrp_int.tcl 692 2015-06-21 11:53:24Z mueller $
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# $Id: test_rhrp_int.tcl 692 2015-06-21 11:53:24Z mueller $
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#
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#
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# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2015-06-20 692 1.1.1 de-configure all drives at begin
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# 2015-06-20 692 1.1.1 de-configure all drives at begin
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# 2015-05-04 674 1.1 w11a start/stop/suspend overhaul
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# 2015-05-04 674 1.1 w11a start/stop/suspend overhaul
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# 2015-03-29 667 1.0 Initial version
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# 2015-03-29 667 1.0 Initial version
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#
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#
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# Test interrupt response
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# Test interrupt response
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# A:
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# A:
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# ----------------------------------------------------------------------------
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# ----------------------------------------------------------------------------
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rlc log "test_rhrp_int: test interrupt response ------------------------------"
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rlc log "test_rhrp_int: test interrupt response ------------------------------"
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rlc log " setup: unit 0:RP06(mol), 1:RM05(mol,wrl), 2: RP07(mol=0), 3: off"
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rlc log " setup: unit 0:RP06(mol), 1:RM05(mol,wrl), 2: RP07(mol=0), 3: off"
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package require ibd_rhrp
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package require ibd_rhrp
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ibd_rhrp::setup
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ibd_rhrp::setup
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rlc set statmask $rw11::STAT_DEFMASK
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rlc set statmask $rw11::STAT_DEFMASK
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rlc set statvalue 0
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rlc set statvalue 0
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# de-configure all drives (and clear errros and reset vv)
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# de-configure all drives (and clear errros and reset vv)
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$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \
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$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv]
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-wibr rpa.ds [regbld ibd_rhrp::DS erp vv]
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# configure drives
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# configure drives
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$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \
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$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol] \
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol] \
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-wibr rpa.dt $ibd_rhrp::DTE_RP06 \
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-wibr rpa.dt $ibd_rhrp::DTE_RP06 \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol wrl] \
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol wrl] \
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-wibr rpa.dt $ibd_rhrp::DTE_RM05 \
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-wibr rpa.dt $ibd_rhrp::DTE_RM05 \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \
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-wibr rpa.dt $ibd_rhrp::DTE_RP07 \
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-wibr rpa.dt $ibd_rhrp::DTE_RP07 \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \
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-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}]
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-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}]
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# clear errors: cs1.tre=1 via unit 0
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# clear errors: cs1.tre=1 via unit 0
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$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \
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$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \
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-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \
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-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \
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-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \
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-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \
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-wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \
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-wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \
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-rma rpa.ds -edata [regbld ibd_rhrp::DS dpr mol dry]
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-rma rpa.ds -edata [regbld ibd_rhrp::DS dpr mol dry]
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# load test code
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# load test code
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$cpu ldasm -lst lst -sym sym {
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$cpu ldasm -lst lst -sym sym {
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.include |lib/defs_cpu.mac|
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.include |lib/defs_cpu.mac|
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.include |lib/defs_rp.mac|
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.include |lib/defs_rp.mac|
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;
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;
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.include |lib/vec_cpucatch.mac|
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.include |lib/vec_cpucatch.mac|
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;
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;
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. = 000254 ; setup RHRP interrupt vector
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. = 000254 ; setup RHRP interrupt vector
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v..rp: .word vh.rp
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v..rp: .word vh.rp
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.word cp.pr7
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.word cp.pr7
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;
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;
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. = 1000 ; data area
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. = 1000 ; data area
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stack:
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stack:
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ibuf: .blkw 4. ; input buffer
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ibuf: .blkw 4. ; input buffer
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rint: .word 0 ; reinterrupt
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rint: .word 0 ; reinterrupt
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;
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;
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icnt: .word 0 ; interrupt count
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icnt: .word 0 ; interrupt count
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pcnt: .word 0 ; poll count
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pcnt: .word 0 ; poll count
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obuf: .blkw 6. ; output buffer
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obuf: .blkw 6. ; output buffer
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fbuf: .blkw 5. ; final buffer
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fbuf: .blkw 5. ; final buffer
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;
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;
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. = 2000 ; code area
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. = 2000 ; code area
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start: spl 7 ; lock out interrupts
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start: spl 7 ; lock out interrupts
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clr icnt ; clear counters
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clr icnt ; clear counters
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clr pcnt
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clr pcnt
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;
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;
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mov #obuf,r0 ; clear obuf
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mov #obuf,r0 ; clear obuf
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr r5 ; r5 used to time int delay
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clr r5 ; r5 used to time int delay
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;
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;
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mov #ibuf,r0 ; setup regs from ibuf
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mov #ibuf,r0 ; setup regs from ibuf
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mov (r0)+,@#rp.cs2 ; cs2
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mov (r0)+,@#rp.cs2 ; cs2
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mov (r0)+,@#rp.da ; da
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mov (r0)+,@#rp.da ; da
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mov (r0)+,@#rp.dc ; dc
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mov (r0)+,@#rp.dc ; dc
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mov (r0)+,@#rp.cs1 ; cs1
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mov (r0)+,@#rp.cs1 ; cs1
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spl 0 ; allow interrupts
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spl 0 ; allow interrupts
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;
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;
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inc r5 ; time int delay, up to 10 instructions
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inc r5 ; time int delay, up to 10 instructions
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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inc r5
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;
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;
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poll: inc pcnt ; count polls
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poll: inc pcnt ; count polls
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tstb @#rp.cs1 ; check cs1 rdy
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tstb @#rp.cs1 ; check cs1 rdy
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bpl poll ; if rdy=0 keep polling
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bpl poll ; if rdy=0 keep polling
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tst icnt ; did we have an interrupt ?
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tst icnt ; did we have an interrupt ?
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bne 1$ ;
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bne 1$ ;
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;
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;
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mov #obuf,r0 ; store regs in obuf
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mov #obuf,r0 ; store regs in obuf
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mov @#rp.cs1,(r0)+ ; cs1
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mov @#rp.cs1,(r0)+ ; cs1
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mov @#rp.cs2,(r0)+ ; cs2
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mov @#rp.cs2,(r0)+ ; cs2
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mov @#rp.er1,(r0)+ ; er1
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mov @#rp.er1,(r0)+ ; er1
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mov @#rp.ds,(r0)+ ; ds
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mov @#rp.ds,(r0)+ ; ds
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mov @#rp.as,(r0)+ ; as
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mov @#rp.as,(r0)+ ; as
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;
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;
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1$: tst rint ; re-interrupt wanted ?
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1$: tst rint ; re-interrupt wanted ?
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bne 2$ ;
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bne 2$ ;
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mov #377,@#rp.as ; if not, cancel all attentions
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mov #377,@#rp.as ; if not, cancel all attentions
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clr rint
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clr rint
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;
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;
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2$: bit #rp.erp,@#rp.ds ; ds.erp = 1 ? any controller errors ?
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2$: bit #rp.erp,@#rp.ds ; ds.erp = 1 ? any controller errors ?
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beq 3$
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beq 3$
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mov #<rp.fcl+rp.go>,@#rp.cs1 ; than do drive clear
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mov #<rp.fcl+rp.go>,@#rp.cs1 ; than do drive clear
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;
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;
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3$: bit #rp.tre,@#rp.cs1 ; cs1.tre = 1 ? any transfer errors ?
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3$: bit #rp.tre,@#rp.cs1 ; cs1.tre = 1 ? any transfer errors ?
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beq 4$
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beq 4$
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mov #rp.tre,@#rp.cs1 ; if yes, clear them with tre=1 write
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mov #rp.tre,@#rp.cs1 ; if yes, clear them with tre=1 write
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;
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;
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4$: mov #fbuf,r0 ; store final regs in fbuf
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4$: mov #fbuf,r0 ; store final regs in fbuf
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mov @#rp.cs1,(r0)+ ; cs1
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mov @#rp.cs1,(r0)+ ; cs1
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mov @#rp.cs2,(r0)+ ; cs2
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mov @#rp.cs2,(r0)+ ; cs2
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mov @#rp.er1,(r0)+ ; er1
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mov @#rp.er1,(r0)+ ; er1
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mov @#rp.ds,(r0)+ ; ds
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mov @#rp.ds,(r0)+ ; ds
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mov @#rp.as,(r0)+ ; as
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mov @#rp.as,(r0)+ ; as
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halt ; halt if done
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halt ; halt if done
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stop:
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stop:
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;
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;
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clr pcnt ; clear pcnt again
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clr pcnt ; clear pcnt again
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mov #obuf,r0 ; clear obuf again
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mov #obuf,r0 ; clear obuf again
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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clr (r0)+
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;
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;
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mov #rp.ie,@#rp.cs1 ; re-enable interrupt
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mov #rp.ie,@#rp.cs1 ; re-enable interrupt
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br poll
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br poll
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; RHRP interrupt handler
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; RHRP interrupt handler
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vh.rp: mov #obuf,r0 ; store regs in obuf
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vh.rp: mov #obuf,r0 ; store regs in obuf
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mov @#rp.cs1,(r0)+ ; cs1
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mov @#rp.cs1,(r0)+ ; cs1
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mov @#rp.cs2,(r0)+ ; cs2
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mov @#rp.cs2,(r0)+ ; cs2
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mov @#rp.er1,(r0)+ ; er1
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mov @#rp.er1,(r0)+ ; er1
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mov @#rp.ds,(r0)+ ; ds
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mov @#rp.ds,(r0)+ ; ds
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mov @#rp.as,r1 ;
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mov @#rp.as,r1 ;
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mov r1,(r0)+ ; as
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mov r1,(r0)+ ; as
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mov r5,(r0)+ ; int delay
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mov r5,(r0)+ ; int delay
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;
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;
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1$: tst icnt ; test first interrupt
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1$: tst icnt ; test first interrupt
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beq 2$ ; if yes quit
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beq 2$ ; if yes quit
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mov r1,@#rp.as ; if not, clear as
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mov r1,@#rp.as ; if not, clear as
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2$: inc icnt ; count interrupts
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2$: inc icnt ; count interrupts
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rti ; and return
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rti ; and return
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}
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}
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##puts $lst
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##puts $lst
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# define tmpproc for readback checks
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# define tmpproc for readback checks
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proc tmpproc_dotest {cpu symName opts} {
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proc tmpproc_dotest {cpu symName opts} {
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upvar 1 $symName sym
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upvar 1 $symName sym
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set tout 10.; # FIXME_code: parameter ??
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set tout 10.; # FIXME_code: parameter ??
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# setup defs hash, first defaults, than write over concrete run values
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# setup defs hash, first defaults, than write over concrete run values
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array set defs { i.cs2 0 \
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array set defs { i.cs2 0 \
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i.da 0 \
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i.da 0 \
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i.dc 0 \
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i.dc 0 \
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i.cs1 0 \
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i.cs1 0 \
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i.idly 0 \
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i.idly 0 \
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o.cs1 0 \
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o.cs1 0 \
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o.cs2 0 \
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o.cs2 0 \
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o.er1 0 \
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o.er1 0 \
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o.ds 0 \
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o.ds 0 \
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o.as 0 \
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o.as 0 \
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o.itim 10 \
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o.itim 10 \
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o.icnt 0 \
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o.icnt 0 \
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o.pcnt 1 \
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o.pcnt 1 \
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or.cs1 0 \
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or.cs1 0 \
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or.cs2 0 \
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or.cs2 0 \
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or.er1 0 \
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or.er1 0 \
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or.ds 0 \
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or.ds 0 \
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or.as 0 \
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or.as 0 \
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or.icnt 0 \
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or.icnt 0 \
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or.pcnt 1 \
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or.pcnt 1 \
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do.rint 0 \
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do.rint 0 \
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do.lam 0
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do.lam 0
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}
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}
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array set defs $opts
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array set defs $opts
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# build ibuf
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# build ibuf
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set ibuf [list $defs(i.cs2) $defs(i.da) $defs(i.dc) $defs(i.cs1) \
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set ibuf [list $defs(i.cs2) $defs(i.da) $defs(i.dc) $defs(i.cs1) \
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$defs(do.rint)]
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$defs(do.rint)]
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# setup idly, write ibuf, setup stack, and start cpu at start:
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# setup idly, write ibuf, setup stack, and start cpu at start:
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$cpu cp -wibr rpa.cs1 [regbld ibd_rhrp::RCS1 \
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$cpu cp -wibr rpa.cs1 [regbld ibd_rhrp::RCS1 \
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[list val $defs(i.idly)] \
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[list val $defs(i.idly)] \
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[list func $ibd_rhrp::RFUNC_WIDLY] ] \
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[list func $ibd_rhrp::RFUNC_WIDLY] ] \
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-wal $sym(ibuf) \
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-wal $sym(ibuf) \
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-bwm $ibuf \
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-bwm $ibuf \
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-wsp $sym(stack) \
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-wsp $sym(stack) \
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-stapc $sym(start)
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-stapc $sym(start)
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# here do minimal lam handling (harvest + send DONE)
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# here do minimal lam handling (harvest + send DONE)
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if {$defs(do.lam)} {
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if {$defs(do.lam)} {
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rlc wtlam $tout apat
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rlc wtlam $tout apat
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$cpu cp -attn \
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$cpu cp -attn \
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-wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_DONE]
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-wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_DONE]
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}
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}
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$cpu wtcpu -reset $tout
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$cpu wtcpu -reset $tout
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# determine regs after cleanup
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# determine regs after cleanup
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set cs1msk [rutil::com16 [regbld ibd_rhrp::CS1 {func -1}]]
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set cs1msk [rutil::com16 [regbld ibd_rhrp::CS1 {func -1}]]
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set fcs2 [expr {$defs(o.cs2) & 0x00ff}]; # cs1.tre clears upper byte !
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set fcs2 [expr {$defs(o.cs2) & 0x00ff}]; # cs1.tre clears upper byte !
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set fer1 0
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set fer1 0
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if {!$defs(do.rint)} { # no reinterrupt, ata clear by cpu
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if {!$defs(do.rint)} { # no reinterrupt, ata clear by cpu
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set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 sc tre {func -1}] }]
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set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 sc tre {func -1}] }]
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set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS ata erp] }]
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set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS ata erp] }]
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set fas 0
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set fas 0
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} else { # reinterrupt, ata still pending
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} else { # reinterrupt, ata still pending
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set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 tre {func -1}] }]
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set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 tre {func -1}] }]
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set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS erp] }]
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set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS erp] }]
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set fas $defs(o.as)
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set fas $defs(o.as)
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}
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}
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$cpu cp -rpc -edata $sym(stop) \
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$cpu cp -rpc -edata $sym(stop) \
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-rsp -edata $sym(stack) \
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-rsp -edata $sym(stack) \
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-wal $sym(icnt) \
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-wal $sym(icnt) \
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-rmi -edata $defs(o.icnt) \
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-rmi -edata $defs(o.icnt) \
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-rmi \
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-rmi \
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-rmi -edata $defs(o.cs1) \
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-rmi -edata $defs(o.cs1) \
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-rmi -edata $defs(o.cs2) \
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-rmi -edata $defs(o.cs2) \
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-rmi -edata $defs(o.er1) \
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-rmi -edata $defs(o.er1) \
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-rmi -edata $defs(o.ds) \
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-rmi -edata $defs(o.ds) \
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-rmi -edata $defs(o.as) \
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-rmi -edata $defs(o.as) \
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-rmi -edata $defs(o.itim) \
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-rmi -edata $defs(o.itim) \
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-rmi -edata $fcs1 $cs1msk \
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-rmi -edata $fcs1 $cs1msk \
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-rmi -edata $fcs2 \
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-rmi -edata $fcs2 \
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-rmi -edata $fer1 \
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-rmi -edata $fer1 \
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-rmi -edata $fds \
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-rmi -edata $fds \
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-rmi -edata $fas
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-rmi -edata $fas
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if {!$defs(do.rint)} return "";
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if {!$defs(do.rint)} return "";
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$cpu cp -start
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$cpu cp -start
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$cpu wtcpu -reset $tout
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$cpu wtcpu -reset $tout
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# determine regs after cleanup
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# determine regs after cleanup
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set fcs1 [expr {$defs(or.cs1) & ~[regbld ibd_rhrp::CS1 sc] }]
|
set fcs1 [expr {$defs(or.cs1) & ~[regbld ibd_rhrp::CS1 sc] }]
|
set fcs2 $defs(or.cs2)
|
set fcs2 $defs(or.cs2)
|
set fer1 0
|
set fer1 0
|
set fds [expr {$defs(or.ds) & ~[regbld ibd_rhrp::DS ata] }]
|
set fds [expr {$defs(or.ds) & ~[regbld ibd_rhrp::DS ata] }]
|
set fas 0
|
set fas 0
|
|
|
$cpu cp -rpc -edata $sym(stop) \
|
$cpu cp -rpc -edata $sym(stop) \
|
-rsp -edata $sym(stack) \
|
-rsp -edata $sym(stack) \
|
-wal $sym(icnt) \
|
-wal $sym(icnt) \
|
-rmi -edata $defs(or.icnt) \
|
-rmi -edata $defs(or.icnt) \
|
-rmi \
|
-rmi \
|
-rmi -edata $defs(or.cs1) \
|
-rmi -edata $defs(or.cs1) \
|
-rmi -edata $defs(or.cs2) \
|
-rmi -edata $defs(or.cs2) \
|
-rmi -edata $defs(or.er1) \
|
-rmi -edata $defs(or.er1) \
|
-rmi -edata $defs(or.ds) \
|
-rmi -edata $defs(or.ds) \
|
-rmi -edata $defs(or.as) \
|
-rmi -edata $defs(or.as) \
|
-rmi \
|
-rmi \
|
-rmi -edata $fcs1 \
|
-rmi -edata $fcs1 \
|
-rmi -edata $fcs2 \
|
-rmi -edata $fcs2 \
|
-rmi -edata $fer1 \
|
-rmi -edata $fer1 \
|
-rmi -edata $fds \
|
-rmi -edata $fds \
|
-rmi -edata $fas
|
-rmi -edata $fas
|
|
|
return ""
|
return ""
|
}
|
}
|
|
|
# discard pending attn to be on save side
|
# discard pending attn to be on save side
|
rlc wtlam 0.
|
rlc wtlam 0.
|
rlc exec -attn
|
rlc exec -attn
|
|
|
# -- Section A ---------------------------------------------------------------
|
# -- Section A ---------------------------------------------------------------
|
rlc log " A -- function basics ----------------------------------------------"
|
rlc log " A -- function basics ----------------------------------------------"
|
rlc log " A1: test rdy and ie logic ---------------------------------"
|
rlc log " A1: test rdy and ie logic ---------------------------------"
|
rlc log " A1.1 set cs1.ie=1 alone -> no interrupt ------------"
|
rlc log " A1.1 set cs1.ie=1 alone -> no interrupt ------------"
|
|
|
# Note: no interrupt, so ie stays on !
|
# Note: no interrupt, so ie stays on !
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie] \
|
o.icnt 0 \
|
o.icnt 0 \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie] \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry] \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry] \
|
o.as 0 \
|
o.as 0 \
|
o.itim 0
|
o.itim 0
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A1.2 set cs1.ie=1 with rdy=1 -> software interrupt -"
|
rlc log " A1.2 set cs1.ie=1 with rdy=1 -> software interrupt -"
|
|
|
# Note: interrupt, so ie switched off again !
|
# Note: interrupt, so ie switched off again !
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 rdy ie] \
|
i.cs1 [regbld ibd_rhrp::CS1 rdy ie] \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy] \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry] \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry] \
|
o.as 0 \
|
o.as 0 \
|
o.itim 1
|
o.itim 1
|
]
|
]
|
|
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A2: test state functions: iff no, as yes ------------------"
|
rlc log " A2: test state functions: iff no, as yes ------------------"
|
rlc log " A2.1 noop function ---------------------------------"
|
rlc log " A2.1 noop function ---------------------------------"
|
|
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie go] \
|
o.cs1 [regbld ibd_rhrp::CS1 ie dva rdy] \
|
o.cs1 [regbld ibd_rhrp::CS1 ie dva rdy] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry] \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry] \
|
o.as 0 \
|
o.as 0 \
|
o.itim 0
|
o.itim 0
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A2.2 pack acknowledge function (sets ds.vv=1) ------"
|
rlc log " A2.2 pack acknowledge function (sets ds.vv=1) ------"
|
|
|
set rbcs1func [list func $ibd_rhrp::FUNC_PACK]
|
set rbcs1func [list func $ibd_rhrp::FUNC_PACK]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func ie go] \
|
i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func ie go] \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \
|
o.as 0 \
|
o.as 0 \
|
o.itim 0
|
o.itim 0
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A3: test seek type functions: iff no, as yes --------------"
|
rlc log " A3: test seek type functions: iff no, as yes --------------"
|
|
|
rlc log " A3.1 seek function, ie=0, valid da,dc---------------"
|
rlc log " A3.1 seek function, ie=0, valid da,dc---------------"
|
|
|
# check that cs1.sc=1, ds.ata=1, and as.u0=1
|
# check that cs1.sc=1, ds.ata=1, and as.u0=1
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK]
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func go] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.itim 0
|
o.itim 0
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A3.2 seek function, valid da,dc, idly=0 ------------"
|
rlc log " A3.2 seek function, valid da,dc, idly=0 ------------"
|
|
|
# check re-interrupt too
|
# check re-interrupt too
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK]
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.dc 814 \
|
i.dc 814 \
|
i.idly 0 \
|
i.idly 0 \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.itim 1 \
|
o.itim 1 \
|
do.rint 1 \
|
do.rint 1 \
|
or.icnt 2 \
|
or.icnt 2 \
|
or.cs1 [regbld ibd_rhrp::CS1 sc dva rdy] \
|
or.cs1 [regbld ibd_rhrp::CS1 sc dva rdy] \
|
or.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
or.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
or.er1 0 \
|
or.er1 0 \
|
or.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
or.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
or.as [regbld ibd_rhrp::AS u0]
|
or.as [regbld ibd_rhrp::AS u0]
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A3.3 seek function, invalid dc ---------------------"
|
rlc log " A3.3 seek function, invalid dc ---------------------"
|
|
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK]
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.dc 815 \
|
i.dc 815 \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 [regbld ibd_rhrp::ER1 iae] \
|
o.er1 [regbld ibd_rhrp::ER1 iae] \
|
o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.itim 1
|
o.itim 1
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A3.4 search function, valid da,dc, idly=0 ----------"
|
rlc log " A3.4 search function, valid da,dc, idly=0 ----------"
|
|
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.dc 0 \
|
i.dc 0 \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \
|
i.idly 0 \
|
i.idly 0 \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.itim 1
|
o.itim 1
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A3.5 search function, valid da,dc, idly=2 ----------"
|
rlc log " A3.5 search function, valid da,dc, idly=2 ----------"
|
|
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.dc 0 \
|
i.dc 0 \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \
|
i.idly 2 \
|
i.idly 2 \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.itim 3
|
o.itim 3
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A3.5 search function, valid da,dc, idly=8 ----------"
|
rlc log " A3.5 search function, valid da,dc, idly=8 ----------"
|
|
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.dc 0 \
|
i.dc 0 \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \
|
i.idly 8 \
|
i.idly 8 \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 0 \
|
o.er1 0 \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.itim 9
|
o.itim 9
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A3.5 search function, invalid sa, idly=8 -----------"
|
rlc log " A3.5 search function, invalid sa, idly=8 -----------"
|
# Note: idly is 8, but error ata's come immediately !!
|
# Note: idly is 8, but error ata's come immediately !!
|
|
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.dc 0 \
|
i.dc 0 \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 22}] \
|
i.da [regbld ibd_rhrp::DA {ta 0} {sa 22}] \
|
i.idly 8 \
|
i.idly 8 \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.er1 [regbld ibd_rhrp::ER1 iae] \
|
o.er1 [regbld ibd_rhrp::ER1 iae] \
|
o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.as [regbld ibd_rhrp::AS u0] \
|
o.itim 1
|
o.itim 1
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
rlc log " A4: test transfer functions: iff yes, as no ---------------"
|
rlc log " A4: test transfer functions: iff yes, as no ---------------"
|
rlc log " A4.1 read function, valid da,dc --------------------"
|
rlc log " A4.1 read function, valid da,dc --------------------"
|
|
|
set rbcs1func [list func $ibd_rhrp::FUNC_READ]
|
set rbcs1func [list func $ibd_rhrp::FUNC_READ]
|
set opts [list \
|
set opts [list \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \
|
o.icnt 1 \
|
o.icnt 1 \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy $rbcs1func] \
|
o.cs1 [regbld ibd_rhrp::CS1 dva rdy $rbcs1func] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.cs2 [regbld ibd_rhrp::CS2 or ir] \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \
|
o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \
|
do.lam 1
|
do.lam 1
|
]
|
]
|
tmpproc_dotest $cpu sym $opts
|
tmpproc_dotest $cpu sym $opts
|
|
|
|
|
